Atmel Corporation Product Training. FPGA/Configurator. Guy Lafayette/Itsu Wang/Yad Dhami

Size: px
Start display at page:

Download "Atmel Corporation Product Training. FPGA/Configurator. Guy Lafayette/Itsu Wang/Yad Dhami"

Transcription

1 Atmel Corporation 2004 Product Training FPGA/Configurator Guy Lafayette/Itsu Wang/Yad Dhami

2 A full spectrum of density & package options

3 What is a Configurator?? It is a NVM memory used to configure all SRAM based FPGA, FPSLIC and some DSP - Atmel, Xilinx, Altera, Cypress, Lattice ( Lucent) Also called PROM by Xilinx and Serial configuration device by Altera. All ATMEL parts are reprogrammable via simple 2- wire interface Competition in most cases are OTP ( One Time Programmable) It is sold between 10%-25% of FPGA price making it good business for a simple memory >>> ATMEL HAS A SOLUTION

4 FPGA Configuration Memories: a complete offer Part Number Density Target Market Features AT17LV 65K upto 4M Xilinx, Altera ISP/eeprom AT17N 256K upto 4M Xilinx Spartan2/3 limited write cycles AT17F 4M upto 32M Xilinx Virtex/ Altera Apex ISP/Flash "C" = 8-LAP "P" = 8-PDIP "N" = 8-SOIC "J" = 20-PLCC "S" = 20-SOIC "Q" = 32-TQFP "BJ" = 44-PLCC "TQ" = 44-TQFP Some examples.. 44 TQFP -- AT17LV040-10TQC 8 LAP -- AT17LV512-10CC ISP Reprogrammable FPGA configuration memory ATMEL,Altera, Xilinx 6mm 6mm LAP is 6 mm 2 with the same pinout and footprint as V08 and S08 8-lead (SOIC) packages. Like V08 LAP is 1 mm thick.

5 New!!: Low cost Configurator family Why do we need Low cost option - new Low cost FPGA: Spartan from Xilinx and Cyclone from Altera Reduced features to lower the cost (15%-30%) - limited number of write cycle ( ~10) - no ready pin, no cascade, 3.3volt only, limited package option - Easy for factory programming for volume PN: AT17N, N for N Time Programmable Density and package options: - from 256K up to 4Meg, 8DIP, 8SOIC/LAP, 20SOIC, 44TQFP In Full production now >> Target all Xilinx Spartan2/2E/3 PROM

6 New!!: High Density Configurators Offer More Features for Less $$ ATMEL FLASH technology : from 4M up to 32M 8-lead LAP package for 4M, 8M, and 16M(same footprint as 8-SOIC) Page Select pins option: 4 Pages available to store different versions of FPGA bit stream Support 2-wire ISP protocol 33 MHz clock speed No need to go to OTP for cost reduction >> Target all Xilinx Virtex/ Altera Stratix PROM

7 AT17 Package offering Configurator All Xilinx Xilinx Spartan2 and Spartan3 NEW! Altera Pinout 65K-256K 512K 1M 2M NEW! NEW! NEW! NEW! 4M 8M 16M 32M AT17LVXX-10 AT17FXX-30 8 LAP 8 LAP 8 LAP 8 LAP 8 LAP 8 LAP 8 LAP 8 PDIP 8 PDIP 8 PDIP 20 SOIC 20 SOIC 20 SOIC 20 SOIC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 44 TQFP 44 TQFP 44 TQFP 44 TQFP 44 PLCC 44 PLCC 44 PLCC 44 PLCC 44 PLCC AT17NXX-10 8 PDIP(*) 8 PDIP 8 PDIP (*) Only 256K offered 8 SOIC(*) 8 LAP 8 LAP 8 LAP 20 SOIC(*) 20 SOIC 20 SOIC 20 SOIC 44 TQFP 44 TQFP AT17LVXXA-10 AT17FXXA-30 8 PDIP 8 PDIP 8 PDIP 8 LAP 8 LAP 8 LAP 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 20 PLCC 32 TQFP 32 TQFP 32 TQFP 32 TQFP 44PLCC 44PLCC

8 Techno AT17LV: EEprom AT17N: NTP AT17F:Flash Part Number AT17F16A-30CI Density 65 : 65Kbit 128 : 128Kbit 256 : 256Kbit 512 : 512Kbit 010 : 1Mbit 002 : 2Mbit 040 : 4Mbit 080 : 8Mbit 16 : 16Mbit 32 : 32Mbit Vendor type A: Altera Blank: Xilinx Speed 10: 10Mhz 30: 33Mhz Temperature C: Commercial I: Industrial Package C: 8-LAP P : 8-PDIP N:8-SOIC J :20-PLCC S :20-SOIC Q : 32-TQFP BJ : 44-PLCC TQ : 44-TQFP Get latest cross ref from psli@atmel.com

9 So how do we identify the opportunities? 1. Look for the customers who are currently using Xilinx or Altera FPGA? If YES 2. Which configurator do they use? (write down the list) 3. Use the cross reference guide to identify ATMEL equivalent or Send an to 4. For new design, use second portion of the cross reference guide to see which FPGA they are using and offer them the corresponding Atmel Configurator.

10 Configurator Cross Reference Guide Pin-to-pin is drop-in replacement. No modification is needed. Not Pin-to-pin Compatible, but functionality is the same. Pinout is different, but the functionality for the Master Serial Mode is the same.

11 Configurator Cross Reference Guide Configurator FPGA

12 Competitive Advantages Vs. Xilinx PROMs Vs. Platform Flash(XCFxxS). Platform Flash offers only 1 package per density while Atmel Flash PROMs are offered in variety of packages(8, 20, 44 pin packages). Vs. Legacy PROMs. Again Atmel has advantages in package offering(xc18v s smallest package is 20SOIC). Atmel has the broadest 8 pin offerings - 8SOIC is only offered in XC17V01! XC17V02 and up are not offered in 8 pin packages. Vs. System ACE. Average cost of $3 per Mbits. Multi- Chip solution which will increase board space. >> Xilinx PROM revenue ~ $70M ( estimated in 2003)

13 Packages Competitive Advantage Vs. Altera Configuration solutions Vs. EPC1441, EPC1, and EPC2. EPC1441 & EPC1 do not support ISP, they are OTP!! EPC2 is 1.69Mbits while Atmel AT17LV002 is full 2Mbits!! Vs. Enhanced Configuration Device (EPC4 to EPC16). They offered in 100PQFP only! Atmel offers 8LAP, 20PLCC, and 32TQFP. Vs. Cyclone Configurators (EPCS1 & EPCS4). Complex ISP using the FPGA itself, only supports AS mode and only 1 package option. Altera 8 pin solutions are OTP ONLY!! >> Altera serial config revenue ~ $40M ( estimated in 2003)

14 Other Competitive Advantages Data Retention of 190 years on AT17LVxxx series (Xilinx has 20 years) 100,000 cycle write times for AT17LVxxx 10,000 cycle write times for AT17Fxxx Wider voltage range support (3.0V to 5.5V) 8 pin package from 65K upto 16M Atmel offers 1. Factory programming 2. Custom markings 3. Tape and Reel

15 ATDH2200E Configurator Programming Kit Programmer kit for AT17LVxxx, AT17Nxxx, and AT17Fxxx - AT17 sample and ISP programming board - Parallel cable and power supply - PC download programming S/W - Socket adapters: ATDH2221 for all 20 pin SOIC ATDH2222 for 20 pin PLCC (included) ATDH2223 for 8 pin SOIC ATDH2224 for 44 pin TQFP ATDH2226 for 32 pin PQFP ATDH2227 for 44 pin PLCC ATDH2228 for 8 pin LAPD - Supported in IDS and System Designer» DOWNLOAD->CONFIGURATOR - In-stock and shipping NOW - $350 price inclusive

16 ATDH2225 ISP Programming Cable ISP prog. cable for AT17LVxxx, AT17Fxxx, and AT17Nxxx - Parallel port to programming header cable - Supported in IDS and SystemDesigner» DOWNLOAD->CONFIGURATOR - In-stock and shipping NOW - $95 10 pin ribbon cable ATDH2225 Programming cable TO PC parallel port

17 Configurator Programming Software (CPS) Takes files straight from Atmel, Xilinx, and Altera software Supports *.mcs, *.hex, *.bst, *.pof, *.rbf file format Enable and disable internal oscillator for AT17LVxxx series Supports AT17LVxxx, AT17Nxxx, and AT17Fxxx configurators Download from web fo free

18 Atmel s Configurator Roadmap AT18F AT18F Series Series JTAG programming Densities to to 64M 64M Serial and and Parallel mode 3.3V/1.8V 3.3V/1.8V JTAG (IEE1532 High Feature Set Features AT17LV AT17LV Series Series Density to to 8M 8M 8-pin 2-wire ISP ISP 3.3V 3.3V and and 5volt 5volt AT17F AT17F Series Series Density to to 32M 32M 2-wire ISP ISP 3.3V 3.3V Small package High Density AT17N AT17N Series Series Density to to 4M 4M 3.3V 3.3V Reduced features High Vo

19 Actions Required ASAP Target the big FPGA users: Nokia, Lucent, Marconi, Ericson, Alcatel, Siemens, Cisco, Dell, IBM, Nortel, Philips, Thomson, Samsung Visit the buyers and show them our cross reference Visit the designers and design in the new products Identify new high volume FPGA customers >> Remember configurator are high ASP parts and we have the best offer

20 Stay tuned and call if you need support: Guy for Europe: / glafayette@ Itsu for Asia : /iwang@ Yad for US : / ydhami@ Technical support configurator@atmel.com THANK YOU

ATDH2200E Programming Kit... User Guide

ATDH2200E Programming Kit... User Guide ATDH2200E Programming Kit... User Guide Table of Contents Section 1 Atmel s ATDH2200E Configurator Programming Kit... 1-1 1.1 Features...1-1 1.1.1 Hardware...1-1 1.1.2 Software...1-1 1.1.3 System Contents...1-1

More information

AT17A Series FPGA Configuration EEPROM Memory. Application Note. FPGAs. AT17A Series Conversions from Altera FPGA Serial Configuration Memories

AT17A Series FPGA Configuration EEPROM Memory. Application Note. FPGAs. AT17A Series Conversions from Altera FPGA Serial Configuration Memories ATA Series Conversions from Altera FPGA Serial Configuration Memories Introduction The Atmel ATA FPGA Configuration EEPROM () is a serial memory that can be used to load SRAM based FPGAs. This application

More information

FPGA Configurator Programming Kit (Enhanced) ATDH2200E. Features. Description

FPGA Configurator Programming Kit (Enhanced) ATDH2200E. Features. Description Features Hardware Supports Programming of all AT7LV and AT7F Series Devices Connection to Allow In-System Programming (ISP) Runs off Portable 9V DC Power Supply.0V Supply Software CPS Configurator Programming

More information

Atmel Corporation 2004 Product Training EPLD

Atmel Corporation 2004 Product Training EPLD Atmel Corporation 2004 Product Training EPLD Guy Lafayette/Itsu Wang/Yad Dhami EPLD Agenda 2003 EPLD Overview Simple PLDs (SPLD) Complex PLDs (CPLDs) Military PLDs Applications for PLDs Development Tool

More information

LOW-COST FPGA CONFIGURATION VIA INDUSTRY-STANDARD SPI SERIAL FLASH & LatticeECP/EC FPGAs

LOW-COST FPGA CONFIGURATION VIA INDUSTRY-STANDARD SPI SERIAL FLASH & LatticeECP/EC FPGAs LOW-COST FPGA CONFIGURATION VIA INDUSTRY-STANDARD SPI SERIAL FLASH & LatticeECP/EC FPGAs June 2004 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com

More information

AT17LV65A (1), AT17LV128A (1), AT17LV256A (1) AT17LV512A, AT17LV010A, AT17LV002A

AT17LV65A (1), AT17LV128A (1), AT17LV256A (1) AT17LV512A, AT17LV010A, AT17LV002A AT17LV65A, AT17LV128A, AT17LV256A AT17LV512A, AT17LV010A, AT17LV002A Note 1. AT17LV65A, AT17LV128A, and AT17LV256A are Not Recommended for New Designs (NRND) and are Replaced by AT17LV512A. Features FPGA

More information

FPGA Configuration EEPROM Memory AT17C65 AT17LV65 AT17C128 AT17LV128 AT17C256 AT17LV256

FPGA Configuration EEPROM Memory AT17C65 AT17LV65 AT17C128 AT17LV128 AT17C256 AT17LV256 Features EE Programmable 65,536 x 1-, 131,072 x 1-, and 262,144 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) In-System Programmable via 2-wire

More information

AT17 Series FPGA. Configuration Memory. Application Note. In-System Programming Circuits for AT17 Series Configurators with Atmel and Xilinx FPGAs

AT17 Series FPGA. Configuration Memory. Application Note. In-System Programming Circuits for AT17 Series Configurators with Atmel and Xilinx FPGAs In-System Circuits for AT1 Series Configurators with Atmel and Xilinx s Atmel AT1 (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable Gate Arrays (s)

More information

AT17F040A and AT17F080A

AT17F040A and AT17F080A AT17F040A and AT17F080A FPGA Configuration Flash Memory DATASHEET Features Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market

More information

AT17(A) Series FPGA Configuration Memory. Application Note

AT17(A) Series FPGA Configuration Memory. Application Note Cascaded Programming Circuits using AT1(A) Configurators with Atmel, Xilinx and Altera FPGAs Atmel AT1A (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable

More information

FPGA Configuration Flash Memory AT17F16

FPGA Configuration Flash Memory AT17F16 Features Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) 3.3V Output Capability 5V Tolerant I/O Pins Program Support

More information

AT17LV(A) Series FPGA Configuration Memory. Application Note. Programming Specification for AT17LV(A) Series FPGA Configuration Memories

AT17LV(A) Series FPGA Configuration Memory. Application Note. Programming Specification for AT17LV(A) Series FPGA Configuration Memories Programming Specification for AT17LV(A) Series FPGA Configuration Memories The FPGA Configurator The FPGA Configurator is a serial EEPROM memory that can also be used to load programmable devices. This

More information

Platform Flash In-System Programmable Configuration PROMs

Platform Flash In-System Programmable Configuration PROMs R 0 Platform Flash In-System Programmable Configuration PROMs DS123 (v2.2) December 15, 2003 0 0 Preliminary Product Specification Features In-System Programmable PROMs for Configuration of Xilinx FPGAs

More information

Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles

Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles Class 330 Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles Steven Knapp (sknapp) Arye Ziklik (arye) Triscend Corporation www.triscend.com Copyright 1998,

More information

FPGA Configuration EEPROM Memory AT17C020A AT17LV020A

FPGA Configuration EEPROM Memory AT17C020A AT17LV020A Features Serial EEPROM Family for Configuring Altera FLEX Devices Simple Interface to SRAM FPGAs EE Programmable 2M-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate

More information

Field Programmable Gate Array (FPGA) Devices

Field Programmable Gate Array (FPGA) Devices Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs

More information

Configuring Cyclone FPGAs

Configuring Cyclone FPGAs Configuring Cyclone FPGAs March 2003, ver. 1.1 Application Note 250 Introduction You can configure Cyclone TM FPGAs using one of several configuration schemes, including the new active serial (AS) configuration

More information

Section II. Software Settings

Section II. Software Settings Section II. Software Settings Configuration options can be set in the Quartus II and MAX+PLUS II development software. You can also specify which configuration file formats Quartus II or MAX+PLUS II generates.

More information

FPGA Discovery-III XC3S200 Board Manual

FPGA Discovery-III XC3S200 Board Manual FPGA Discovery-III XC3S200 Board Manual 77/9 SOI LADPRAO 1, LADPRAO ROAD, JOMPOL, JATUJAK DISTRICT, BANGKOK THAILAND 10900 TEL. 66(0)2939-2084 FAX.66(0)2939-2084 http://www.ailogictechnology.com 1 FPGA

More information

High-Tech-Marketing. Selecting an FPGA. By Paul Dillien

High-Tech-Marketing. Selecting an FPGA. By Paul Dillien High-Tech-Marketing Selecting an FPGA By Paul Dillien The Market In 2011 the total PLD market was $4.97B The FPGA portion was worth $4.1B 2 FPGA Applications The dominant applications have always been

More information

Platform Flash In-System Programmable Configuration PROMs

Platform Flash In-System Programmable Configuration PROMs 0 Platform Flash In-System Programmable Configuration s DS123 (v2.1) November 18, 2003 0 0 Preliminary Product Specification Features In-System Programmable s for Configuration of Xilinx FPGAs Low-Power

More information

4. Configuring Cyclone II Devices

4. Configuring Cyclone II Devices 4. Configuring Cyclone II Devices CII51013-2.0 Introduction Cyclone II devices use SRAM cells to store configuration data. Since SRAM memory is volatile, configuration data must be downloaded to Cyclone

More information

8-megabit 2.5-volt or 2.7-volt DataFlash AT45DB081D

8-megabit 2.5-volt or 2.7-volt DataFlash AT45DB081D Features Single 2.5V or 2.7V to 3.6V Supply RapidS Serial Interface: 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 User Configurable Page Size 256 Bytes per Page 264 Bytes per Page Page Size

More information

16-megabit 2.5-volt or 2.7-volt DataFlash AT45DB161D

16-megabit 2.5-volt or 2.7-volt DataFlash AT45DB161D Features Single 2.5V - 3.6V or 2.7V - 3.6V Supply RapidS Serial Interface: 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 User Configurable Page Size 512 Bytes per Page 528 Bytes per Page

More information

Pin-Master 48. Everything you need from a development programmer

Pin-Master 48. Everything you need from a development programmer Pin-Master 48 Everything you need from a development programmer Device Types Over 8750 device types Includes 3V parts EPROMs, EEPROMs, FLASH EPROMs and Emulators up to 48 pins PLDs and FPGAs including

More information

Microchip Serial EEPROMs

Microchip Serial EEPROMs Questions: Microchip Serial EEPROMs Serial EEPROM advantages? Which EEPROM bus is best? Package options? Design tools? Pin limited? 2008 Microchip Technology Incorporated. All Rights Reserved. EEPROM Overview

More information

5. Configuring Cyclone FPGAs

5. Configuring Cyclone FPGAs 5. Configuring Cyclone FPGAs C51013-1.5 Introduction You can configure Cyclone TM FPGAs using one of several configuration schemes, including the active serial (AS) configuration scheme. This scheme is

More information

EE4380 Microprocessor Design Project

EE4380 Microprocessor Design Project EE4380 Microprocessor Design Project Fall 2002 Class 1 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas Introduction What is a Microcontroller? Microcontroller

More information

INTRODUCTION TO FPGA ARCHITECTURE

INTRODUCTION TO FPGA ARCHITECTURE 3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)

More information

Features. Description. 4 2 Platform Flash In-System Programmable Configuration PROMS. DS123 (v2.6) March 14, Preliminary Product Specification

Features. Description. 4 2 Platform Flash In-System Programmable Configuration PROMS. DS123 (v2.6) March 14, Preliminary Product Specification 4 2 Platform Flash In-System Programmable Configuration PROMS DS123 (v2.6) March 14, 2005 0 Features In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR FLASH Process

More information

XAPP170 May 19, 1999 (Version 1.0) Application Note

XAPP170 May 19, 1999 (Version 1.0) Application Note XAPP170 May 19, 1999 (Version 1.0) Application Note Summary This application note illustrates the use of Spartan devices in an ISDN modem. The design example shows how cost effective a Spartan device can

More information

Trends in Prototyping Systems. ni logic Pvt. Ltd., Pune, India

Trends in Prototyping Systems. ni logic Pvt. Ltd., Pune, India Trends in Prototyping Systems ni logic Pvt. Ltd., Pune, India Focus of design dept. Electronic system & Flow Design problems Educating design Prototype USDP Features Applications Conclusion Agenda Faster

More information

FPGA Configuration EEPROM Memory AT17C65A AT17LV65A AT17C128A AT17LV128A AT17C256A AT17LV256A

FPGA Configuration EEPROM Memory AT17C65A AT17LV65A AT17C128A AT17LV128A AT17C256A AT17LV256A Features Serial EEPROM Family for Configuring Altera FLEX Devices In-System Programmable via 2-wire Bus Simple Interface to SRAM FPGAs EE Programmable 64K, 128K and 256K Bits Serial Memories Designed to

More information

Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs

Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs Implementing the Top Five Control-Path Applications with Low-Cost, Low-Power CPLDs WP-01146-1.2 White Paper Since their introduction in the mid-1980s and across all end markets, CPLDs have been design

More information

CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8

CHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8 CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram

More information

Serial EEPROM and Serial Flash for automotive applications

Serial EEPROM and Serial Flash for automotive applications Serial EEPROM and Serial Flash for automotive applications Selection guide www.st.com/eeprom www.st.com/serialflash Leading the way in serial non-volatile memories As a leader in serial EEPROM and an innovator

More information

Version 1.6 Page 2 of 25 SMT351 User Manual

Version 1.6 Page 2 of 25 SMT351 User Manual SMT351 User Manual Version 1.6 Page 2 of 25 SMT351 User Manual Revision History Date Comments Engineer Version 28/07/04 First revision JPA 1.1 16/09/04 Added pin number for JP1 pinout section. Updated

More information

F 2 MC-8FX Family. 8-bit Microcontroller. MB95200 Series

F 2 MC-8FX Family. 8-bit Microcontroller. MB95200 Series F 2 MC-8FX Family 8-bit Microcontroller The MB95200 series with a general-purpose low pin count package and built-in CR oscillator has been added to the product lineup of the 8-bit microcontroller 8FX

More information

Vertex Detector Electronics: ODE to ECS Interface

Vertex Detector Electronics: ODE to ECS Interface Vertex Detector Electronics: ODE to ECS Interface LHCb Technical Note Issue: 1 Revision: 0 Reference: LHCb 2000-012 VELO Created: 1 February 2000 Last modified: 20 March 2000 Prepared By: Yuri Ermoline

More information

AT17F Series. Application Note. Programming Circuits for AT17F Series Configurators with Xilinx FPGAs. 1. Introduction

AT17F Series. Application Note. Programming Circuits for AT17F Series Configurators with Xilinx FPGAs. 1. Introduction Programming Circuits for ATF Series s with Xilinx s. Introduction Atmel s ATF series Flash Configuration Memory devices use a simple serial-access procedure to configure one or more Xilinx Field Programmable

More information

AL8253 Core Application Note

AL8253 Core Application Note AL8253 Core Application Note 6-15-2012 Table of Contents General Information... 3 Features... 3 Block Diagram... 3 Contents... 4 Behavioral... 4 Synthesizable... 4 Test Vectors... 4 Interface... 5 Implementation

More information

Platform Flash In-System Programmable Configuration PROMs

Platform Flash In-System Programmable Configuration PROMs 48 Platform Flash In-System Programmable Configuration PROMs 0 Product Specification Features In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR Flash Process Endurance

More information

Platform Flash In-System Programmable Configuration PROMs

Platform Flash In-System Programmable Configuration PROMs Platform Flash In-System Programmable Configuration PROMs 0 Product Specification Features In-System Programmable PROMs for Configuration of Xilinx FPGAs Low-Power Advanced CMOS NOR FLASH Process

More information

Handouts. FPGA-related documents

Handouts. FPGA-related documents Handouts FPGA-related documents 1. Introduction to Verilog, Verilog P. M. Nyasulu and J. Knight, Carleton University, 2003 (Ottawa, Canada). 2. Quick Reference for Verilog HDL, HDL R. Madhavan, AMBIT Design

More information

Figure 2.1 The Altera UP 3 board.

Figure 2.1 The Altera UP 3 board. Figure 2.1 The Altera UP 3 board. USB Port PS-2 Port USB PHY Chip Heat Sink Parallel Port B B VGA Port I2C PROM Chip... JP19 Headers for I2C Bus Signals J3 Mounting Hole Santa Cruz Expansion Long Connector

More information

Spartan-II Demo Board User s Guide

Spartan-II Demo Board User s Guide Spartan-II Demo Board User s Guide Version.2 May 200 Overview The Spartan-II Demo Board is a low cost evaluation platform for testing and verifying designs based on the Xilinx Spartan-II family of FPGA

More information

24AA128/24LC128/24FC128

24AA128/24LC128/24FC128 18K I C CMOS Serial EEPROM Device Selection Table Part Number Range Max. Clock Frequency Temp. Ranges Temperature ranges: - Industrial (I): -0 C to +8 C - Automotive (E): -0 C to +1 C A8 1.-.V 00 khz (1)

More information

5M bytes free disk space Available parallel printer port

5M bytes free disk space Available parallel printer port The ATF1500AS Product Family ISP Board Atmel offers two options for customers that want to implement In-System Programming (ISP). The Atmel ISP kit is useful for customers that want to implement ISP in

More information

2-megabit 2.7-volt Minimum DataFlash AT45DB021D

2-megabit 2.7-volt Minimum DataFlash AT45DB021D Features Single 2.7V to 3.6V Supply RapidS Serial Interface: 66 MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 User Configurable Page Size 256 Bytes per Page 264 Bytes per Page Page Size Can

More information

Section I. FPGA Configuration Devices

Section I. FPGA Configuration Devices Section I. FPGA Configuration Devices This section provides information on Altera configuration devices. The following chapters contain information about how to use these devices, feature descriptions,

More information

AL8259 Core Application Note

AL8259 Core Application Note AL8259 Core Application Note 10-24-2012 Table of Contents General Information... 3 Features... 3 Block Diagram... 3 Contents... 4 A. Behavioral... 4 B. Synthesizable... 4 C. Test Vectors... 4 Interface...

More information

M32 Development Board

M32 Development Board M32 Development Board User Guide Document Control Information This Document Release Date: 12th March 2006 This Document Version: 1.0 Document History Author Release Date Reference Release Notes JSL 23rd

More information

Handouts. 1. Project Guidelines and DSP Function Generator Design Specifications. (We ll discuss the project at the beginning of lab on Wednesday)

Handouts. 1. Project Guidelines and DSP Function Generator Design Specifications. (We ll discuss the project at the beginning of lab on Wednesday) Handouts Project-related documents 1. Project Guidelines and DSP Function Generator Design Specifications. (We ll discuss the project at the beginning of lab on Wednesday) FPGA-related documents 2. Introduction

More information

XC95144 In-System Programmable CPLD

XC95144 In-System Programmable CPLD R 0 XC95144 In-System Programmable CPLD 0 5 Product Specification Features 7.5 ns pin-to-pin logic delays on all pins f CNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user pins 5V in-system

More information

QPro XQ17V16 Military 16Mbit QML Configuration PROM

QPro XQ17V16 Military 16Mbit QML Configuration PROM R 0 QPro XQ17V16 Military 16Mbit QML Configuration PROM DS111 (v1.0) December 15, 2003 0 8 Product Specification Features 16Mbit storage capacity Guaranteed operation over full military temperature range:

More information

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs. Features. Description

XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs. Features. Description 0 XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs December 10, 1997 (Version 1.1) 0 5* Product Specification Features On-chip address counter, incremented by each rising edge

More information

An Arduino Controlled 1 Hz to 60 MHz Signal Generator

An Arduino Controlled 1 Hz to 60 MHz Signal Generator An Arduino Controlled 1 Hz to 60 MHz Signal Generator Greg McIntire, AA5C AA5C@arrl.net WWW..ORG 1 Objectives Build a standalone 60 MHz signal generator based on the DDS-60 board. Originally controlled

More information

About using FPGAs in radiation environments

About using FPGAs in radiation environments About using FPGAs in radiation environments Tullio Grassi (FNAL / Univ. of MD) Motivations We may need some "glue logic" between the Front-End ASICs and the GBT (see talk from Chris Tully HB/HE Strawman

More information

System Designer. Programmable SLI AT94K/AT94S Series. Features. Description

System Designer. Programmable SLI AT94K/AT94S Series. Features. Description Features Atmel s System Designer Contains the Following Items: CD-ROM Containing all Necessary Software and Online Documents Atmel s AVR Studio Atmel s Configurator Programming System (CPS) Co-verification,

More information

Enabling success from the center of technology. A Practical Guide to Configuring the Spartan-3A Family

Enabling success from the center of technology. A Practical Guide to Configuring the Spartan-3A Family A Practical Guide to Configuring the Spartan-3A Family Goals 2 Explain advantages and disadvantages of each configuration mechanism available for Spartan-3A Show how to use an industry standard flash for

More information

QPRO Family of XC1700E Configuration PROMs

QPRO Family of XC1700E Configuration PROMs 11 QPRO Family of XC1700E Configuration PROMs Product Specification Features Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices

More information

Section 3. System Integration

Section 3. System Integration Section 3. System Integration This section includes the following chapters: Chapter 9, Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family Chapter 10, Hot-Socketing

More information

Embedded System Design

Embedded System Design Embedded System Design p. 1/2 Embedded System Design Prof. Stephen A. Edwards sedwards@cs.columbia.edu NCTU, Summer 2005 Spot the Computer Embedded System Design p. 2/2 Embedded System Design p. 3/2 Hidden

More information

SMT166-FMC User Guide

SMT166-FMC User Guide Sundance Multiprocessor Technology Limited Product Specification Unit / Module Description: Unit / Module Number: Document Issue Number: Issue Date: Original Author: SMT166-FMC User Guide Revision History

More information

5. Configuration Devices for SRAM-Based LUT Devices Data Sheet

5. Configuration Devices for SRAM-Based LUT Devices Data Sheet 5. Configuration Devices for SRAM-Based LUT Devices Data Sheet CF52005-2.1 Features Configuration device family for configuring Stratix series, Cyclone TM series, APEX TM II, APEX 20K (including APEX 20K,

More information

System Designer. Programmable SLI AT94K/AT94S Series. Features. Description

System Designer. Programmable SLI AT94K/AT94S Series. Features. Description Features Atmel s System Designer Contains the Following Items: CD-ROM Containing all Necessary Software and Online Documents Atmel s AVR Studio Atmel s Configurator Programming System (CPS) Co-verification,

More information

24AA16/24LC16B. 16K I 2 C Serial EEPROM. Device Selection Table. Description: Features: Package Types. Block Diagram. Temp. Ranges.

24AA16/24LC16B. 16K I 2 C Serial EEPROM. Device Selection Table. Description: Features: Package Types. Block Diagram. Temp. Ranges. 6K I C Serial EEPROM Device Selection Table Part Number Features: Vcc Range Max. Clock Frequency Temp. Ranges A6.7-. 00 khz () I LC6B.-. 00 khz I, E Note : 00 khz for

More information

Using the Nios Development Board Configuration Controller Reference Designs

Using the Nios Development Board Configuration Controller Reference Designs Using the Nios Development Board Controller Reference Designs July 2006 - ver 1.1 Application Note 346 Introduction Many modern embedded systems utilize flash memory to store processor configuration information

More information

Connecting Spansion SPI Serial Flash to Configure Altera FPGAs

Connecting Spansion SPI Serial Flash to Configure Altera FPGAs Connecting SPI Serial Flash to Configure Altera s Application By Frank Cirimele 1. Introduction Altera s are programmable logic devices used for basic logic functions, chip-to-chip connectivity, signal

More information

OVERVIEW ChipMax2 With high throughput and maximum flexibility Maxloader

OVERVIEW ChipMax2 With high throughput and maximum flexibility Maxloader OVERVIEW ChipMax2 is a high-speed universal device programmer for USB 2.0 PC-interface. It programs a 64Mbit flash memory in 42 seconds. This is a true low-price production oriented system. The ChipMax2

More information

Arduino Uno R3 INTRODUCTION

Arduino Uno R3 INTRODUCTION Arduino Uno R3 INTRODUCTION Arduino is used for building different types of electronic circuits easily using of both a physical programmable circuit board usually microcontroller and piece of code running

More information

ice65 mobilefpga Configuration & Programming Overview 05/12/2010

ice65 mobilefpga Configuration & Programming Overview 05/12/2010 ice65 mobilefpga Configuration & Programming Overview 05/12/2010 Configuration vs. Programming CONFIGURATION ice65 is a standard SRAM FPGA (reconfigurable) During power up, a configuration image is loaded

More information

address lines and a parallel interface, the Atmel DataFlash uses an Atmel RapidS serial interface to sequentially access its data. The simple sequenti

address lines and a parallel interface, the Atmel DataFlash uses an Atmel RapidS serial interface to sequentially access its data. The simple sequenti Features Single 2.5V or 2.7V to 3.6V Supply RapidS Serial Interface: 66MHz Maximum Clock Frequency SPI Compatible Modes 0 and 3 User Configurable Page Size 256-Bytes per Page 264-Bytes per Page Page Size

More information

Configuration Handbook, Volume 2

Configuration Handbook, Volume 2 Configuration Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com CF5V2-2.2 Copyright 2005 Altera Corporation. All rights reserved. Altera, The Programmable

More information

S2C K7 Prodigy Logic Module Series

S2C K7 Prodigy Logic Module Series S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device

More information

2-wire Serial EEPROM AT24C512. Preliminary. 2-Wire Serial EEPROM 512K (65,536 x 8) Features. Description. Pin Configurations.

2-wire Serial EEPROM AT24C512. Preliminary. 2-Wire Serial EEPROM 512K (65,536 x 8) Features. Description. Pin Configurations. Features Low-voltage and Standard-voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 1.8 (V CC = 1.8V to 3.6V) Internally Organized 65,536 x 8 2-wire Serial Interface Schmitt Triggers,

More information

FPGA Development Board Hardware and I/O Features

FPGA Development Board Hardware and I/O Features CHAPTER 2 FPGA Development Board Hardware and I/O Features Photo: The Altera DE1 board contains a Cyclone II FPGA, external SRAM, SDRAM & Flash memory, and a wide assortment of I/O devices and connectors.

More information

JTAG Interface : Common Pinouts

JTAG Interface : Common Pinouts Interface : Common Pinouts amt_ann003 (v1.1) Application Note OVERVIEW This Application Note resumes the Common interface pinouts used by the most popular manufacturers of processors, FPGAs or CPLDs devices

More information

CS310 Embedded Computer Systems. Maeng

CS310 Embedded Computer Systems. Maeng 1 INTRODUCTION (PART II) Maeng Three key embedded system technologies 2 Technology A manner of accomplishing a task, especially using technical processes, methods, or knowledge Three key technologies for

More information

PLAs & PALs. Programmable Logic Devices (PLDs) PLAs and PALs

PLAs & PALs. Programmable Logic Devices (PLDs) PLAs and PALs PLAs & PALs Programmable Logic Devices (PLDs) PLAs and PALs PLAs&PALs By the late 1970s, standard logic devices were all the rage, and printed circuit boards were loaded with them. To offer the ultimate

More information

Usable gates 600 1,250 2,500 5,000 10,000 Macrocells Logic array blocks Maximum user I/O

Usable gates 600 1,250 2,500 5,000 10,000 Macrocells Logic array blocks Maximum user I/O MAX 3000A Programmable Logic Device Family June 2006, ver. 3.5 Data Sheet Features... High performance, low cost CMOS EEPROM based programmable logic devices (PLDs) built on a MAX architecture (see Table

More information

4. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, & EPCS64) Features

4. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, & EPCS64) Features 4. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, & EPCS64) Features C51014-1.5 Introduction The serial configuration devices provide the following features: 1-, 4-, 16-, and 64-Mbit flash memory

More information

An Introduction to Programmable Logic

An Introduction to Programmable Logic Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor

More information

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROM

QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROM R DS126 (v1.0) December 18, 2003 0 8 Product Specification 0 QPro XQR17V16 Radiation Hardened 16Mbit QML Configuration PROM Features Latch-Up Immune to LET >120 MeV/cm 2 /mg Guaranteed TID of 50 krad(si)

More information

My First FPGA for Altera DE2-115 Board

My First FPGA for Altera DE2-115 Board My First FPGA for Altera DE2-115 Board 數位電路實驗 TA: 吳柏辰 Author: Trumen Outline Complete Your Verilog Design Assign The Device Add a PLL Megafunction Assign the Pins Create a Default TimeQuest SDC File Compile

More information

AT45DB041E. 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory. Features

AT45DB041E. 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory. Features 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory Features Single 1.65V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Supports RapidS

More information

Prof. Tit. José Renes Pinheiro, Dr. Eng. IX SACT November, 2000.

Prof. Tit. José Renes Pinheiro, Dr. Eng. IX SACT November, 2000. Introduction to rogrammable Logic Devices LD s and FA s rof. Tit. José Renes inheiro, Dr. ng. IX SAT November, 2000. 1 Jack Kilby (1958) first analog integrated circuit (I). Introduction 1960 Beginning

More information

2-wire Serial EEPROM AT24C512

2-wire Serial EEPROM AT24C512 Features Low-voltage and Standard-voltage Operation 5.0 (V CC = 4.5V to 5.5V). (V CC =.V to 5.5V). (V CC =.V to.v) Internally Organized 5,5 x -wire Serial Interface Schmitt Triggers, Filtered Inputs for

More information

1K-16K UNI/O Serial EEPROM Family Data Sheet

1K-16K UNI/O Serial EEPROM Family Data Sheet 11AA010/11LC010 11AA080/11LC080 11AA00/11LC00 11AA160/11LC160 11AA040/11LC040 1K-16K UNI/O Serial EEPROM Family Data Sheet Features: Single I/O, UNI/O Serial Interface Bus Low-Power CMOS Technology - 1

More information

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public

Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary

More information

Gate Estimate. Practical (60% util)* (1000's) Max (100% util)* (1000's)

Gate Estimate. Practical (60% util)* (1000's) Max (100% util)* (1000's) The Product Brief October 07 Ver. 1.3 Group DN9000K10PCIe-4GL XilinxVirtex-5 Based ASIC Prototyping Engine, 4-lane PCI Express (Genesys Logic PHYs) Features PCI Express (4-lane) logic prototyping system

More information

Altera EP4CE6 Mini Board. Hardware User's Guide

Altera EP4CE6 Mini Board. Hardware User's Guide Altera Hardware User's Guide 1. Introduction Thank you for choosing the! is a compact FPGA board which is designed based on device. It's a low-cost and easy-to-use platform for learning Altera's Cyclone

More information

Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL)

Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) 0 Spartan/XL Family One-Time Programmable Configuration PROMs (XC17S00/XL) 0 5 Product Specification Features Configuration one-time programmable (OTP) read-only memory designed to store configuration

More information

AVR FLASH MICROCONTROLLERS. Atmel Corporation

AVR FLASH MICROCONTROLLERS. Atmel Corporation AVR FLASH MICROCONTROLLERS Atmel Corporation General Introduction to AVR AVR Standard Products Existing and New General Purpose Microcontrollers JTAG, Self Programming, LCD interface LCD Interface - A

More information

Terasic DE0 Field Programmable Gate Array (FPGA) Development Board

Terasic DE0 Field Programmable Gate Array (FPGA) Development Board Lecture FPGA-01 DE0 FPGA Development Board and Quartus II 9.1 FPGA Design Software Terasic DE0 Field Programmable Gate Array (FPGA) Development Board 1 May 16, 2013 3 Layout and Components of DE0 May 16,

More information

VLSI Design Lab., Konkuk Univ. Yong Beom Cho LSI Design Lab

VLSI Design Lab., Konkuk Univ. Yong Beom Cho LSI Design Lab AVR Training Board-I V., Konkuk Univ. Yong Beom Cho ybcho@konkuk.ac.kr What is microcontroller A microcontroller is a small, low-cost computeron-a-chip which usually includes: An 8 or 16 bit microprocessor

More information

AT45DB021E. 2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum SPI Serial Flash Memory PRELIMINARY DATASHEET. Features

AT45DB021E. 2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum SPI Serial Flash Memory PRELIMINARY DATASHEET. Features AT45DB021E 2-Mbit DataFlash (with Extra 64-Kbits), 1.65V Minimum SPI Serial Flash Memory Features PRELIMINARY DATASHEET Single 1.65V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports

More information

ByteBlaster II Parallel Port Download Cable

ByteBlaster II Parallel Port Download Cable ByteBlaster II Parallel Port Download Cable December 2002, Version 1.0 Data Sheet Features Allows PC users to perform the following functions: Program MAX 9000, MAX 7000S, MAX 7000AE, MAX 7000B, MAX 3000A,

More information

Galep-4 Universal Programmer [ Parallel Port ]

Galep-4 Universal Programmer [ Parallel Port ] Galep-4 Universal Programmer [ Parallel Port ] PALMSIZED, 40 PIN PROGRAMMER Device Support: By name: 5,825. By package: 12,330 Dual power (AC adapter plus internal battery w/8 hours continuous operation

More information