Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles
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1 Class 330 Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles Steven Knapp (sknapp) Arye Ziklik (arye) Triscend Corporation Copyright 1998, Triscend Corporation. All rights reserved.
2 Agenda Forces Shaping Embedded Design Types of Design Solutions Programmable Technologies Technical Challenges
3 Key Forces Shaping Embedded Systems Time-to- Market Pressure Performance Embedded System Design Differentiation System Cost Pressure
4 Time-to-Market Why 'Configurable'? Fast iterations Fast in-system, real-time debugging Fast component availability Adaptability During design and debug In the field In the application Performance Match the architecture to the problem Fast response to real-time events Parallel operations Increased Differentiation
5 Types of Design Solutions Stand-Alone Processor Processor Derivative Processor + ASIC Processor + Programmable Logic Custom Processor in Programmable Logic Custom Processor in ASIC Configurable Processor System on a Chip
6 Embedded System Solutions High Low Hardware Customization Instruction Set Peripheral Set, System Architecture Custom Logic System on a chip Processor + ASIC System on a chip Processor + ASIC Configurable Logic (off the shelf) Roll your own in FPGA Configurable processor (on-chip accelerator) Processor + FPGA Configurable processor I/O, Interface, Processor + CPLD/FPGA Decoding Processor + ASIC Configurable processor Stand-alone processor or None - derivative Highest Customization Fast Time-to- Market
7 Increasing Functionality, Density, and Performance History of Configurable Technologies TTL Discrete Solutions MCU TTL TTL PAL RAM EPROM MCU Derivative MCU Derivative CPLD/ FPGA RAM ASIC MCU Derivatives and Programmable Logic EPROM/ FLASH "System on a Chip" Peripheral Peripheral Peripheral "Roll-Your- Own" MCU in FPGA Configurable Processors Configurable Processor EPROM EPROM/ FLASH Year 2000
8 Today's Configurable Technologies Complex Programmable Logic Devices (CPLD) Field Programmable Gate Arrays (FPGA) Hybrid Devices Processor interface Programmable logic Configurable Processors Integrated processor Programmable logic Dedicated on-chip bus On-chip memory
9 What is a CPLD? A function block is similar to a PAL or PLD Switch Matrix Function Block M.C. M.C. M.C. M.C. M.C. M.C. M.C. M.C. DQ Function Block Function Block Function Block Switch Matrix Macrocell Feedback Pin Feedback PAD
10 CPLD Vendors Company CPLDs PLDs/PALs Altera MAX Classic Xilinx XC Vantis MACH PAL Lattice plsi, GALs GAL Cypress Flash 370, PAL PAL Atmel ATF, ATV ATF TI - PAL Philips CoolRunner - ICT - PEEL See also:
11 What is an FPGA? PIO PIO PIO PIO PIO PIO PIO PIO Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block Logic Block PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO PIO L.C. L.C. Carry LUT/ RAM PIO PIO PIO PIO PIO PIO PIO PIO Logic Cell D Q EN CLR PIO PIO PIO PIO PIO PIO PIO PIO PIO
12 FPGA Vendors Process Technology Architecture Static Memory Anti-Fuse Flash Coarsegrained Finegrained Altera (FLEX) Xilinx (Spartan, 4KX, Virtex) Lucent (ORCA) Atmel (AT40K) Vantis (VF1) DynaChip QuickLogic (pasic) Atmel (AT6000) Actel (ACT, MX, SX) Gatefield See also:
13 Comparing CPLDs and FPGAs Key Attributes Typical Applications Design Timing Process Technology Power Consumption CPLDs Fast pin-to-pin delay Predictable timing Wide fan-in Easy to use Bus interfaces Complex state machines Fast memory interfaces Wide decoders PAL-device integration Usually fixed, PAL-like Fast pin-to-pin delays EPROM (OTP) EEPROM (some ISP) FLASH (some ISP) W static (some "zero power") W dynamic FPGAs Very high density Lots of I/Os and flip-flops Generally lower power Advanced features (RAM) Logic consolidation Board integration Replace obsolete devices Simple state machines Complex controllers Application dependent High internal performance SRAM (ISP) Anti-fuse (OTP) EEPROM (ISP) Very low static Dynamic consumption is application dependent, 0.1-2W typical See also:
14 Programmable Logic Market Data (Reference) Ranking Vendor Revenues Market (millions) '96-'97 Share Change Altera $ 631 $ % 31% 27% 2 Xilinx $ 574 $ % 28% 27% 3 Vantis $ 243 $ 248-2% 12% 13% 4 Lattice $ 237 $ 220 8% 11% 12% 5 Actel $ 156 $ 150 4% 8% 8% 6 Lucent $ 97 $ 91 7% 5% 5% 7 Cypress $ 52 $ 68-24% 3% 4% 8 Atmel $ 31 $ 27 15% 1% 1% 9 QuickLogic $ 29 $ 25 16% 1% 1% 10 TI $ 18 $ 23-22% 1% 1% TOTAL $ 2,068 $ 1,858 11% Source: Electronic Buyer s News, 30-MAR-98 The Programmable Logic Jump Station See also:
15 Hybrid Devices WSI Programmable System Device (PSD) 8- or 16-bit MCU interface CPLD-style macrocells on-chip memory Lucent ORCA 3 and 3+ FPGAs Motorola/IBM PowerPC interface Limited Intel 960 interface Limited connectivity to FPGA array
16 What Is a Configurable Processor? Industry-standard processor Dedicated bus Programmable Logic Soft peripherals User-defined functions Programmable I/O Programmable I/O Dedicated Processor Dedicated Peripherals Hardware Breakpoint System Bus Programmable I/O Programmable I/O RAM Programmable Logic Soft peripherals User logic Programmable I/O Hardware acceleration On-Chip Memory
17 Triscend E5 Configurable Processor Power Control Clock and Crystal Oscillator Control Power-On Reset Bus Arbiter Memory Interface Unit Address Mappers 8032 "Turbo" Microcontroller Twochannel DMA Controller Data Bus Address Bus Selector Selector Selector CSI Socket Configurable System Logic (CSL) Matrix Byte-wide System RAM Hardware Breakpoint Unit PIO PIO PIO PIO PIO PIO JTAG Interface Initialization Boot ROM Configurable System Interconnect (CSI) bus
18 Case Study: Our Own Derivative CaptureStrobe DebugCounter CounterClock Display_B Display_A INT1 CaptureHi CaptureMid CaptureLow 8032 Interrupt Controller INT0 24 TC 24BitCntr ENA RST 7 7 7seg 7seg 4 4 ReadSwitch CounterCtrl SevenSegment
19 Case Study: Technical Challenges Communication between the processor and programmable logic functions Maintaining a standard development flow Debugging a system with both processor and programmable logic
20 Communication between the Processor and Programmable Logic Routing data and address bus Decoding/controlling bus transactions Register intimacy Debugging
21 Processor Routing Bus Signals: FPGA Example DATA ADDR Write Decode CONTROL Read Decode I/Os between devices Many required, even for basic 8-bit interface) Adds delay to critical path Extra power consumption and EMI in two-chip solution Distributing address/data on-chip Uses programmable interconnect Adds delay to critical path Variable delays in some architectures Some devices provide bidirectional bussing
22 Another Approach: CSI Bus Socket (Configurable System Interconnect) 8032 "Turbo" Microcontroller 2-Channel DMA Controller Hardware Breakpoint Unit Side-band Signals Configurable System Interconnect (CSI) Bus CSI Socket Interface Data Write Data Read Address? Selectors Bus Clock DMA Request/ Acknowledge Wait-State Control Breakpoint Control Configurable System Logic (CSL) Matrix Distributes address and data to CSL matrix No additional I/O required Dedicated address decoding Predictable, synchronous timing Forward compatible with future configurable processors Wait-state control Contention-free bussing
23 Decoding Bus Transactions FPGA Style READ/ WRITE- A15 A14 A13 LUT LUT RDSEL LUT LUT WRSEL LUT LUT A0 LUT Decode delay is fan-out and routing dependent
24 Decoding Bus Transactions CPLD/PSD Style A0 A13 A14 A15 READ/ WRITE- RDSEL WRSEL Decode delay is constant
25 An CSI Bus Address Match0 Match1 Bus Clock RdSel Data Read [7:0] Decoding Bus Transactions A2 A1 A0 READ WRITE BCLK DATA Decode delay is constant (less than 5 ns after clock) CSI Selector Style RDSEL WRSEL Fast address decoding Any address range Access type Code Data Special Function Register (SFR) Three modes Selector Chip Select DMA Control Register Up to 200 selectors in a single device
26 Connecting the Two Development Worlds Hardware Development Design and soft module libraries Passing register addresses to compiler/assembler Vendor place and route software Device programming support System-wide insystem debugging support Software Development Compiler/assembler support Function libraries Instruction-set simulator System-wide insystem debugging support
27 Preserving Existing Tool Flow Configurable Processor Tools 1 System Configuration Header File MCU Development Tools 2 Program Development Soft Module Library 4 System Test and Debug Object File 3 Program Debug Source Code Library 5 Device Programming Designer s standard tool flow
28 Case Study Design: FastChip Software Soft Module Library Dedicated Resources Soft peripherals dragged into CSL matrix Resources Used Indicators
29 Real-Time, In-System Debugging Difficult in most ASIC or system-on-a-chip designs Must rely on simulation before completing design Most debuggers only support the processor Monitor bus activity Monitor processor registers Break on event and single-step Additional debugging desired for programmable logic functions Monitor the state of logic and flip-flops in soft peripherals Monitor or force a breakpoint from programmable logic
30 Summary Configurable embedded systems offer potential benefits: Faster time to market Higher performance compared to discrete solutions Higher product differentiation Configurable processors are a new class of single-chip programmable devices designed for embedded systems applications Industry-standard processor Dedicated, high-performance internal bus Programmable logic, connected to internal bus On-chip, high-density memory
31 Looking for More? (Booth 5010) Applications engineers available for questions Software demonstrations throughout the day CD-ROM with on-line tutorial and FastChip preview release Visit Roll Your Own RISC (Wednesday, 8:30, Class 402) Prototyping Embedded Microcontrollers in FPGAs (Wednesday, 4:00, Class 470) An Introduction to FPGA Design (Thursday, 8:30 and 10:30, Classes 509 and 529)
32 Questions?
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