TQPED MMIC Design Training

Transcription

1 TQPED MMIC Design Training Outline Installation and Use of the Library AWR AWR Design Kit (PDK Process Design Kit) ICED Layout Kit Create a new document using the Library Environment Setup Hotkeys Background color Element View Useful Shortcuts Element Placement Get familiar with the Design Manual Layers Process rules (transistor orientation) Layout Tips and running DRC Snapping things together, freezing objects, and restricting selection How to run DRC and address errors Rule list Simulation Tips and Axiem EM simulate passive structures Don t use extract block 3D View mesh to check for connectivity Utilize full wave data sets in the linear simulations Example Project Lumped element equivalent structures Probe pads and suggestions for measurements Advanced Drawing own capacitors Drawing own inductors 2 1

2 MMIC Design Accurately model your circuit (EM Simulation) Time constraints Leverage the capabilities of the software to tune your circuit Combine full wave simulations and linear models to speed up simulation time Process capabilities Can be more creative than what is offered in PDK as long as it obeys DRC 3 Outline Installation and use of the library Environment setup Getting familiar with the design manual Working with the layout and running DRC EM simulation with Axiem Example Project Advanced topics 4 2

3 Installing the Library (PDK) Install MWO (probably already have this done) Install the MWO Design kit Install ICED Install ICED Layout Kit (DRC) Follow installation instructions included in the zip file for directory setup and for setting environment variables etc. 5 Installing the Library (PDK) Install TQMailtools Copy the scripts into your ScriptsUser Folder Help > Show Files/Directories Double click on the ScriptsUserfolder to open the folder Copy the.bas script files into this folder 6 3

4 Start AWRDE Using the Library File > New With Library > TQOR_TQPED 7 Outline Installation and Use of the Library Environment Setup Get familiar with the Design Manual Layout Tips and running DRC Simulation Tips and Axiem Example Project Advanced 8 4

5 Hotkeys Using hotkeys can speed up the layout process. To set them up Tools > Hotkeys 9 ShapeSnapTogether: S Useful Hotkeys Select the Items Category and click on ShapeSnapTogether Click in the Press the new hotkeys field and press the S key Leave Standard as the editor Click Assign Other useful hotkeys Assign R to EditRotateRight(Category: Edit) Assign H to WindowTileHorizontal(Category: Window) Assign V to WindowTileVertical(Category: Window) 10 5

6 Toggle Layout Background Color The colors used for the layers in the layout show up best with a black background 11 Layout Background Color To change this go to Options > Environment Options Navigate to the Colorstab and change the layout background to black and grid to white 12 6

7 Element View Within the Elementstab elements appear in the bottom pane The view can be changed by right clicking and selecting Details 13 Useful Shortcuts Ctrl + L to Add Circuit Element Use Ctrl + click on the column header to change the field that is searched Ctrl + K Add SubcircuitElement Ctrl + P Add Port Ctrl + G Add Ground 14 7

8 Element Placement Prior to placement elements can be rotated or flipped Rotate: Right Click Flip about horizontal axis: Shift + Right Click Flip about vertical axis: Ctrl + Right Click 15 Outline Installation and Use of the Library Environment Setup Get familiar with the Design Manual Layout Tips and running DRC Simulation Tips and Axiem Example Project Advanced 16 8

9 Design manual There is a lot of useful information in regards to what you can make in the TQPED Commercial Process Layers 17 Design Manual Suggestions for how to make inductors and microstrip lines Multiple metal layers are used for microstriplines. In the PDK the line is called Plated (M1 + Via2 + M2). The thickness is 6 um (2um + 4um). 18 9

10 DRC and TQPED Design Manual Pg DRC and the TQPED Design Manual Interconnect Layout Design Rules Minimum inclusions for MIM and metal layers 20 10

11 Substrate Vias Substrate via dimensions are fixed, so place with PDK and don t edit. There are placement rules. 21 Minimum Metal Sizes You ll notice most of the structures drawn by the PDK obey this limit 22 11

12 Outline Installation and Use of the Library Environment Setup Get familiar with the Design Manual Layout Tips and running DRC Simulation Tips and Axiem Example Project Advanced 23 Layout Tips Snapping things together Select All and if Hotkey is setup click S You may need to flip or rotate objects to get the layout as you wish Snap two objects Select first object which will not move Select second object and snap together (second object will snap to first object) 24 12

13 Once objects are placed as desired you may want to Freeze the object Right click on the object and go to Shape Properties > Freeze You can also restrict the ability to select objects Right click on an open area in the layout and select Restrict Selection Restricting Selection 25 Running DRC At this point it is useful to run DRC on a small portion of the circuit before spending too much time simulating Also it is easier to address DRC errors on subcircuitsbefore including them in another circuit Be sure you ve save your project before you run DRC Schematics with spaces in the name are not supported for DRC 26 13

14 Running DRC Select the schematic from the list Select ICED DRC Select No LVS Select the path to the ICED.exe and icped.bat file 27 Running DRC Errors can be viewed in AWR For subcircuitsthe MISSING_CELL_BOUNDARY_ERR can be ignored as the final layout will contain the cell boundary This DRC found 18 Errors (4 of which can be ignored since it is a subcircuit). SVIA_GMTRY_ERR can be ignored. This is the only DRC error that can be ignored (all substrate vias will give this error)

15 Resolving DRC issues Double click on the error to highlight it s location in the schematic. Consult the rule list for more info on the specific error. The rule list is located C:\tqs_home\iced\tqped_v227\drctqped _rulelist.txt For additional information consult the design manual Consult drctqped_rulist.txt first to get a description of the error If more information is desired the Design Manual can be consulted. 29 Resolving DRC issues Fix the VIA2_NOTCH_ERR by adjusting the line with to the source of the transistor Fix the PHEMT_GATE_GMTRY_ERR by orienting the transistor vertically 30 15

16 Outline Installation and Use of the Library Environment Setup Get familiar with the Design Manual Layout Tips and running DRC Simulation Tips and Axiem Example Project Advanced 31 EM Simulation Using Axiem EM simulation is useful to ensure the design will perform as design. Linear models may not be accurate so it is essential to do full wave simulations on essentially all the passive structures Matching networks Bias tees Combiner networks Start by doing full wave simulations of small parts to ensure they function as designed, then simulate larger portions of the circuit 32 16

17 EM Simulation Using Axiem I would suggest not using the EM Extract block To run an EM Simulationusing Axiem Complete layout Copy layout to new EM Structure Select Simulator AWR AXIEM Async Select From Stackup under initialization options (Should be selected by default) Select TQPED_STACK_AXIEM for the Stackup 33 Add Edge Port For a Plated line select the Metal 2 object and then select Add Edge Port Click on the edge of the structure where you want the port placed Double click on the port to access the Port Attributes and set the Explicit Ground Reference to Connect to Lower EM Simulation Using Axiem 34 17

18 EM Simulation Using Axiem To simulate the structure create a graph and select the Data Source Name as the EM Structure Once the EM Structure has been simulated it can be added as a subcircuitin the linear simulator 35 EM 3D view to check connectivity From EM Structure 2D select View EM 3D Layout Select Show 3D Mesh Connectivity will be color coded 36 18

19 Outline Installation and Use of the Library Environment Setup Get familiar with the Design Manual Layout Tips and running DRC Simulation Tips and Axiem Example Project Advanced 37 Example Project Tunable Directional Coupler 38 19

20 Ideal Coupler Performance vs. Frequency For a desired tuning range of S 31 between -40 and -5 db corresponds to C= 8 ffto C= 400 ff Isolationis greater than 24 db Insertion loss is less than 1.3 db Return loss greater than 24 db S 31 and S 11 vs. frequency S 41 and S 21 vs. frequency IMS2012 Montreal TH3B-5 June 21, Implement the l/ W transmission line with a p- equivalent circuit Bias 3 depletion mode Schottky diodes with same voltage (D var ) MMIC Implementation Simplified bias circuit Implemented in a standard 0.5 μm GaAs phemt process (TQS TQPED) IMS2012 Montreal TH3B-5 June 21,

21 Layout Probe Pad Placement Template has 150 um pitch and 250 um pitch probe pads drawn Probe station has 4 axis that can be measured Can t measure a device with pads on the same side of the circuit DC probes may be place anywhere within reason (things may be too close to land all of the probes) If you are going to want to use bond wires probes should be placed at the edge of the circuit 41 Advance Concepts Draw own capacitors (DC blocking capacitors are a great example) They can be integrated into feed lines to save space Cutting microstriplines simulated with Axiemusing mutual ports Insert a linear model for MLIN to tune Adding series ports between the top and bottom plate of a capacitor in Axiem Use an ideal capacitor across this port Once tuned appropriately adjust the capacitor to reflect the full wave simulation + the ideal capacitor Draw own inductor, cut down the middle. Add mutual ports. Insert linear coupled line model to tune the circuit 42 21