Process technology and introduction to physical

Transcription

1 Neuromorphic Engineering II Lab 3, Spring Lab 3 March 10, 2014 Process technology and introduction to physical layout Today you will start to learn to use the Virtuoso layout editor XL which is part of the Cadence design environment to do physical layout of a cell. You will lay out the circuits for a first-order lowpass filter (follower integrator) using a transconductance amplifier and a MOS capacitor. The schematic is shown in Fig The goals are to Understand how the masks that you draw result in the fabricated planar technology. Understand bulk (substrate and well) connections. Understand that a methodical use of wiring layers in canonical directions can help make layout manageable. To lay out the smallest circuit that you can so as to conserve silicon area, given the constraints on the circuit design (transistor geometries). To lay out the cell so that it can be composed into a delay line. To learn to label nets for documentation and ease of understanding. Labeling nets on the layout are also required for some tools that perform layout versus schematic (LVS) checks. 3.1 Instructions The targeted process We are targeting the Austria Microsystems (AMS) H18 process. This is a 0.18 um process (0.18 um is the minimum transistor length or feature size) with 4 metals. The supply voltage for this technology is 1.8V. We will be using the H18 process design rules. Printouts of the relevant parts of the rules will be provided to you for reference.

2 Neuromorphic Engineering II Lab 3, Spring Figure 3.1: Schematic of simple follower integrator. Transistor sizes are all W/L=1.2u/1.2u Capacitance value may need to be modified Capacitance value Before drawing the follower-integrator s capacitor, calculate the capacitance needed for the capacitor if we want an RC time constant of 0.1 ms and we run the amplifier at a bias current of 1 na. Assum κ = 0.8. There are many ways to realize capacitors in the AMS H18 process we are using. In this lab, we will implement a capacitor using an NFET transistor. One terminal of the capacitor is the gate of the NFET, the other terminal is the inversion layer beneath the gate. Between these two terminals is the gate oxide. The inversion layer can be contacted through the source and the drain which are shorted together to form one terminal of the capacitor. You will now evaluate the capacitance of an NFET capacitor through simulations using the circuit shown in Fig. 3.2: 1. Create a cell capeval and enter the schematic in Fig Use the vpulse voltage source from analoglib to drive the gate of the transistor. Set the vpulse voltage source paratemetrs to obtain a voltage ramp from 0 to 1.8V in 50us. 2. Simulate capeval and plot the current through the voltage source. You may want to adjust the simulator tolerances. What is the relation between this current and the NFET capacitance value? In which range of operation does the capaitance of the NFET reach its maximum value? Why? 3. The permitivitty of silicon dioxide is , estimate the thickness of the gate oxide. 4. Find the dimensions of the NFET transistor needed to realize the follower-integrator s capacitor.

3 Neuromorphic Engineering II Lab 3, Spring Figure 3.2: measurement circuit for evaluating the capacitance of a MOS transistor Creating the schematic and generating the layout PCells We will use Cadence s schematic driven layout to create the layout of the follower integrator circuit in Fig In schematic driven layout, Cadence helps you maintain a correspondence between the instances in the schematic (the transistors) and the instances in the layout, and between the wires and polygons in the layout and the nets in the schematic. This provides direct feedback on how the layout maps to the schematic and helps to quickly catch any mismatch between the layout and the schematic. The representation of a transistor in the schematic view is a symbol with configurable properties (width, length, etc..). In the layout view, a transistor is represented by a PCell (parameterized cell). This cell also has configurable properties, and changing these properties changes the geometry of the cell. For example, changing the length of the transistor PCell changes the length of the polysilicon shape forming the gate. 1. Create a cell followeintegrator and enter the schematic in Fig Use the NFET capacitor dimensions you calculated in the previous section. Make sure you include the 3 schematic pins V1,V2, and Vb. Also make sure that you connect the sub! net to the gnd! net through the subcx instance from the cmhv7sf library. subcx represents a substrate contact that ties the substrate potential to gnd!. 2. We now need to create a layout view for the followeintegrator cell. Select the cell in the library manager then select File - New - Cell View. In the view name, type layout, and select Layout XL from the open with list. Press ok. 3. You should now see an empty layout window and the LSW window. the LSW window contains a list of the layers available in the current technology. Each layer has a name and a purpose. The most common purposes are drawing and pin. Layers with a pin purpose are used to create pin shapes. The most important layers are: RX : Active layer. P+ or N+ diffusion layer depending on whether or not it is covered by the BP layer BP : P+ implant marking layer. Marks P+ diffusion. RX not covered by BP is N+

4 Neuromorphic Engineering II Lab 3, Spring diffusion PC : Polysilicon layer. A transistor gate is formed by the overlap of PC and RX NW : Nwell layer M1 : First metal layer CA : Contact layer connecting PC or RX to M1 M2 : second metal layer V1 : Via layer connecting M1 to M2 4. Click a layer in the LSW and experiment with drawing rectangles and paths. You can scroll up/down, scroll left/right, zoom in/out by using the mouse wheel together with the shift and ctrl keys. Some important shortcuts are: r: Create rectangle p: Create path Shift-p: Create polygon l: Create label i: Create instance o: Create contact ctrl+shift+w : create wire m: move s: stretch c: copy q: show properties 5. We now generate the PCells for the follower-integrator layout. Click the Generate from source button at the bottom left. Click ok. You should now have transistor pcells in the layout. There is a 1-1 correspondence between these cells and the schematic cells. Selecting a cell in one view highlights the corresponding cell in the other view. 6. Each pcell has contacts on the source and drain. You can disbale them by selecting a cell, pressing q, and in the cell parameters, setting Fet configuration to n ss. Do that for all transistor pcells. You can usually obtan more area-efficient layouts by working with these bare-bones transistor cells and adding contacts only when they are needed Wiring It is useful to decide on a consistent wiring strategy for all cells, since it makes interfacing them later much easier. Start by drawing the global nets such as wells, power lines and biases, since these must connect across the cells to form arrays. For this exercise you should use the following strategy: Use MET1 for power/gnd rails. power at the top, and gnd at the bottom. The rails run horizontally and the cells are placed between them.

5 Neuromorphic Engineering II Lab 3, Spring Use MET1 to route signals whenever possible. Switch to M2 if you can not route using M1. Use MET3 for carrying biases in the vertical direction. Use ctrl+shift+w to quickly create wires Create contacts using the o shortcut. Notice that Layout XL infers the nets of the wires you use. You can see the schematic net name of a shape by selecting the shape, pressing q, and looking in the connectivity tab. Enable the navigator pane by selecting window - assistants - navigator. There you will see a list of instances, nets, and pins. Select any of them to highlight it in the layout Enable the Annotation browser by selecting window - assistants - annotation browser. The annotation browser shows you the sources of mismatch between the layout and the schematic. Keep in mind that the layout you create will typically be instantiated with other layout views in a higher level of the hierarchy. At a higher level of the hierarchy, the layout editor connectivity detection algorithms only see the pin shapes in the instantiated layout view. If connectivity detection actually parsed the wires and shapes all the way down the hierarchy in order to reconstruct the connectivity of the design, connectivity extraction would be extremely time-consuming. This would also defeat one of the main purposes of hierarchical design which is improving scalability by allowing the design tools to maintain detailed information only about the current level of the hierarchy while abtsracting lower levels. After the follower-integrator ayout is finished, select the pin shapes, and place them where you want the higher level of the hierarchy to connect to your follower-integrator cell. The layer of the pin is important as it specifies what layer the higher level of the hierarchy will use to connect to a pin shape. If the pin is placed on an M1 wire, it should have the M1-pin layer where pin is the layer purpose. This indicates that this pin should be contacted by an M1 shape at a higher level of the hierarchy. Remember that RX can also be used as a wiring layer (which has a high resistance however), although it cannot cross a well edge Design rules You will be using so-called native design rules. A printout of the rules is provided for you and the DRC will check against these rules. You should have a close look at the rules to understand their structure by mask layer and type (e.g. spacing, overlap, enclosure, etc.)

6 Neuromorphic Engineering II Lab 3, Spring Bulk connections and butted contacts Don t forget the well and substrate contacts. These are also called taps or plugs. The taps can be drawn either with separate contacts or butted contacts. A separate contact is an area drawn in its own active area which is separate from any transistor active region. A butted contact shares an active area with a transistor. The tap should be N+ diffusion to contact an NWell or a P+ diffusion to contact the substrate. Since the nearby active area is doped oppositely to form a transistor source or drain, the butted contact forms a lateral pn junction. Since mask misalignment may cause the p and n implants to overlap or not touch, this junction may actually act like a short, a Schotky diode, or some other odd device. Therefore it is very important that these butted contacts always be shorted by a metal line to the power supply or the ground line, i.e., the source of the transistor that uses a butted tap must be connected to the power supply (pfet) or to ground (nfet). 3.2 Postlab Sketch the cross sections of the process steps up to MET1 to show how each mask that you used in the exercise is used. (You don t need to worry about threshold implant, LDD, local interconnect. Just sketch how your drawn masks get used for etch, implant, etc. as best you can.) 3.3 What we expect you to learn What does a layout editor do? What distinguishes drawn and derived layers? What kinds of derived layers are there, e.g. for design rule checking and layout extraction? Can you write the physical mask layers for a basic CMOS process? How are the layers you draw related to the masks that are fabricated? What are design rules? How are chips fabricated? Can you draw the process flow for planar silicon CMOS technology? What is an implant? a diffusion? an etch? a deposition? How are impurities gettered from the wafer? How do you draw a poly capacitor? a MOS capacitor? a photodiode? What are well and substrate contacts, why are they necessary, and how do you draw them? What are butted contacts and why must they always be shorted by metal? 3.4 Next Week Design rules and DRC, more layout exercises.