Lab 2. Standard Cell layout.

Transcription

1 Lab 2. Standard Cell layout. The purpose of this lab is to demonstrate CMOS-standard cell design. Use the lab instructions and the cadence manual ( as guide through the different design steps. If you have forgotten how to start Cadence and then draw and simulate schematic, use lab 1 as guide. Lab 2 consists of designing two digital blocks (standard cells), a NOR-gate and a flip-flop. After designing each standard cell, make sure that it is approved by a lab-assistant. Euler Paths A compact and efficient method to design layouts for complex gates is to place all the transistor gates on one long strip of diffusion, illustrated by the two diffusion strips in figure 1b. A method to find the strips is to find the Euler paths in the circuit diagram. An Euler path is a path where all branches (transistors) are passed once and only once. However, a node can be visited several times. The paths, one for the PUN respective the PDN, can be found directly in the circuit diagram as shown in figure 1a. A B A f NAND f AND f AND B a) GND b) Figure 1 : AND gate with a) the Euler path and b) the corresponding layout A B GND A rule of thumb is to try finding Euler paths having the same gate order at PUN and PDN to avoid crossing the polysilicon wires. Several Euler paths can often be found. Figure 1a shows two. Another starts at the node through the B- transistor, through the A-transistor back to the node, and finally through the P-channel transistor in the inverter to the f AND node. These paths will thus give different layouts. It is not always possible to find a single Euler path. In such cases, the Euler path as well as the diffusion strip has to be broken in multiple paths. Home assignments: Explain the following terms for a CMOS technology with N-well (draw simple figures). NMOS transistor PMOS transistor Transistor width Transistor length Substrate contact N-well For the same technology, explain how to connect the substrate contacts for both PMOS and NMOS transistors in a digital standard cell. 1

2 Find and explain the following terms and abbreviations in lab 2: vdd/gnd netlist Standard cell Transient analysis Abstract view DRC LVS Post-layout simulation Draw a transistor schematic of a two-input CMOS NOR-gate. Suggest input stimuli to simulate the NOR-gate. Suggest Euler paths for the NOR-gate. Draw symbolic layout of the NOR-gate using diffusion strips based on Euler paths. Suggest p-transistor dimensions in a balanced CMOS two-input NOR gate if the n-transistors are of minimum size (W/L = 160/120). Explain the function of the inverting TSPC-ff of fig 7-33 in the textbook (also shown below). Draw a signal graph. M3 CLK M6 Y M9 Q bar Q D CLK M2 X M5 CLK M8 M1 CLK M4 M7 Suggest input stimuli to simulate the TSPC-ff. Figure 7-33 in the textbook Include an inverter at the output of the TSPC-ff of fig 7-33 and Suggest Euler paths for the resulting noninverting TSPC-ff. Avoid crossing the polysilicon wires. Draw a symbolic layout using diffusion strips based on Euler paths. It is possible to do the layout with only one metal layer. Read chapters 1-6 in the Cadence manual ( Lab assignments: Schematic and Layout of a CMOS NOR-gate Create a new design library named lab2 and a new schematic named nor2 in library lab2. Design a two-input NOR-gate in schematic using the transistor data of your preparations and simulate its behavior. Hint: Modify a test bench from lab 1, use an inverter as load. Next step is to make a standard cell layout of the NOR-gate using diffusion strips based on Euler paths. 2

3 Create a new cellview with Library Name lab2, Cell Name nor2, View Name layout and Tool Virtuoso. Two windows are now opened; The Virtuoso Layout Editing window where the layout is drawn and the LSW window where you select layer to draw(metal 1, metal 2, polysilicon etc). Start the Virtuoso XL tool by choosing Tools Layout XL from the menu. This creates a connection between the schematic and layout and allows for simple instantiation of the schematic components. Since the layout is going to be a standard cell, the height of the cell as well as the vdd and gnd lines must be defined to make cell abutment possible. To avoid DRC errors when abutting the cells, it is also important to keep the left and right borders of the cell free of any drawing except for the n-well (ntub) that is aligned with the cell borders. A celltemplate of height 7µm containing vdd and gnd lines as well as a default n-well can be used for this purpose. Get the 7µm high cell template from library diglab cellname celltemplate using Create Instance [i]. The width of the cell is set using the parameter Width. The cell must be wide enough to contain the whole NOR gate. If needed the, width can be changed later on, using the properties; Edit Properties [q]. Get and place the transistor layout instances using Create Pick from schematics The transistors can either be marked directly in the schematic view or picked from the list, using the Unplaced button. Pick the transistors only, not the pins. If the transistors appear just as read boxes, press Shift-F, to toggle the display mode to show hierarchical depths. Since the Virtuoso XL tool knows about the connection of the transistors in the schematic, it knows how the transistors are supposed to be ordered. This information can be used to remove redundant connections. Place two neighboring transistors, belonging to the same diffusion strip, on top of each other and see what happens. In the schematic, the transistors have four connections, in the layout there are only three. This is because the substrate contact is not part of the device. The substrate contacts are placed separately by choosing Create Contact and the contact named M1_NWEL or M1_PACTIVE. The N-well needs to be connected to vdd and the rest of the substrate needs to be connected to gnd. The connections can be put anywhere into the substrate and the well respectively, but the closer to the transistors, the better. Next step is to connect the nodes of the transistors. Use metal 1 ME1 drw and polysilicon 1 PO1 drw. Select layers in the LSW-window. All drawing is made using the drw layers. To draw connections, choose Create Rectangle [r] and click on the diagonal corners where you want to add for instance a rectangle in metal 1. Another alternative for connections is to use Create Path [p]. This has the advantage that Virtuoso XL will be able to help choosing the correct layer for drawing the path. Test both methods to see which you prefer. To simplify the drawing it is possible to zoom using Window Zoom In [z]. To get from polysilicon to metal 1, choose Create Contact and the contact named M1_POLY. Use M1_POLY to get a metal 1 contact at the connected gates. To check the layout so far, run a Design Rule Check (DRC) using Assura Run DRC. Use Technology umc130_drc and Rule Set dig2009. It may also be a good idea to specify Run Directory, to get all the output files placed in a certain directory, as shown in the figure on next page. Then press OK or Apply to start the tool 3

4 The DRC option checks for a large number of rule violations. The result of the DRC is shown in a pop-up window called the Error Layer Window. Here it is possible to inspect the errors one by one. Make sure that all DRC errors are removed and then re-run the check. The next step is to add pins. When the Assura tools are used, pins are defined using labels. The labels must be of the same layer type as the pin. In this design that means metal1. Therefore: Choose ME1 drw in the LSW-window. Choose Create Label [l]. Write the name of label, e.g. A, and then place the label at the A net. It is possible to reduce the size of the labels, if they are too large. The pins for vdd and gnd shall be named vdd! and gnd!. Adding a! after a pin name makes the pin globally connected. This means for instance that all vdd! pins in a design are connected together automatically. After completing the layout, do a final DRC. Next step is to do a Layout Versus Schematic (LVS) test. Choose Assura Run LVS. Here the Technology should be umc130_lvs while the Rule Set still is dig2009. Also for this operation it may be smart to choose a Run Directory as shown below. 4

5 Click OK or Apply to run the LVS, and wait for it to finish. After the run, the tool will report if the schematic and the layout matches. There is also an option to open the LVS Debug view, to look for possible errors in the design matching. If you have any errors, correct them and re-run the LVS. Since we want to do a post-layout simulation, an extracted view is created for the NOR-gate. This is done by choosing Assura Run RCX in the menu. In the Setup tab, make sure that Technology is umc130_lvs and the Rule Set is dig2009. In addition choose Output to be Extracted View, as shown below. 5

6 Switch to the Extraction tab. Set Extraction Type RC and Cap Coupling Mode to Coupled with gnd! as Ref Node, as shown below. Now pres OK or Apply to run the extraction. The created view, the av_extracted, will be used in the postlayout simulation. Post-layout simulation of a CMOS NOR-gate In the previous schematic simulation, a testbench schematic for the NOR-gate was created. This testbench can also be used for the post-layout simulation. To do this, a config view of the testbench shall be created. In the config view it is possible to select simulation model for the different instances in a top level schematic. Before creating the config view, we shall make a small modification in the testbench. Open the testbench. Copy the NOR-gate symbol and make sure that both NOR-gates have identical input signals. 6

7 The reason for having two NOR-gates in the schematic is to compare the output of a schematic NOR-gate and a layout NOR-gate. After Check and Save [X], create the config view. Select File New Cellview in the Library Manager or the main window and create a config view of the testbench with Tool Hierarcy-Editor. Two windows now open. In the window entitled New Configuration, press the button Use Template and choose Template Name spectre. Press OK. In the window entitled New Configuration, make sure that the view is set to schematic, as shown in the figure. Then press OK. In the Hierarchy Editor window, a simulation model is selected for each instance. To get a better view of the hierarcy of the testbench, select View Tree. In the Hierarchy Editor there are two NOR-gates each having an unique instance number. The instance numbers are also seen in the schematic view. The simulation model for one of the NOR-gates shall be changed to view av_extracted, which was created by the RCX extraction. To change the simulation model, right click on the instance in the config view and choose Set Instance View av_extracted. The simulation model for the other NOR-gate does not have to be changed since the default simulation view is schematic. Choose View update [ctrl-u] and File Save [ctrl-s] in the config view. To get the Analog simulator to use the settings made in the config view, close the testbench and reopen it by pressing the button Open in the config view. The simulation is performed in the same way as in the schematic simulation. Zoom in an edge in the waveform window to view differences between the schematic simulation model and the analog_extracted simulation. NOR-gate approved by 7

8 The following flow chart serves as a repetition of the workflow for creating a standard cell. Draw Schematic Simulate Schematic LVS Create Layout view Build analog extracted Place transistors Create config view Draw connections Simulate using analog extracted view Place contacts Place pins (labels) Create abstract (not included in the lab) DRC A TSPC-ff standard cell Design the non-inverting TSPC-ff according to the preparations and simulate its behavior. For simplicity, use transistor sizes 0.4/0.35 for all n-transistors and 0.8/0.35 for all p-transistors. To avoid braking any setup or hold times for the TSPC-ff, delay the input relative to the clock by adding a Delay time of 100 ps in the pulse generator. Make a standard cell layout of the non-inverting TSPC-ff using diffusion strips based on Euler paths. Do postlayout simulation of the non-inverting TSPC-ff. Find the minimum clock period for both simulation models of the TSPC-ff. Hint: Replace the clock period with a parameter (for instance T, Pulse width = T/2). T min schematic T min layout TSPC-ff approved by 8