Co-Design and Co-Verification using a Synchronous Language. Satnam Singh Xilinx Research Labs

Transcription

1 Co-Design and Co-Verification using a Synchronous Language Satnam Singh Xilinx Research Labs

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4 Virtex-II PRO Device Array Size Logic Gates PPCs GBIOs BRAMs 2VP2 16 x 22 38K VP4 40 x 22 81K VP7 40 x K VP20 56 x K VP50 88 x K

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7 ZBT SSRAM SDRAM DDR SDRAM ROM ZBT SSRAM Controller SDRAM Controller DDR SDRAM Controller External Bus Controller OPB Bridge OPB On-Chip Peripheral CoreConnect Processor Local Bus (PLB) Arbiter CoreConnect OPB (On-Chip Peripheral Bus) 405 PPC I-Cache PLB D-Cache PLB High-Speed Peripheral OPB Bridge On-Chip Peripheral

8 Formal Techniques Project Domain specific languages for hardware design and verification (Lava) and cryptology (Cryptol). Formal methods for CAD (routing) and dynamic reconfiguration (reconfiguration controllers). Formal notations/representations for HW/SW co-design and verification (e.g. Esterel) Property checking (PSL/Sugar) IP -reuse (more powerful type systems la de Alfaro and Henzinger)

9 Problems Challenges Customer requirements for migrating software into hardware ( salmon effect ): determinism: multiple SW processes on RTOS vs. genuinely concurrent HW verification isolation Customer requirements to trade-off HW/SW partitioning for products at different price points. Requirements for verification of SW+HW Safe Dynamic Reconfiguration Verification of control-based systems

10 LocalLink (Point to Point)

11 Aurora (Link Layer Protocol)

12 TX of 10 Gigabit Ethernet MAC

13 Verify RX Control Signals

14 Safe Dynamic Reconfiguration

15 JPEG2000 Platform

16 Video Monitoring Application

17 Bus Based Reconfiguration

18 Bus Based Reconfiguration

19 Bus Based Reconfiguration

20 Single Specification for Hardware and Software VHDL, Verilog - > h a r d w a r e i m p l e m e n t a t i o n HW/SW agnostic specification void uart_device_driver ( ) {... } uart.c C - > software implementation

21 Embedded Developer Kit

22 Configuration ELF File bit File DATA2BRAM BlockRam Memory Map (.bmm) # CPU address space 0xFFFFE000-0xFFFFFFFF. ADDRESS_BLOCK dramctlr BUS_BLOCK [0xFFFFF000:0xFFFFFFFF] xrefdes/dramctlr/bram0 [7:0] LOC=RAMB16_X0Y0; xrefdes/dramctlr/bram1 [15:8] LOC=RAMB16_X1Y0; xrefdes/dramctlr/bram2 [23:16] LOC=RAMB16_X2Y0;... END_BUS_BLOCK; END_ADDRESS_BLOCK;.mem File New.bit File

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24 FSM Specification

25 Esterel Specification

26 FIFO Extract

27 Concurrent Loops

28 Orthogonality Orthogonal language constructs for: Sequencing Concurrency Waiting Pre-emption Freely mixable at any level. Things are only written once. Gérard Berry.

29 Esterel Studio

30 Creating design Via Safe State Machines Via Esterel code loop [ await A await B ] ; emit O each R

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35 Code generation VHDL, Verilog - > h a r d w a r e i m p l e m e n t a t i o n Esterel design void uart_device_driver ( ) {... } uart.c C - > software implementation

36 Hardware UART XC2V1000

37 Direct use in SoC

38 Soft UART MicroBlaze XC2V1000

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40 parallel to serial shift

41 receive

42 serial to parallel

43 FIFO

44 UART without bus interface

45 OPB Protocol M1_BE Byte enable

46 UART with OPB Interface

47 Generated circuit Esterel UART Lite : 912 LUTs 385 flip flops

48 Comparison with Original CoreGen IP CoreGen UART Lite IP : 100 LUTs 51 flip flops 9 times smaller!

49 Verification by simulation

50 Verification with Observers Inputs Observed system System model Observer BUG BUG is always emitted Verifier Outputs BUG is possibly emitted BUG is never emitted

51 Verification engines 2 proof engines available inside Esterel Studio Built -in verifier : TiGer BDD technique Prover Plug-in S A T t e c h n i q u e

52 Formal verification Of the FIFO : proving that only a read access can make it exit the full state Proven in less than 2 seconds

53 Specification of master behavior...

54 slave

55 and arbiter

56 OPB Protocol violations e.g. Checking that RNW doesn t change during a transaction :

57 Formal verification Of the OPB slave interface : proving that it won t cause bus timeouts Proven in less than 2 seconds

58 Formal verification Of the FIFO : proving that only initialized data is returned Using an internal observer to access internal signals No constraint on input signals Proven in 30 seconds

59 Interactive Deadlock Demo

60 Other examples (LocalLink, Aurora,...)

61 Positive Conclusions Control-based calculations can be implemented in hardware using a software style specification in Esterel ( computing without processors ). Synchronous observers provide an additional verification technique to simulation, assertion languages (Sugar/OpenVERA etc.) and permits co-verification. Co-synthesis allows HW/SW trade-offs to be explored. VHDL/RTL provide poor interface between high systems and back-end tools.

62 Next Steps C u r r e n t l y w o r k i n g o n : Xilinx Link Layer protocol (LocalLink, Aurora). TX portion of 10 gigabit ethernet MAC. Wire -s p e e d h i g h l e v e l p r o c e s s i n g o f g i g a b i t a n d 1 0 -gigabit traffic. Language enhancements to better support HW d e s i g n. I n t e r f a c e s y n t h e s i s ( a l a C o W a r e ) Control for System Generator

63 System Generator System Generator extends Simulink to support external simulation engines Hardware acceleration Mixed- mode HDL/data flow Hardware in the loop co- simulation HDL co- simulation