Case study of IBIS V4.1 by JEITA EDA-WG
|
|
- Raymond Ferguson
- 6 years ago
- Views:
Transcription
1 Case study of IBIS V4.1 by JEITA EDA-WG June 8, 2004 IBIS SUMMIT in San Diego, California JEITA EDA-WG A. Itoh,, T. Watanabe, N. Matsui JEITA ; Japan Electronics and Information Technology Industries Association JEITA All Rights Reserved. 1
2 Outlines 1. JEITA EDA-WG Activities 2. Case study of IBIS V EMI Model JEITA All Rights Reserved. 2
3 1. JEITA EDA-WG Activities JEITA All Rights Reserved. 3
4 EDA Model for Objectives of JEITA EDA Digital Consumer Electronics Cellular Phone, LCD TV, Digital Camera/Video, DVD Recorder (Digital, RF, and Analog circuits) Auto Mobile Electronics? (Motor Drive, EMC) < Applicability of IBIS V4.1 > JEITA All Rights Reserved. 4
5 EDA Model for SI, PI and EMI Simulation PCB FPC Cables Connectors Passive Component (LCR, Filter) RF Modules LSI Model IC Chip IC Package Display device Discreet Semicon Crystal Oscillator JEITA All Rights Reserved. 5
6 IC Package ICs RF Modules Passive Components (LCR, Filter) Discrete Semiconductors Crystal Oscillator EDA Models For Digital Consumer electronics Connectors Cables FPC PCB JEITA All Rights Reserved. 6
7 JEITA EDA-WG Member Digital Consumer Electronics Supplier Discrete ICs Panasonic Sony Sharp Canon Toshiba Shin Dengen EDA(internal/vendor) Fujitsu Mitsubishi Apsim Semicon NECEL Toshiba EDA Models For Digital Consumer electronics Connectors JAE FPC JEITA All Rights Reserved. Mectron Passive Components TDK Murata PCB CMK 7
8 2. Case study of IBIS V4.1 JEITA All Rights Reserved. 8
9 Summary of investigation of IBIS V4.1 ASIC/SOC for EMI/SSO Power Semiconductor OpAMP DSP, AD/DA, Xtal Passive Components Package, Module, PCB Connector, Cable, FPC V3.2 ( ) ( ) IBIS V4.1 SPICE V4.1 *AMS ( ) ( ) (?) ICM Comments Accurate models need the internal gates for EMI/SSO. IBIS V4.1 SPICE discloses process parameters. IBIS V4.1 SPICE discloses process parameters. I/O for SI can be described in V3.2. Inside needs *AMS. Can describe LCRK models ICM describes S-parameters (?) IBIS 4.1 SPICE can t describe ( ) ( ) JEITA All Rights Reserved. S-parameters or lossy coupled transmission line. ICM can t include discrete components. SiP and PWRGND modeling. ICM can t include discrete components. 9
10 Understanding of IBIS V4.1 ICM V1.0 IBISV4.1 [Component] [Node Declarations] [Circuit Call] VHDL-AMS SPICE3 Verilog-AMS IBIS [Model] Model_type [External Model] [External Circuit] IMIC (Table_SPICE) IBIS excludes IMIC JEITA All Rights Reserved. 10
11 How to describe SPICE transistor model in in IBIS 4.1 without disclosing proprietary information Models described in SPICE transistors have flexibility. Net List Equivalent Circuit (Macro Model) using Transistor Models Transistor Parameters IBIS V4.1 allows to use SPICE3 but discloses process parameters IMIC (Table_SPICE) allows to hide the transistor parameters, but IBIS V4.1 excludes IMIC. JEITA All Rights Reserved. 11
12 How to hide transistor model parameters in in IBIS V4.1 SPICE description without losing accuracy IMIC (Table_SPICE) allows to hide the transistor parameters, but IBIS V4.1 excludes IMIC. Need to have a bridge from IMIC to IBIS V4.1 SPICE 3 without disclosing the original SPICE transistor parameters. JEITA All Rights Reserved. 12
13 3. EMI Model (NEC/APSIM) NEC/APSIM All Rights Reserved. 13
14 LSI Model for EMI Simulation LSI Power Supply RF Current of LSI 1. Measurement; IEC Magnetic Probe Method 2. Simulation Model; EMI Model for LSI NEC/APSIM All Rights Reserved. 14
15 EMI Simulation for PCB LSI PCB Chip power RF Current IO Model Power and Ground Model input PCB PKG PKG Clock output ground Power/Ground Plane Power/Ground Plane Input/ Output Clock Macro Non-Clock Macro EMI simulation needs the internal gates power/ground model with loading effects in time/frequency domain. NEC/APSIM All Rights Reserved. 15
16 Current Waveforms of 32-bit LSI Output Internal Total NEC/APSIM All Rights Reserved. 16
17 Measurement IEC Magnetic Probe Method Spectrum analyzer Pre-amplifier (option) Magnetic probe LSI Magnetic field IC test board Current Decoupling capacitor NEC/APSIM All Rights Reserved. Power supply 17
18 Simulation VS Measurement dbua 8Tr D,FL,RAM Simulation Measurement 5s(D) 5s(B+D+F) 実測 MHz NEC/APSIM All Rights Reserved. 18
19 Current/Magnetic Field Distribution Simulation Measurement APSIM NEC/APSIM All Rights Reserved. 19
20 EMI Simulation Model for LSI Power and Ground Model of Core Logics (internal gates) PKG PKG power RF Current input output Input Clock Macro Non-Clock Macro Output ground IBISV3.2 IMIC IBISV3.2 IBIS 4.1 NEC/APSIM All Rights Reserved. 20
21 Developed IMIC to IBIS V4.1 Converter Any SPICE.MODEL Any SPICE Table_SPICE Generator Table_SPICE.MODEL IMIC Table_SPICE to SPICE 3 MODEL3 Converter SPICE 3 LEVEL=3.MODEL IBIS V4.1 The parameters of LEVEL=3 can t disclose those of the original SPICE. NEC/APSIM All Rights Reserved. 21
22 Full chip power/ground current models in in time/frequency domain for EMI Simulation Table LEVEL=3 NEC/APSIM All Rights Reserved. 22
23 Example of LSI Power/Ground Model (IBIS V 4.1) NEC/APSIM All Rights Reserved. 23
24 1 Example of LSI Power/Ground Model (IBIS V 4.1) Original SPICE MOS parameters 2 Table_SPICE MOS V-I-C data 3 SPICE 3 Level=3 MOS minimum parameters NEC/APSIM All Rights Reserved. 24
JEITA EDA -WG Activity and Study of Interconnect Model Part-3
JEITA EDA -WG Activity and Study of Interconnect Model Part-3 Oct 27, 2006 IBIS SUMMIT in China JEITA EDA-WG Takeshi Watanabe (NEC Electronics) Hiroaki Ikeda (Japan Aviation Electronics) JEITA ; Japan
More informationModel Connection Protocol extensions for Mixed Signal SiP
Model Connection Protocol extensions for Mixed Signal SiP Taranjit Kukal (kukal@cadence.com) Dr. Wenliang Dai (wldai@cadence.com) Brad Brim (bradb@sigrity.com) Presented by: Yukio Masuko Cadence Note:
More informationEECE 615: High-Frequency Design Techniques
Department of Electrical and Computer Engineering EECE 615: High-Frequency Design Techniques Prerequisites: EECE 417, PHYS 204C Required for all MSEE majors Catalog Description:Study of the problems associated
More informationTHE DESIGNER'S GUIDE TO VERILOG-AMS First Edition June 2004
THE DESIGNER'S GUIDE TO VERILOG-AMS First Edition June 2004 KENNETH S. KUNDERT Cadence Design Systems OLAF ZINKE Cadence Design Systems k4 Kluwer Academic Publishers Boston/Dordrecht/London Chapter 1 Introduction
More informationSimulation and Modeling for Signal Integrity and EMC
Simulation and Modeling for Signal Integrity and EMC Lynne Green Sr. Member of Consulting Staff Cadence Design Systems, Inc. 320 120th Ave NE Bellevue, WA 98005 USA (425) 990-1288 http://www.cadence.com
More informationThe 3S Proposal: A SPICE Superset Specification for Behavioral Modeling
The 3S Proposal: A SPICE Superset Specification for Behavioral Modeling Michael Mirmak Intel Corporation June 5, 2007 Legal Disclaimer THIS DOCUMENT AND RELATED MATERIALS AND INFORMATION ARE PROVIDED "AS
More informationModeling and Verifying Mixed-Signal Designs with MATLAB and Simulink
Modeling and Verifying Mixed-Signal Designs with MATLAB and Simulink Arun Mulpur, Ph.D., MBA Industry Group Manager Communications, Electronics, Semiconductors, Software, Internet Energy Production, Medical
More informationApplication Note. EMC Design Guide. F 2 MC-8L Family. History 04 th Jul 02 NFL V1.0 new version
Application Note EMC Design Guide F 2 MC-8L Family Fujitsu Mikroelektronik GmbH, Microcontroller Application Group History 04 th Jul 02 NFL V1.0 new version 1 Warranty and Disclaimer To the maximum extent
More informationPractical Shielding, EMC/EMI, Noise Reduction, Earthing and Circuit Board Layout
Practical Shielding, EMC/EMI, Noise Reduction, Earthing and Circuit Board Layout Contents 1 Introduction 1 1.1 Introduction 1 1.2 EMI vs EMC 3 1.3 Interference sources 3 1.4 Need for standards 5 1.5 EMC
More informationIBIS and Behavioral Modeling
IBIS and Behavioral Modeling Michael Mirmak Intel Corporation Chair, EIA IBIS Open Forum IBIS Summit Shenzhen, China December 6, 2005 迈克尔. 莫马克英特尔公司 IBIS 委员会主席 亚洲 IBIS 技术研讨会中国深圳 2005 年 12 月 6 日 Legal Disclaimers
More informationCompact Model Council
Compact Model Council Keith Green (TI) Chair Peter Lee (Elpida) Vice Chair 1 History and Purpose The CMC was formed in 1996 as a collaboration of foundries, fabless companies, IDMs and EDA vendors Foundry
More informationConnecting MATLAB & Simulink with your SystemVerilog Workflow for Functional Verification
Connecting MATLAB & Simulink with your SystemVerilog Workflow for Functional Verification Corey Mathis Industry Marketing Manager Communications, Electronics, and Semiconductors MathWorks 2014 MathWorks,
More informationWie entsteht ein EMV-Modell für eine integrierte Schaltung?
Wie entsteht ein EMV-Modell für eine integrierte Schaltung? P. Schneider Overview Motivation Introduction Signal- and Power Integrity Simulation Tools Input Data Preparation gds2def & Power Annotation
More informationAN_8430_002 April 2011
A Maxim Integrated Products Brand 78Q8430 10/100 Ethernet MAC and PHY APPLICATION NOTE AN_8430_002 April 2011 Introduction 78Q8430 Layout Guidelines The TSC 78Q8430 is a single chip 10Base-T/100Base-TX
More informationW5100 Layout Guide version 1.0
version 1.0 2009 WIZnet Co., Inc. All Rights Reserved. For more information, visit our website at http://www.wiznet.co.kr Copyright 2009 WIZnet Co., Inc. All rights reserved. Table of Contents 1 Goal...
More informationdesigns with signals operating in the multi-gigahertz (MGH) frequency range. It
DATASHEET ALLEGRO PCB SI GXL Cadence Allegro PCB SI GXL provides a virtual prototyping environment for designs with signals operating in the multi-gigahertz (MGH) frequency range. It offers a completely
More informationIBIS 4.1 Macromodel Library for Simulator Independent Modeling
IBIS 4.1 Macromodel Library for Simulator Independent Modeling Arpad Muranyi, Mike LaBonte, Todd Westerhoff Sam Chitwood, Ian Dodd, Barry Katz, Scott McMorrow, Bob Ross, Ken Willis 1 Agenda History How
More informationTEXAS INSTRUMENTS ANALOG UNIVERSITY PROGRAM DESIGN CONTEST MIXED SIGNAL TEST INTERFACE CHRISTOPHER EDMONDS, DANIEL KEESE, RICHARD PRZYBYLA SCHOOL OF
TEXASINSTRUMENTSANALOGUNIVERSITYPROGRAMDESIGNCONTEST MIXED SIGNALTESTINTERFACE CHRISTOPHEREDMONDS,DANIELKEESE,RICHARDPRZYBYLA SCHOOLOFELECTRICALENGINEERINGANDCOMPUTERSCIENCE OREGONSTATEUNIVERSITY I. PROJECT
More informationInconsistency of EBD (Electrical Board Description) specification in DDR3 DIMM
Inconsistency of EBD (Electrical Board Description) specification in DDR3 DIMM Asian IBIS Summit Yokohama, Japan November 20, 2014 Shogo Fujimori Fujitsu Advanced Technologies s.fujimori@jp.fujitsu.com
More informationHigh-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs. I.K. Anyiam
High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs I.K. Anyiam 1 Introduction LVDS SerDes helps to reduce radiated emissions, but does not completely eliminate them EMI prevention must
More informationMulti-Lingual Modeling Applications and Issues
Multi-Lingual Modeling Applications and Issues Bob Ross June 13, 2002 IBIS Summit Meeting New Orleans, Louisiana Benefits of Multi-Lingual Support Model advances beyond IBIS True differential buffers,
More informationElectrical optimization and simulation of your PCB design
Electrical optimization and simulation of your PCB design Steve Gascoigne Senior Consultant at Mentor Graphics Zagreb, 10. lipnja 2015. Copyright CADCAM Group 2015 The Challenge of Validating a Design..
More informationCadence Power Integrity Solutions For PCBs and IC Packages. May 2013
Cadence Power Integrity Solutions For PCBs and IC Packages May 2013 Simultaneous Switching Noise (SSN) A Power Integrity Issue Design with decaps intentionally removed to demonstrate how poor PI performance
More informationSymbol Parameter Min Typ Max VDD_CORE Core power 0.9V 1.0V 1. 1V. VDD33 JTAG/FLASH power 2.97V 3.3V 3.63V
1 Introduction The user guide provides guidelines on how to help you successfully design the CME-M7 board which includes the power supply, configuration, clock, DDR2 or DDR3, high speed USB, LVDS and ADC
More informationSimulation Using IBIS Models and Pin Mapping Issues
Power/Gnd Simulation Using IBIS Models and Pin Mapping Issues Raj Raghuram Sigrity, Inc. IBIS Summit Meeting, Sep. 13, 2001 2/14/96 Outline Motivation automated Power/Gnd simulation Example of Power/Gnd
More informationPlease visit SMSC's website at for the latest updated documentation.
AN 10.13 Migrating from the LAN83C180 10/100 PHY to the 10/100 PHY 1 Introduction 1.1 Overview This application note discusses how to migrate from an existing design using the SMSC LAN83C180 PHY to SMSC's
More informationSSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions
SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions Patrice Joubert Doriol 1, Aurora Sanna 1, Akhilesh Chandra 2, Cristiano Forzan 1, and Davide Pandini 1 1 STMicroelectronics, Central
More informationEVB-USB2514Q36-BAS, USB2513 and USB Pin QFN Evaluation Board, Revision C User Manual
EVB-USB2514Q36-BAS, USB2513 and USB2512 36-Pin QFN Evaluation Board, Revision C User Manual Copyright 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating
More informationEVB-USB2514Q36-BAS, USB2513 and USB Pin QFN Evaluation Board User Manual
EVB-USB2514Q36-BAS, USB2513 and USB2512 36-Pin QFN Evaluation Board User Manual Copyright 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products
More informationMulti-lingual Model Support within IBIS
Multi-lingual Model Support within IBIS Bob Ross, Vice Chair. January 28, 2002 IBIS Summit, Santa Clara, CA Benefits of Multi-lingual Support Model advances beyond IBIS True differential buffers, current
More informationEvolution of CAD Tools & Verilog HDL Definition
Evolution of CAD Tools & Verilog HDL Definition K.Sivasankaran Assistant Professor (Senior) VLSI Division School of Electronics Engineering VIT University Outline Evolution of CAD Different CAD Tools for
More informationDM9051NP Layout Guide
NP Version: 1.1 Technical Reference Manual Davicom Semiconductor, Inc Version: NP-LG-V11 1 1. Placement, Signal and Trace Routing Place the 10/100M magnetic as close as possible to the (no more than 20mm)
More informationApplication Suggestions for X2Y Technology
Application Suggestions for X2Y Technology The following slides show applications that would benefit from balanced, low inductance X2Y devices. X2Y devices can offer a significant performance improvement
More informationThis Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices.
Course Introduction Purpose This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices. Objectives Learn approaches and design methods
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
More informationTHE DESIGNER S GUIDE TO VERILOG-AMS
THE DESIGNER S GUIDE TO VERILOG-AMS THE DESIGNER S GUIDE BOOK SERIES Consulting Editor Kenneth S. Kundert Books in the series: The Designer s Guide to Verilog-AMS ISBN: 1-00-80-1 The Designer s Guide to
More informationPCB PCB. (dielectric constant) (Crosstalk) ground guard/shunt traces. (termination) side-by-side
PCB 1 PCB PCB PCB ( GHz ) FR-4 GHz (dielectric loss) (dielectric constant) 2 (Crosstalk) ground guard/shunt traces 3 (output impedance)(topology) (termination) 4 ( ) (side-by-side) (over-under) side-by-side
More informationGLAST. Prototype Tracker Tower Construction Status
Prototype Tracker Tower Construction Status June 22, 1999 R.P. Johnson Santa Cruz Institute for Particle Physics University of California at Santa Cruz 1 1 11 2 3 5 4 Prototype Tracker Tower Configuration
More informationREV CHANGE DESCRIPTION NAME DATE. A Release
REV CHANGE DESCRIPTION NAME DATE A Release 7-25-12 Any assistance, services, comments, information, or suggestions provided by SMSC (including without limitation any comments to the effect that the Company
More informationPDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05
PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf
More informationUsing S-parameters for behavioral interconnect modeling
欢迎与会的各位专家! Using S-parameters for behavioral interconnect modeling Asian IBIS Summit Zhu ShunLin 朱顺临 High-Speed System Lab, EDA Dept. ZTE Corporation Zhu.shunlin@zte.com.cn October 27, 2006 Agenda Using
More informationHigh Performance Analog Solutions for Digital World ESD & EMI Product Presentation
ESD & EMI Product Presentation Union Semiconductor Inc. UNION ESD Products 50nm ESD Protechtion Area Gate Oxide Thickness Trend: Chip size decreases to minimum Impact: 12.5nm 8nm Gate Oxide Thickness 4.15nm
More informationApplication Note: AN-146. Guidelines for Effective LITELINK Designs. AN-146-R03 1
Guidelines for Effective LITELINK Designs AN-146-R03 www.ixysic.com 1 1. Introduction Two of the important functions provided by LITELINK to the host systems are high-voltage isolation between the host
More informationBest practices for EMI filtering and IC bypass/decoupling applications
X2Y Component Connection and PCB Layout Guidelines Best practices for EMI filtering and IC bypass/decoupling applications X2Y Attenuators, LLC 1 Common X2Y Circuit Uses EMI FILTERING Conducted and Radiated
More informationEVB-USB2517 Evaluation Board User Manual (Revision A)
EVB-USB2517 Evaluation Board User Manual (Revision A) Copyright 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means
More informationChapter 1 Introduction
Chapter 1 Introduction 1.1 MOTIVATION 1.1.1 LCD Industry and LTPS Technology [1], [2] The liquid-crystal display (LCD) industry has shown rapid growth in five market areas, namely, notebook computers,
More informationCalibrating Achievable Design GSRC Annual Review June 9, 2002
Calibrating Achievable Design GSRC Annual Review June 9, 2002 Wayne Dai, Andrew Kahng, Tsu-Jae King, Wojciech Maly,, Igor Markov, Herman Schmit, Dennis Sylvester DUSD(Labs) Calibrating Achievable Design
More informationAddressing the Power-Aware Challenges of Memory Interface Designs
Addressing the Power-Aware Challenges of Memory Interface Designs One of the toughest challenges in designing memory interfaces is accurately measuring timing while also considering fluctuations in power
More informationFPGA Based Digital Design Using Verilog HDL
FPGA Based Digital Design Using Course Designed by: IRFAN FAISAL MIR ( Verilog / FPGA Designer ) irfanfaisalmir@yahoo.com * Organized by Electronics Division Integrated Circuits Uses for digital IC technology
More information1.4 Other Services Services offered to a broad set of customers, such as product installation and field application support.
1. Services 1.1 Consulting Services Services offered to a unique customer to deliver modified or completed electronic designs, including semiconductor or Semiconductor Intellectual Property (SIP) products,
More informationALLEGRO PCB SI 630 DATASHEET VIRTUAL PROTOTYPING ENVIRONMENT FOR DESIGNS WITH MULTI-GIGAHERTZ SIGNALS THE ALLEGRO SYSTEM INTERCONNECT DESIGN PLATFORM
DATASHEET ALLEGRO PCB SI 630 VIRTUAL PROTOTYPING ENVIRONMENT FOR DESIGNS WITH MULTI-GIGAHERTZ SIGNALS Cadence Allegro PCB SI 630 a key PCB Signal Integrity tool within the Allegro system interconnect design
More informationAdvances in 3D Simulations of Chip/Package/PCB Co-Design
Advances in 3D Simulations of Chip/Package/PCB Co-Design Richard Sjiariel, CST AG Co-design environment Signal Integrity and timing Thermal analysis and stress Power Integrity and noise analysis EMC/EMI
More informationStatus Report IBIS 4.1 Macro Working Group
Status Report IBIS 4.1 Macro Working Group IBIS Open Forum Summit July 25, 2006 presented by Arpad Muranyi, Intel IBIS-Macro Working Group Intel - Arpad Muranyi Cadence Lance Wang, Ken Willis Cisco - Mike
More information+Denotes lead-free/rohs-compliant. J5 1 J10 J13 4 J17 1 L1 1 L2 1 L4 L7 4
19-4156; Rev 0; 5/08 E V A L U A T I O N K I T A V A I L A B L E General Description The MAX3674 evaluation kit (EV kit) is a fully assembled and tested demonstration board that simplifies evaluation of
More informationBGA SSD with EMI Shielding
BGA SSD with EMI Shielding Jong-ok Chun Senior Managing Director Sun System Co.,Ltd www.sunsystem.kr rfjob@sunsysm.com, OCT-2017 Trend of SSD Form-Factor Form Factor - 2.5 Inch - Slim SATA 100x70mm 54x39mm
More informationAOZ8900. Ultra-Low Capacitance TVS Diode Array PRELIMINARY. Features. General Description. Applications. Typical Application
Ultra-Low Capacitance TS Diode Array General Description The is a transient voltage suppressor array designed to protect high speed data lines from Electro Static Discharge (ESD) and lightning. This device
More informationToshiba Case Study RF Module Shrink (TransferJet TM )
Toshiba Case Study RF Module Shrink (TransferJet TM ) These slides are an abridgement of two presentations given by Toshiba at the Zuken Innovation World (ZIW) conference held in Japan in 2012 and 2013.
More informationIP1001 LF DESIGN & LAYOUT GUIDELINES
Index 1 Purpose...2 2 Magnetic trace routing...2 3 Power Supply Plane & GND Plane...3 4 PHY interface...3 5 Trace routing & Placement...3 6 ESD protection...3 7 EMI Supression...3 1/7 April 17 2008. Ver:1.5
More informationEMI/ESD Filters for Cellular Phones
EMI/ESD Filters for Cellular Phones Cellular phones, as with all handheld and wireless devices are susceptible to the damaging effects of Electrostatic Discharge (ESD) transients. As much as 40 kilovolts
More informationDEV-1 HamStack Development Board
Sierra Radio Systems DEV-1 HamStack Development Board Reference Manual Version 1.0 Contents Introduction Hardware Compiler overview Program structure Code examples Sample projects For more information,
More informationTABLE OF CONTENTS 1.0 PURPOSE INTRODUCTION ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2
TABLE OF CONTENTS 1.0 PURPOSE... 1 2.0 INTRODUCTION... 1 3.0 ESD CHECKS THROUGHOUT IC DESIGN FLOW... 2 3.1 PRODUCT DEFINITION PHASE... 3 3.2 CHIP ARCHITECTURE PHASE... 4 3.3 MODULE AND FULL IC DESIGN PHASE...
More informationEMBEDDED SYSTEMS COURSE CURRICULUM
On a Mission to Transform Talent EMBEDDED SYSTEMS COURSE CURRICULUM Table of Contents Module 1: Basic Electronics and PCB Software Overview (Duration: 1 Week)...2 Module 2: Embedded C Programming (Duration:
More informationA Proposal for Developing S2IBISv3
A Proposal for Developing S2IBISv3 Paul Franzon Michael Steer Automated Design Tools for Integrated Mixed Signal Microsystems (NeoCAD) Outline Background DARPA Program NeoCad Program Objectives Program
More informationMicroelettronica. J. M. Rabaey, "Digital integrated circuits: a design perspective" EE141 Microelettronica
Microelettronica J. M. Rabaey, "Digital integrated circuits: a design perspective" Introduction Why is designing digital ICs different today than it was before? Will it change in future? The First Computer
More informationCIRCUIT DESIGN. is published monthly by: UP Media Group Inc Powers Ferry Road, Ste. 600 Atlanta, GA Tel (678) Fax (678)
P R I N T E D CIRCUIT DESIGN is published monthly by: UP Media Group Inc. 2018 Powers Ferry Road, Ste. 600 Atlanta, GA 30339 Tel (678) 589-8800 Fax (678) 589-8850 All material published in this file and
More informationTackling the challenges of System level ESD: from efficient ICs ESD protection to system level predictive modeling
Author manuscript, published in "Taiwan ESD and Reliability Conference, Hsinchu : Taïwan (2013)" Tackling the challenges of System level ESD: from efficient ICs ESD protection to system level predictive
More informationA Qualitative and Quantitative Method for Assessing the Risk of PCB Level Design Changes Affecting EMC Performance
A Qualitative and Quantitative Method for Assessing the of PCB Level Design Changes Affecting EMC Performance Martin O Hara Telematica Systems Limited, Trafficmaster UK, University Way, Cranfield, Beds,
More informationSignal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs
White Paper Introduction Signal Integrity Comparisons Between Stratix II and Virtex-4 FPGAs Signal integrity has become a critical issue in the design of high-speed systems. Poor signal integrity can mean
More informationAllegro Sigrity SI Streamlining the creation of high-speed interconnect on digital PCBs and IC packages
Streamlining the creation of high-speed interconnect on digital PCBs and IC packages The Cadence Allegro Sigrity signal integrity (SI) integrated high-speed design and analysis environment streamlines
More informationElectronic Control systems are also: Members of the Mechatronic Systems. Control System Implementation. Printed Circuit Boards (PCBs) - #1
Control System Implementation Hardware implementation Electronic Control systems are also: Members of the Mechatronic Systems Concurrent design (Top-down approach?) Mechanic compatibility Solve the actual
More informationIC Testing and Development in Semiconductor Area
IC Testing and Development in Semiconductor Area Prepare by Lee Zhang, 2004 Outline 1. Electronic Industry Development 2. Semiconductor Industry Development 4Electronic Industry Development Electronic
More informationJapanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left?
Japanese two Samurai semiconductor ventures succeeded in near 3D-IC but failed the business, why? and what's left? Liquid Design Systems, Inc CEO Naoya Tohyama Overview of this presentation Those slides
More information10/100 Application Note General PCB Design and Layout Guidelines AN111
10/100 Application Note General PCB Design and Layout Guidelines AN111 Introduction This application note provides recommended guidelines in designing a product that complies with both EMI and ESD standards
More informationRClamp TM 0504M RailClamp Low Capacitance TVS Diode Array PRELIMINARY Features
Description RailClamps are surge rated diode arrays designed to protect high speed data interfaces. The RClamp series has been specifically designed to protect sensitive components which are connected
More informationLecture 1. Course Overview and The 8051 Architecture
Lecture 1 Course Overview and The 8051 Architecture MCUniversity Program Lectures 8051 architecture t System overview of C8051F020 8051 instruction set System clock, crossbar and GPIO Assembler directives
More informationEDA: Electronic Design Automation
EDA: Electronic Design Automation Luis Mateu Contents What is EDA The Phases of IC design Opportunities for parallelism 2006 Synopsys, Inc. (2) Electronic Design Automation? The software tools engineers
More informationControl System Implementation
Control System Implementation Hardware implementation Electronic Control systems are also: Members of the Mechatronic Systems Concurrent design (Top-down approach?) Mechanic compatibility Solve the actual
More informationGRAPHICS CONTROLLERS APIX PCB-DESIGN GUIDELINE
Fujitsu Semiconductor Europe Application Note an-mb88f33x-apix-pcb-design-guideline-rev1-10 GRAPHICS CONTROLLERS MB88F33X INDIGO2(-X) APIX PCB-DESIGN GUIDELINE APPLICATION NOTE Revision History Revision
More informationGuide To Making Schematic Components For ExpressSCH
Guide To Making Schematic Components For ExpressSCH The ExpressSCH program includes hundreds of components and symbols that you can use to draw your schematics. However, sometimes we may not have all of
More informationMMA043AA Datasheet 0.5 GHz 12 GHz GaAs phemt MMIC Wideband Low-Noise Amplifier
MMA043AA Datasheet 0.5 GHz 12 GHz GaAs phemt MMIC Wideband Low-Noise Amplifier Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA:
More informationLPB Copyright JEITA EDA-TC LPB-WG All Rights Reserved /12/15 Page1
LSI Package Board needs Mutual Communication Design Consistency Shorten Development Time Enabled by LPB New Standard format LPB Copyright JEITA EDA-TC LPB-WG All Rights Reserved 2013 2013/12/15 Page1 Introduction
More informationPrepared by: Jim Lepkowski ON Semiconductor
Application Hints for Transient Voltage Suppression Diode Circuits Prepared by: Jim Lepkowski ON Semiconductor APPLICATION NOTE INTRODUCTION Transient Voltage Suppression (TVS) diodes provide a simple
More informationRenesas New Generation of R8C/Tiny Series MCUs Adds 1.8V Support and Coprocessing With Background Operation to Enable Low-cost Innovative Designs
PRESS CONTACT: Akiko Ishiyama Renesas Technology America, Inc. (408) 382-7407 akiko.ishiyama@renesas.com Renesas New Generation of R8C/Tiny Series MCUs Adds 1.8V Support and Coprocessing With Background
More informationParag Choudhary Engineering Architect
Parag Choudhary Engineering Architect Agenda Overview of Design Trends & Designer Challenges PCB Virtual Prototyping in PSpice Simulator extensions for Models and Abstraction levels Examples of a coding
More information+Denotes lead(pb)-free and RoHS compliant. FOUTL-, FOUTL+, FOU TR-, FO U TR+, V D D, P G N D
19-4071; Rev 1; 9/09 MAX9736A Evaluation Kit General Description The MAX9736A evaluation kit (EV kit) is a fully assembled and tested printed-circuit board (PCB) that configures the MAX9736A Class D amplifier
More informationTHM3060. Multiple Protocols Contactless Reader IC. Features. Pinning Diagram
THM3060 Multiple Protocols Contactless Reader IC Features Compatible with ISO/IEC 14443 A/B Support higher baudrate up to 848 Kbit/s Compatible with ISO/IEC 15693 Host interface selectable: UART,SPI and
More informationWill Silicon Proof Stay the Only Way to Verify Analog Circuits?
Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Pierre Dautriche Jean-Paul Morin Advanced CMOS and analog. Embedded analog Embedded RF 0.5 um 0.18um 65nm 28nm FDSOI 0.25um 0.13um 45nm 1997
More informationBurn-in & Test Socket Workshop
Burn-in & Test Socket Workshop IEEE March 4-7, 2001 Hilton Mesa Pavilion Hotel Mesa, Arizona IEEE COMPUTER SOCIETY Sponsored By The IEEE Computer Society Test Technology Technical Council COPYRIGHT NOTICE
More informationThis Part-A course discusses techniques that are used to reduce noise problems in the design of large scale integration (LSI) devices.
Course Introduction Purpose This Part-A course discusses techniques that are used to reduce noise problems in the design of large scale integration (LSI) devices. Objectives Understand the requirement
More informationBoard design and IBIS simulation in consideration of the delay control
Board design and IBIS simulation in consideration of the delay control Asian IBIS Summit Tokyo, JAPAN November 16, 2015 Makoto Matsumuro IB-ELECTRONICS IB-ELECTRONICS Page 1 Agenda Results of the simulation
More informationAn Introduction to Programmable Logic
Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor
More informationAN-1055 APPLICATION NOTE
AN-155 APPLICATION NOTE One Technology Way P.O. Box 916 Norwood, MA 262-916, U.S.A. Tel: 781.329.47 Fax: 781.461.3113 www.analog.com EMC Protection of the AD7746 by Holger Grothe and Mary McCarthy INTRODUCTION
More informationShort Course On Phase-Locked Loops and Their Applications Day 3, PM Lecture. Behavioral Simulation Exercises
Short Course On Phase-Locked Loops and Their Applications Day 3, PM Lecture Behavioral Simulation Exercises Michael H Perrott August 13, 2008 Copyright 2008 by Michael H. Perrott All rights reserved. A
More informationProduct Specification 4.3 COLOR TFT-LCD MODULE
Doc. Total Page 16 Date 2008/05/23 Product Specification 4.3 COLOR TFT-LCD MODULE MODEL NAME: C043GW01 V0 < < >Final Specification Note: The content of this specification is subject to change. 2006 AU
More informationThermocouple Sensor Board Version 2 SP1202S05RB Users' Guide
June 2009 Rev - 1.1 Thermocouple Sensor Board Version 2 SP1202S05RB Users' Guide 2009 National Semiconductor Corporation. Table of Contents 1 http://www.national.com 1.0 Introduction... 3 2.0 Board Assembly...
More informationVladimir Tsarkov Electrical Engineering
. Travis Ram William Brumby Electrical Engineering Gaston Mulisanga Computer Engineering Computer Engineering Vladimir Tsarkov Electrical Engineering Motivation Traditional meters offer little assistance
More informationPSMC Roadmap For Integrated Photonics Manufacturing
PSMC Roadmap For Integrated Photonics Manufacturing Richard Otte Promex Industries Inc. Santa Clara California For the Photonics Systems Manufacturing Consortium April 21, 2016 Meeting the Grand Challenges
More informationInternational standards affecting embedding technology
International standards affecting embedding technology Walter Huck, Murata Europe Chris Hunt, NPL 22.09.2016 IMAPS Embedding Conference 1 Innovation & Standardization Identify stakeholders, scope and propose
More informationCreating Xnets for Resistor Packs in Allegro PCB Editor. Product Version SPB16.6 April 2, 2014
Creating Xnets for Resistor Packs in Allegro PCB Editor Product Version SPB16.6 April 2, 2014 Copyright Statement 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence
More informationMAX3872/MAX3874 Evaluation Kits
9-2767; Rev 0, 2/03 MAX3872/MAX3874 Evaluation Kits General Description The MAX3872/MAX3874 evaluation kits (EV kits) simplify evaluation of the MAX3872 and MAX3874 clock and data recovery with limiting
More information