EC4205 Microprocessor and Microcontroller

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1 EC4205 Microprocessor and Microcontroller Webcast link: All announcement made through webpage: check back often Students are welcome outside the class (right after class) Dr. A. Islam Dept. of ECE BIT, Mesra, Ranchi Prepared and presented by Dr. A. Islam 1

2 EC4205 Lecture notes based on material From me, Prof. (Dr.) R. Sukesh Kumar and following text books: 1. Digital Computer Electronics, 2/e, by A. P. Malvino. 2. Microprocessor Architecture, Programming and Applications with 8085, by R. S. Gaonkar. 3. Microprocessor and Interfacing, Programming of Hardware, by D. Hall. 4. Microprocessor and Peripherals, by S. P. Chowdhury and S. Chowdhury. 5. INTEL 8086/8088 Microprocessor, Architecture, Programming, Design and Interfacing, 3/e, by B. S. Chhabra. 6. Microprocessor, Microcomputer and their Applications, 2/e, by A, K. Mukhopadhyay. 7. The Intel Microprocessors 8086/888, 80186/80188, 80286, 80386, 80486, Pentium and Pentium Pro processor architecture, programming and interfacing, 4/e, by B. B. Brey. 8. Microprocessors with applications in process control, by SI Ahson. 9. Microprocessors theory and applications: Intel and Motorola, by M. Rafiquzzaman. Use the material without violating copyright act involved with original books. Prepared and presented by Dr. A. Islam 2

3 Module-I: Outline 1. with emphasis on control lines 2. SAP concepts with stress on timing diagrams 3. Microinstructions 4. Microprogramming 5. Variable machine cycle 6. Architecture of 8085 Processor 7. Functions of all signals 8. Bus concepts 9. Multiplexed and De-multiplexed Bus 10.Minimum system Prepared and presented by Dr. A. Islam 3

4 D IN D IN (8-bit) Controlled shift left parallel load register LOAD ENABLE CLK Accumulator of 8085 SHL LOAD CLK SHR ENABLE D OUT D OUT (8-bit) Accumulator of 8085 may have SHL, SHR, LOAD, ENABLE, CLK, but B, C, D, E, H, L are parallel load only and may have ENABLE signal for tristate output. Prepared and presented by Dr. A. Islam 4

5 If JK inputs are controlled & that is called COUNT and if COUNT can be made HIGH or LOW then the above ripple counter will count only when commanded i.e., COUNT is made high. When COUNT is LOW, it will not count. Prepared and presented by Dr. A. Islam 5

6 In SAP-1, the CLR signal goes to any ckt that uses an active high clear and the CLRbar signal to any ckt with an active low clear. That s why CLRbar goes to the counter of Fig. 8.11; it has an active low clear. The similar idea apply to clock signal also. The is dual JK Master-slave FF. The SAP-1 program counter uses two 74107s. Although not shown, pin 14 ties to 5V & 7 to ground. Because master-slave FFs are used, a high CLRbar clocks (enables) the master & a low CLRbar triggers the slave. Before computer run operator pushes a clear button that sends a low CLRbar to program counter. This resets count to Q=0000 Prepared and presented by Dr. A. Islam 6

7 Fig. 8.16(Malvino) SAP-1 ring counter is a dual JK master-slave FF, previously used in SAP-1 program counter. The FFs are connected in a rotate left mode. Since does not have a preset input, the Q 0 FF is inverted so that its Qbar o/p drives the J i/p of the Q 1 FF. In this way a low CLRbar produces the initial timing word T1 and subsequent CLK pulses generates other timing words: T = = T1 T = = T2 T = = T3 T = = T4 T = = T5 T = = T6 Then the cycle repeats. Fig. 8.16(Malvino) SAP-1 ring counter Prepared and presented by Dr. A. Islam 7

8 To fetch and execute instructions, a computer has to activate various ckts at precisely the right time and in the right sequence. This is where ring counter comes in use. It produces ring words for timing different operations during a computer run. In SAP-1 ring counter T6 to T1 are called timing signals. Fig. 8.17(Malvino) SAP-1 ring counter timing diagram Prepared and presented by Dr. A. Islam 8

EC4205 Microprocessor and Microcontroller

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