CANBus in the DCS FE. Valerio Bocci. INFN sez. Roma

Transcription

1 CANBus in the DCS FE Valerio Bocci INFN sez. Roma

2 CAN BUS. Controller Area Network (CAN) is designed to provide an efficient, reliable and very economical link. CAN communicate at speeds up to 1Mbit/s with up to 40 devices. its use has spread in machine and factory automation products thanks to its outstanding features: - Any node can access the bus when the bus is quiet - Non-destructive bit-wise arbitration to allow 100% use of the bandwidth without loss of data - Variable message priority based on 11-bit packet identifier - Multimaster, peer-to-peer, and multi-cast reception - Automatic error detection, signaling and retries - Data packets 8 bytes long.

3 CANbus format Arbitration Data Format

4 CAN Bus physical parameters

5 CANopen CANopen is a networking system based on the CAN serial bus. CANopen assumes that the device s hardware has a CAN transceiver and CAN controller as specified in ISO CANopen profile family specifies standardized communication mechanisms and device functionality. The profile family is available and maintained by CAN in Automation (CiA), the international users license-free.

6 Communication Protocol

7 Connection of CAN bus nodes 9U Board 9U Board I2C I2C CAN node JTAG SPI CAN node JTAG SPI Parallel I/O Parallel I/O 9U Board 9U Board I2C I2C CAN node JTAG SPI CAN node JTAG SPI Parallel I/O Parallel I/O

8 JTAG Boundary SCAN The IEEE ( JTAG )standard defines a four-wire serial interface (a fifth wire is optional) to access complex integrated circuits (ICs) such as microprocessors, DSPs, ASICs, andcplds. Any compatible IC contains shift registers and a state machine to execute the boundary-scan functions. In-system programming of flash memories and PLDs (CPLDs and FPGAs) is quick and easy using JTAG Technologies. Data can then be sent to the IC and read from it using the serial interface. This data may be used to stimulate the device core, drive signals outward to the PCB, sense the input pins from the PCB, or sense the device outputs. The scan modes of operation provide the ability to test a board for manufacturing structural faults and to perform in-system device program-ming all via the standard JTAG TAP.

9 The I2C Bus. The I2C bus was developed in the early 1980's by Philips semiconductors. It's purpose was to provide an easy way to connect a CPU to peripheral chips in a TV-set. The research done by Philips Labs in Eindhoven (The Netherlands) resulted in a 2 wire communication bus called the I2C bus. I2C is an acronym for Inter-IC bus. It's name literally explains it's purpose: to provide a communication link between Integrated Circuits. Nowadays the extent of the bus goes much further than Audio and Video equipment. The bus is generally accepted in industry. The I2C BUs has been adopted by several leading chip manufacturers like : Xicor, SGS-Thomson, Siemens, Intel, TI, Maxim, Atmel, and Analog Devices.

10 CAN node connections Data from Muon boards I/O Delay Chip DAC ADC ASD Threshold CAN node I2C DAC/ ADC ASD Threshold Transceiver Logic CAN Controller Chip SPI 8/16 bit Microcontroller node controller I2C BUS ext. I2C <100 mt. DAC/ ADC ASD Threshold ADCs Physical Parameters of the chamber T,P,HV JTAG Configuration Flash PROM Configuration Flash PROM Configuration Flash Prom Connectivity SCAN Board Test Chips with JTAG SCAN FPGA FPGA FPGA

11 Suppliers of CAN products Semiconductors Software Tool CANopen Manager Remote Module Alcatel/Mietec Bosch Dallas Semiconductor Fujitsu Hitachi IAM/SICAN Infineon Inicore Intel Intermetall Microchip Mitsubishi Motorola National Semiconductor NEC OKI Philips STMicroelectronics/S GS-Thomson Temic Texas Instruments Toshiba Unitrode EMS ESD I+ME Incaa infoteam Intulogic Ixxat Janz port Softing Systec Vector Applicom CAN in Automation Deutschmann EMS Hilscher HMS I+ME Ixxat Janz, port Softing Sontheim Systec Vector Antal Baldor Beckhoff Berghof Hesch Hilscher IFM Inter Control, Ixxat Janz PMA Schleicher SIG Positec, Softing Teko Arteco Bebro Bernstein Bosch Elotech frenzel + berg HBM IFM, 2 Industrial Software Intulogic, Micro-key MKT, 2 PMA, 2 Phytec Schleicher SIG Positec Syslogic

12 Suppliers of CAN products I/O Device Actuator Sensor Interface Arteco Automata Beckhoff, Bernstein Bosch, CD Systems Eckelmann EMS ESD frenzel + berg Hesch Hirschmann. Incaa Inter Control Janz Keba Micro-key MKT, Moeller Electronix, Schleicher, SIG Positec SMC Sontheim TR-Systemtechnik UniControls Wago Wieland Yacoub Arteco Bosch, Control Techniques Datron D-Tech Ever Elettronica Inmotion Technologies, 2 Kollmorgen Seidel Maccon Metronix Micro-key TR-Electronic Yaskawa MTS Balluff Druck Dynisco Fraba, 2 Hengstler IFM IVO Kübler Leine & Linde Trafag TR-Electronic TWK-Elektronik GmbH Wika Applicom Beckhoff EMS ESD, 2 Hilscher Hitex Automation HMS Ixxat Sontheim TR-Systemtechnik Vector

13 Embedded Local Monitor Board ELMB ATLAS CERN & Nikhef project. The ELMB is a general-purpose plug-in board. low cost <150 CHF/board It is based on an AVR microcontroller ATmega kbytes of on-chip flash memory, 4 kbytes of SRAM 4 kbytes of EEPROM. There is a second microcontroller AT90S2313 for in system programming and monitoring functions. The CAN controller is based on a SAE81C91 I/O lines:?6 external interupt inputs?port A 8 digital bi-directional I/O lines (can alternatively be used for external SRAM).?Port C 8 digital output lines (can alternatively be used for external SRAM).?Port D 6 digital bi-directional I/O lines?port E 5 digital bi-directional I/O lines?port F 8 digital input lines or 8 analog inputs for the ADC?JTAG?I2C

14 Fault detection and Fault Tollerance to SEU Canopen Life Guarding any Master=>broadcast Nodeguarding msg if the slave does not receive the msg reset and send a emergency msg The ELMB has two microcontroller one Master and one slave and implement an activity monitor: Master Slave Master Slave The Slave act has watch-dog of the master. If the Slave does not answer the master sen a msg to CAN. The ELMB add a CRC-checksum to each block of data or parameters it saves in EEPROM. A CRC can be added at the END of flash CODE.

15 Xilinx in muon-lhcb enviroment Device X sect =6.49 *10-9 cm 2 one SEU each 4.3 hours Device X sect <5 *10-12 cm 2 one SEU each 4 years. FPGA Real configuration 160 Kbits <1 Krad /10 yr lhcb muon Edge of LHCb muons =10 11 hadrons/cm 2 yr 8bits x 33Mhz SelectMap ~ 5 ms configuration time Flash 1.3 Mbits JTAG (Max 8 Mbit/s Kbits/s 2.6 sec ==> 10 4 hadrons/ cm 2 sec DCS node

16 FPGA initialization INIT LOAD Configuration From Flash OK? NO CAN MSG wrong Flash YES YES Background read-back ERASE & PROGRAM FLASH ROM OK NO FPGA programming using JTAG OK Check CRC No Valerio Bocci 2000

17 Configuration SEU recovery system FPGA init Init _fail jtag Local Task CAN Node FlashRom Continuos readback from the? controller in thecannode init in case of wrong configuration. Test of init fail after configuration CanMessages: =>life guarding =>wrong xlnx config =>wrong init <=program Flashrom CAN Master Valerio Bocci 2000