Dr. Ajoy Bose. SoC Realization Building a Bridge to New Markets and Renewed Growth. Chairman, President & CEO Atrenta Inc.

Transcription

1 SoC Realization Building a Bridge to New Markets and Renewed Growth Dr. Ajoy Bose Chairman, President & CEO Atrenta Inc. October 20, Atrenta Inc.

2 SoCs Are Driving Electronic Product Innovation SoC 2

3 Re-energizing the Semiconductor Industry System value is increasingly realized through system SoCs SoCs driving a new ecosystem SoCs are in everything Significant opportunity for the semiconductor industry by supporting this trend Reduce the barriers for adoption SoCs increase semiconductor gross margins Billions of units primarily in mobile phones, infrastructure & consumer 3

4 Today s SoC Not Just an IC Business Any Longer Typical Characteristics ARM DSP Standard Fabric TSMC Graphics Typically contains: Multi-CPU, DSP cores, graphics blocks, one or more fabrics, many IPs from diverse sources ARM & TSMC are the 800 lb. gorillas driving their own ecosystem Differentiate through peripherals and software Optimization for power, performance and area/cost (PPA) 4

5 But Many Challenges Face SoCs Business cost & time to market Technology Complexity Emerging industry trends 5

6 SoC Design Cost/Risk is Out of Control Increasing complexity means increased risk At 32nm, a typical design has ~50% chance to meet all objectives At 22nm, that number drops to ~30% SoC Development Cost Designer productivity must improve to match chip complexity The later a problem is detected, the more impact it will have on design schedules Source: Gartner Source: I.B.S. Inc. 6

7 Cost ($M) Consequence Less Opportunity Required Revenues Total Costs 0 90nm (60M) 65nm (90M) 45nm (120M) 32nm (150M) 22nm (180M) Feature Dimension (Transistor Count) Source: International Business Strategies 7

8 IC Vendors Must Deliver Complete Solutions IC vendors are expected to deliver the complete solution not just the chip The customers want their IC vendors to provide an increasing part of the application architecture and functionality, which includes both the software as well as the hardware. IC Vendor Product Portfolio Source: I.B.S. Inc. 8

9 Emerging Industry Trends Globalization of Work Flow IP Global Team #1 Global Team #2 Chip Integration Team Derivatives Changing Role of System Houses 9

10 Verified Clean IP Reduces Risks IP suppliers internal & external SoC teams internal & end-customer IP supplier 1 Chip project 1 IP1 IP supplier 2 IP supplier 3 IP Handoff Kit IP 2 IP 3 IP Accept. Kit Chip project 2 Chip project 3 Test Test IP supplier n Power Timing Clocks IP n Power Timing Clocks Chip project n Congestion Congestion Supporting files Supporting files 10

11 Platforms & Derivatives System Company Platform IP 1 IP 2 Silicon Company Error free, well designed IP Consistent methodology Access to special capabilities power management, BIST, Good hand-off Vendor portability Visibility, no surprises Error free, well designed IP Consistent methodology Good hand-off Rapid modification & integration No surprises By 2012, greater than 80% of 32nm SoC revenue will come from platform-based designs (Gartner) 11

12 PPA What Does It Mean PERFORMANCE Fabric generator Architectural behavior model-based SoC designer IP Library POWER Fabric & IP iteration SoC Assembly Make sure that the specs will be met before actually building the SoC AREA Physical SoC optimized for Silicon Realization 12

13 Changing Role of System Houses Want more control over their SoC Vendor independence single flow, deferred commit Differentiated IPs from independent sources Visibility & tracking 13

14 Recap: What s the Problem? SoCs are driving a new level of product innovation BUT SoC design cost is too high So are re-spin rates IP reuse is critical to success, but difficult & costly IC vendors need to deliver the complete solution Hardware, software, architecture Implementation readiness is crucial before P&R starts 14

15 The Answer: SoC Realization* System Realization Correct product definition Enterprise-level OS, middleware End user applications SoC Realization New EDA IP Reuse & assembly HW/SW optimization * With attribution to Cadence Correct SoC definition EDA Classic Synthesis, P&R Tapeout Silicon Realization 15

16 The Architecture of SoC Realization Application specifications Semiconductor IP Internal/3 rd party Ad hoc/structured IP qualification Software virtual prototype Structured ass y IP/platform reuse HW/SW Co-optimization Design exploration Define architecture (HW & SW) Choose correct IP Assemble chip Analyze, verify & optimize RTL analysis & optimization EDA Classic Implementation readiness 16

17 Ve r i f i c a t i o n I P L i b s & M o d e l s Quality & integration issues The SoC Design Flow Where is the Leverage? Software Virtual Prototype Instruction Approximate Cycle Accurate System Design Manufacturabilit y not yet known Hardware Virtual Prototype Assemble the Chip Mature the Design to an Implementation Ready State SoC Realization Early enough to fix problems easily Enough detail to find real problems Build the Actual SoC Physical Implementation Tapeout Classic EDA Too late to make a difference 17

18 EDA Classic SoC Realization V e r i f i c a t i o n System Design Components of the Process Application specs Instruction approximate model OS level Instruction accurate model Appl. scenarios Cycle accurate model Driver & perf. High-level synthesis IP Libraries & Models Structured assembly Register maps PPA analysis Linting Power DFT CDC Timing Congestion Implementation readiness Synthesis Place & Route Extraction/Verif. 18

19 What Does This Mean for EDA? A game-changing opportunity is opening for the EDA industry Focused solutions for the system SoC Facilitate IP supply chain creation, QC, handoff HW/SW solutions Coherence, virtual prototype Assembly, PPA analysis, implementation readiness 19

20 SoC Realization Ecosystem Large and expanding ecosystem System Co IP Supplier SpyLinks SoC Realization EDA Vendors Program Foundry Semis Unprecedented level of partnership & collaboration necessary Enabled by a rich set of standards 20

21 Reducing SoC Cost Will Grow Semiconductor Industry Reduce total SoC costs by reducing chip integration costs while growing IP content Chip Integration And Verification SOC Cost MKTA $250M MKTB $230M MKTF $120M MKTD $160M MKTE $140M MKTL $100M MKTC $180M MKTL $100M MKTG $80M MKTH $70M MKTJ $50M Available Market Customer IP 3 rd Party IP SoC s Potential Markets 21

22 21st Century The Information Economy...the long discussed convergence of computing, communication, content, control 18 October 2011 valuation XOM $US 384B AAPL $US 391B 22

23 Conclusion Industry leaders recognize the power of SoCs leverage in creating the killer apps Showtime has started Intel Atom and foundry services, Microsoft Windows on ARM, Represents a discontinuity for semiconductors/eda/ip SoC Realization provides high design leverage and is a major enabler of this trend Will require significant collaboration across the ecosystem 23

24 Thank you! 2011 Atrenta Inc.