University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS150, Spring 2010

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1 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS10, Spring 010 Homework Assignment 7 Solutions: Memories and Video 1. Your task is to implement a 3K x 3 memory. Assume you are given 3Kit configurale memory locks such as a lock RAM in a FPGA. Each lock can e configured as a 3K x 1it memory or a 1K x 3it memory. Which option would you choose as a uilding lock for your 3K x 3it memory and why? Drawing the 3Kx3 memory using each of the uilding locks, it seems clear that 3Kx1 uilding lock is the est choice. It uses the least extra logic and therefore could have etter performance and lower area cost. Using the 3Kx1 memories, the larger memory can e constructed y simply using the one it from each lock as one of the 3 its of data. On writes, the address goes to all locks, writeenale is asserted for all, and one of the 3 its goes to each lock. Using the 1Kx3 memories, each data word is stored in one of the 3 locks. So, for reads, part of the address chooses the word inside the locks and the rest of the address chooses etween the data from the locks. For writes the datain goes to all locks ut only the appropriate writeenale is asserted, determined y a decoder. So, the 1Kx3 implementation requires an extra 3:1 decoder and a 3-it wide 3:1 mux; this is a lot of extra hardware and if oth memory locks are assumed the same, then performance is also worse ecause of the extra delay through the decoder on writes and mux on reads. 1

2 . (a) Write a parameterized memory in Verilog. module RAM( Clock, WAddress, RAddress, WE, DataIn, DataOut ) ; parameter Width = 16, Depth = 104 4, SynchronousRead = 0 ; / / assume a macro l o g i s d e f i n e d localparam AWidth = l o g ( Depth ) ;

3 input Clock ; input [ AWidth 1:0] WAddress, RAddress ; input WE; input [ Width 1:0] D a t a I n ; output [ Width 1:0] DataOut ; reg [ Width 1:0] mem [ Depth 1 : 0 ] ; reg [ AWidth 1:0] ReadAddress p ; ( posedge Clock ) egin i f (WE) egin mem[ WAddress ] <= DataIn ; end end g e n e r a t e i f ( SynchronousRead ) egin ( posedge Clock ) egin ReadAddress p <= RAddress ; end a s s i g n DataOut = mem[ ReadAddress p ] ; end e l s e egin a s s i g n DataOut = mem[ RAddress ] ; end endgenerate endmodule () Create a Xilinx ISE project and add your RAM module. Set the parameters to implement each of the following memories. For each, record the type of resource used, the percentage of this type of resource that is used up, and the memory configuration used. This information is near the ottom of the synthesis report. i. depth=3, width=1, SynchronousRead=0. Dual Port Rams (RAM3X1D): 1 LUTs: (0%) ii. depth=4096, width=16, SynchronousRead=0. Dual Port Rams (RAM18X1D): 1 LUTs: 40 (3%) iii. depth=3*104, width=3, SynchronousRead=1. Block Rams : 3 of 148 (1%) 3. We want to uild a 3 x 3it register file, with read ports and 1 write port, on an FPGA. Refer to Virtex- FPGA User Guide (ug190.pdf) on the Documents page for this prolem. (a) Build the register file from Block RAM, using as few resources as possile. Description of Virtex- Block RAM can e found starting at pg.109 of the User Guide. Draw your design and give a rief description, including what configuration is used. 3

4 WD RD1 WADDR WEN 1 RA1 18K BlockRAM, SDP mode RD 1 RA 4 18K BlockRAM, SDP mode

5 To get a data width of 3, we can use a 18K BlockRAM in simple dual-port mode, which allows up to 36 it data width and independent read and write. We need reads and 1 write on every cycle, so we need to replicate the BlockRAM memory to gain an extra read port. The write port for oth RAMs will use the same signals. Using BlockRAMs for a 3x3 regfile wastes most rows in the memory. () Build the register file from Distriuted RAM (LUT RAM), using as few resources as possile. The asic primitives are found on pg.07 of the User Guide. There may also e useful information within Chapter : Configurale Logic Blocks (CLBs). Draw your design and give a rief description, including what configuration is used. RA0 RD0 RA1 3x memory (1 write, read) WAddr RD1 WData WE RA0 RA1 RA0 RA1 WAddr WData WE RD0 RD1 RD0 RD1 16 memories total RA0 RA1 WAddr WData WE RD0 RD1 To get a data width of 3 and multiple ports, we choose the LUTRAM 3x Quad port

6 configuration. One port is the SLICEM write signals, which go to all 4 LUT6 s within the SLICEM. Two LUTs, with their independent read addresses can provide the two read ports. The fourth LUT6 is unused (technically the first one is too, ut we need to use its address signals for write address). Inside each LUT6, the two LUT s that comprise it each provide a it of data, and we know that a LUT has 3 its of state, thus 3x memory. We can compose 16 of these 3x 1WR memories in parallel to get the 3-it data width. (c) Assume the rough area costs elow: Component Area (µm ) LUT 80 LUT BRAM BRAM FlipFlop 100 i. Approximately how much area does it take for 36Kits of storage using: A. Block RAM? 36Kit*(1 BRAM36/36Kit) = µm B. LUT RAM? 36Kit*(1 LUT6/64it) = 97900µm C. FlipFlops? 36Kit*(1 FF/1 it) = µm ii. How much area does each of your register file implementations require? A. Block RAM. *BRAM18 = µm B. LUT RAM. 3 LUT6 per quad port 3x memory (when excluding unused fourth port). Need 16 of these in parallel to have 3-it wide data. 16*3*LUT6 = 81600µm. C. FlipFlops (estimate ased on numer of flipflops, as well LUTs for surrounding logic). Each it of :3 decoder (with WE input) can fit in a LUT6, so 3 LUT6 for decoder. 3*3=104 FlipFlops for the memory. 10 LUT6 for each it of the 3:1 Mux. For 3 data width, we use 3 copies of this, so: 10*3=30 LUT6. We have two read ports, so muxes: *30 = 640 LUT6. This is one possile mapping of the 3:1 Mux to LUTs. Below is a schematic of 1 copy (1-it wide 3:1 Mux). 6

7 LUT6 4:1 MUX LUT6 4:1 MUX 3 choices 8 LUTs total F7Mux DataOut 4:1 MUX 4:1 MUX LUT6 LUT6 ( ) LUT F F = µm A more efficient implementation of the 3:1 mux is to use the F7Muxes and F8Mux to create a 16:1 Mux. Two of these 16:1 Muxes can e comined with a :1 Mux (using another LUT). This adds up to 9 LUT6 s per 1-it 3:1 Mux. (3 + 76) LUT 6 = µm From this exercise we first see that BlockRAM is the most dense memory (approximately 10x more dense than flipflops) and desirale for larger memories. We also saw an example of how different memory types compare for a given application. For a 3x3it register file, BlockRAM wastes resources ecause we need two to have enough ports, ut each Block- RAM already has far more space than needed. LUTRAM takes only 81600µm despite needing a replica of the data for each port. Flipflop memory does not need to e replicated for 1 write port and any numer of read ports, ut since it is less dense, the flipflops themselves are more area (aout 0000µm more) than the LUTs, and also need surrounding logic: decoder for writes and muxes for reads. 4. We are using a 800x600 display at 7Hz, meaning 7 frames are sent to the display every second. (a) What is the pixel rate? 800 pixels/line * 600 lines/frame * 7 frames/sec = pixels/sec () For 4-it color, what is the data rate? pixels/sec * 4 it/pixel = it/sec 7

8 (c) What is the pixel frequency (clock used y display) for sending pixels to our 7Hz display? let h=lines/frame, w=pixels/line, h=horizontal lanking interval, v=vertical lanking interval, fr=frame rate, pf=pixel frequency (the unknown) h (w/pf + h) + v = 1/fr 600lines/f rame ((800pixels/line)/pf µs) ms/f rame = 1/7sec/f rame pf = 800/((1/ )/ ) pf = pixels/sec (d) What is the horizontal lanking interval in terms of numer of pixels? One way to think of lanking intervals is as additional display area offscreen as shown elow. 800 pixels Horiz. lanking 600 lines Visile display Vert. lanking Virtual lanking area We know the pixel frequency from (c) and just multiply this y the horizontal lanking interval to get how many pixels. pf h pixel/sec s = 6pixels What is the vertical lanking interval in terms of numer of lines? Part (c) mentioned that the vertical lanking interval is like writing extra offscreen lines at 8

9 the end of each frame. We know the time per line (including lanking interval) y plugging in the pixel frequency. Divide the vertical lanking interval y time per line to get numer of lines. v/(w/pf + h) /((800pixels/line)/( pixels/sec) ) lines The spec for the display used in this prolem can e found at Suppose we implement our 800x600 pixel frameuffer using the Block RAM resources on our XCVLX110T FPGA. You can look in Virtex- Family Overview on the Documents page of the wesite for the resources availale on different Virtex- FPGA models. Suppose half the Block RAMs on the fpga are eing used for our instruction and data memories already, leaving half for the frameuffer. (a) How many its are availale for each pixel? The Family Overview says there are,38ki of BlockRAM memory on the FPGA /( ) = its/pixel The prolem says half of the BlockRAMs are availale so.683 its/pixel. There is not a - it data width configuration for BlockRAMs, so if we were implementing this frameuffer, we might store each pixel across BlockRAMs, using the 3Kx1 configuration (although the addressing may e easier if we just used 4-it pixels and the 8Kx4 configuration). () How many distinct colors can e represented? (Let this numer e hereafter called N) its per pixel to encode the color. = 3 = N. (c) Recall that our video interface supports 4-it color. How can you use a relatively small memory to allow any N of the 4 displayale colors to e used at a given time? Draw a high level lock diagram of the frameuffer, video interface, and the extra memory lock implementing this functionality. Specify the dimensions of the small memory. 9

10 ReadCoordX ReadCoordY Frameuffer (implemented with Block RAMs) N Pixel Address Small Memory DOut Color 4 VideoInterface The small memory is 3x4 it. It has 3 4-it color entries. This tale turns a -it color code into a 4-it color. Thus, at one time we can display up to 3 out of the 4 displayale colors. (d) The CPU should e ale to write to this small memory (sometimes called a Colormap ) to change the colors eing used and even do short animations efficiently. Suppose the Colormap is in the CPU memory map at addresses 0xA xA000007C (rememer memory is yte addressed ut we only use word loads and stores so the least significant its of the address are always zero). Suppose initially oth the frameuffer and Colormap are filled with 0 s in every memory location. Fill in the code in main() that does an animation of a green vertical ar moving across the screen, with a lack ackground. Make 10

11 the animation occur at roughly frames per second. Notice helpful functions sleep() and framebufferaddress() are provided. void s l e e p ( long d e l a y ) { / /... makes CPU w a i t f o r d e l a y m i l l i s e c o n d s... i n t f r a m e B u f f e r A d d r e s s ( i n t x, i n t y ) { / /... r e t u r n s t h e f r a m e u f f e r memory a d d r e s s / / c o r r e s p o n d i n g t o p i x e l ( x, y )... i n t main ( ) { i n t BLACK = 0 x ; i n t GREEN = 0x00FF00 ; i n t colormapbaseaddress = 0xA ; / / w r i t e ars t o t h e f r a m e u f f e r, w i t h c o l o r v a l u e s 1 t h r u N 1. f o r ( i n t x =1; x<n; x ++) { f o r ( i n t y =0; y <600; y ++) { ( f r a m e B u f f e r A d d r e s s ( x, y ) ) = x ; / / w r i t e x t o p i x e l ( x, y ) / / Animation animate a GREEN v e r t i c a l ar moving a c r o s s t h e s c r e e n / / from x=1 t o x=n 1. f o r ( i n t x =1; x<n; x ++) { i n t o l d a = colormapbaseaddress + 4 ( x 1) ; i n t newa = colormapbaseaddress + 4 x ; o l d a = BLACK; newa = GREEN; s l e e p ( 4 0 ) ; 11