A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25 µm CMOS technology for applications in the LHC environment.

Transcription

1 A Configurable Radiation Tolerant Dual-Ported Static RAM macro, designed in a 0.25 µm CMOS technology for applications in the LHC environment. 8th Workshop on Electronics for LHC Experiments 9-13 Sept. 2002, Colmar, France K. Kloukinas, G. Magazzu, A. Marchioro CERN EP division, 1211 Geneva 23, Switzerland

2 Overview Motive of Work Description of the macro-cell design Experimental Results Conclusions Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 2

3 Motive of Work Several Front-End ASICs for the LHC detectors are using the CERN DSM Design Kit in 0.25 µm commercial CMOS technology. Many ASICs require the use of rather large memories in Readout Pipelines, Readout Buffers and FIFOs. CERN DSM Design Kit lacks design automation tools for generating customized SRAM blocks. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 3

4 Proposed Design Built an SRAM macro-cell that can be configured in terms of word counts and bit organization by means of simple floorplanning procedures. Initially designed for the needs of the Kchip Front-End ASIC used in the CMS ECAL Preshower detector. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 4

5 CERN-SRAM specifications Scalable Design Configurable Bit organization (n x 9-bit). Configurable Memory Size (128 4Kwords). Write Address Synchronous Dual-Port Operation Permits Read/Write operations on the same clock cycle. Typical Operating Frequency: 40 MHz. Low Power Design Full Static Operation. Divided Wordline Decoding. Read Address RD WR CLK Data In SRAM Radiation Tolerant Design Data Out Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 5

6 Memory Cell RBL WBL WBL RBL BL BL R_WL W_WL WL Dual Port SRAM Cell Single Port SRAM Cell To minimize the macro-cell area a Single Port memory cell is used based on a conventional cross-coupled inverter scheme. Gain in Memory Cell Layout Area = 18% Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 6

7 Memory Cell Design BL BL BL GND VDD GND BL M1 M2 WL M3 WL Single Port memory cell Interconnect: 3 metal layers 1 st for local interconnects 2 nd for vertical bitlines and power lines 3 rd for horizontal wordlines Memory Cell Area: µm µm 5.60 µm PC Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 7

8 SRAM Block Diagram Din <m-1..0> WA <n-1..0> RA <n-1..0> Addr. Reg. Addr. Reg. Data Reg. m 7 n-7 Row decoder Word-line Buffers Write Drivers SRAM Array Dual-port functionality is realized with a time sharing access mechanism. Registered Inputs Latched Outputs Clk R W clk Timing Logic Read Logic Column-decoder Data Latch Dout <m-1..0> Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 8

9 SRAM Interface Timing Clk WA WRITE READ READ/WRITE t S t H t S t H RA W R Din Dout t acc Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 9

10 SRAM macro-cell Design Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 10

11 Address Mux Register Leaf cell is based on the D-F/F and the 2-input Mux standard cells found in the CERN DSM Design Kit. WA D SET Q True & Complementary output with balanced timing. RA D CLR SET Q Q Addr AddrZ Easily sizeable by abutting the necessary number of leaf cells. Clk CLR Q Leaf Cell Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 11

12 Row Decoder Decoder: 7 to 128 Hardwire-configured. Pre-routed layout block. A6 WL0 WL1 Dynamic NAND-type. Speed, Area, Power advantages over the static NAND-type. Latched output. precharge A0 WL WL2 WL3 evaluate WL128 A0...A6 A0...A6 Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 12

13 Column Decoder Static NAND-type implementation Column decoding is one of the last actions to be performed in the read sequence. It can be executed in parallel with other functions, and can be performed as soon as address is available. Its propagation delay does not add to the overall memory access time. Size Configurable Make use of Design kit standard cells. Decoding function is via-hole programmable. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 13

14 Divided Wordline Decoding Global Word-line Local Word-line Local Word-line Block Select Block Select Reduced Power Consumption. The non accessed portions of the memory remain in the precharge state. Improved Wordline Selection Time. Since the RC delay in each divided wordline is small due to its short length. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 14

15 Divided Wordline Decoding Data In Write Drivers Write Drivers Write Drivers Write Drivers Global Word-line Local Word-line SRAM Array Word-line Buffers SRAM Array Word-line Buffers Row Decoder Word-line Buffers SRAM Array Word-line Buffers SRAM Array Address Read Logic Read Logic Read Logic Read Logic Data Out Column Dec. Column Dec. Column Dec. Column Dec. Block Pre-Dec. Block Select signals Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 15

16 SRAM macro-cell Design Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 16

17 Data Input Output Ports Data Input Register Leaf cell is based on the D-F/F standard cell from CERN DSM Design Kit. True & Complementary output with balanced timing. Data Output Latch Leaf cell is based on the Latch standard cell from CERN DSM Design Kit. Easily sizeable by abutting the necessary number of leaf cells. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 17

18 SRAM Data Path Data in Clk Write enable Bit Line Write Drivers Bit Line precharge BLPC evaluate precharge Word Line evaluate Read Logic Latch Data out Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 18

19 Read Logic Substitution of the conventional sense amplifier with an asymmetric inverter. Reduced Power Consumption Stable operation al low power supply voltages. Acceptable performance for target applications. Easy to design. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 19

20 Replica Techniques Scalability Wordline select time depends on the size of the memory. Dummy Wordline with replica memory cells to track the wordline charge-discharge time. Bitline Timing Dummy Bitlines to mimic the delay of the bitline path over all conditions. 128 rows Dummy Word Line SRAM Array Dummy Bit Lines WLdummy BL0 Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 20

21 Replica Techniques Row Decoder A6 Data in WEN BLPC Bit Line Bit Line Dummy Bit Lines A0 WLPC Global Word Line Local Word Line WLPC WLdummy Block Select LWLdummy Dummy Word Line BL BL BL0 Latch Data out Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 21

22 Timing Logic Data Input Register Clk Address Mux Register Clk SRAM Interface Memory Cell Array Clk R W WLdummy BL0 Timing Logic WLpc BLpc REN WEN Latch Memory Cell Array Data Ouput Latch Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 22

23 Timing Logic Asynchronous internal timing of control signals. Static operation. Hand-shaking and transition detection to realize internal timing loops. Timing loops are initiated by the system clock and terminated upon completion of the operation. All control signals are forced back to their initial state to prepare for subsequent tasks. During standby periods, bitlines and wordlines precharge-evaluate cycles are not initiated, thus keeping the Power Consumption to a minimum. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 23

24 Operation and Timing Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 24

25 Cell Library Size Configurable Fixed Layout Data Input Register Address Mux Register WordLine Buffers SRAM column, 128 x 9bits (50.4 µm x µm) Column Decoder Block Pre-Decoder Output Data Latche Row Decoder Timing logic Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 25

26 Floorplanning Write drv. Read logic Write drv. Read logic Write drv. Read logic Write drv. Read logic Row Decoder (128 rows) Write drv. Block Column Read logic Column Decoder Write drv. Read logic Write drv. Read logic Write drv. Read logic PreDecoder DIn Reg DOut Latch Timing Address Reg vdd gnd DIn WA RA CLK W R DOut Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 26

27 CAD Tools Support Digital Simulation SRAM verilog module (parameterized) Digital Simulator VERILOG Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 27

28 CAD Tools Support Logic Synthesis Template SRAM timing Design Kit.lib file Combined.lib file compilation Combined.db file Logic Synthesis Tool SYNOPSYS Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 28

29 CAD Tools Support Place & Route Template SRAM timing Design Kit TLF file Combined TLF file compilation Combined CTLF file Layout view Abstract view LEF file Place & Route Tool Silicon Ensemble Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 29

30 Experimental Results To prove the concept of the SRAM macro-cell scalability and to evaluate the performance of the proposed design we have fabricated two test chips: a 1Kwords X 9bits and a 4Kwords X 9bits. Both chips were tested and found functional. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 30

31 Submitted SRAM Chips 1 st Prototype Design: CERN_SRAM_1K Configuration: 1K x 9 bit Size: ~560µm x 1,300µm Area: ~0.73mm2 Density: ~12.6Kbit/mm 2 The Memory consists of 2 Blocks of 512 x 9bits. Each Block is composed by 4 Columns of 128 X 9bits. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 31

32 Submitted SRAM Chips 2 nd Prototype Design: CERN_SRAM_4K Configuration: 4K x 9 bit Size: ~1,850µm x 1,300µm Area: ~2.4mm2 Density: ~15.4Kbit/mm 2 The Memory consists of 8 Blocks of 512 x 9bits. Each Block is composed by 4 Columns of 128 X 9bits. Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 32

33 CERN SRAM test results Functional tests Max operating frequency: Simultaneous Read/Write operations: 2.5V Read access time: 2.5V Power dissipation: 15µW / 2.5V for simultaneous Read/Write operations on the same clock cycle 40MHz). Tests for process variations: Test chip: 4Kx9bit Differences in the access time < 1ns for: -3σ, 1.5σ, typ, +1.5σ, +3σ Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 33

34 Performance Tests Test Chip: 4Kword X 9bits Operation Frequency: 50MHz Power Supply: 2.5Volts Read Access Time: 7.5nsec Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 34

35 Performance Tests Test Chip: 4Kword X 9bits Power Supply: Volts Operation Frequency: 50MHz Test Patterns: All 1 s and all 0 s Checkerboard Marching 1 s Marching 0 s Power Supply Voltage (V) Schmoo Plot Pass Access Time (nsec) Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 35

36 Power dissipation CERN SRAM 4K Power dissipation of macro-cell Test chip: 4Kwords x 9bits Power Dissipation (uw) Standby Idle Read Write Read/Write Power Operation (µw/mhz) Standby 0.10 Idle 1.90 Read 7.40 Write Read/Write Clock frequency (MHz) Operation Standby Idle Read Write Read/Write Test Conditions Description No operation, addr. & data static. No operation, addr. & data changing in every clk cycle checkerboard data pattern checkerboard data pattern checkerboard data pattern Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 36

37 Irradiation Tests Ionizing Total Dose Conditions Source: X-rays. Step Irradiation: 1Mrad, 5Mrad, 10Mrad. Constant dose rate: 21.2 Krad/min. Annealing: ~25 o C. Under bias, in Standby mode during irradiation & annealing. Results No increase in power dissipation. No measurable degradation in performance. Single Event Upset: Under preparation Test chip: 4Kwords x 9bit Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 37

38 CERN SRAM popularity! ATLAS MCC chip Memory configuration: 128 x 27bit Detector: ATLAS PIXEL Lab: INFN Genova ALICE AMBRA chip Memory configuration: 16K X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Torino ALICE CARLOS chip Memory configuration: 256 X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Bologna LHCb SYNC chip Memory configuration: 256 X 9 bits Detector: LHCb muon system Lab: INFN Cagliary ATLAS SCAC chip Memory configuration: 128 x 18bit Detector: ATLAS tracker Lab: NEVIS Labs ATLAS DTMROC chip Memory configuration: 128 x 153 bits Detector: ATLAS TRT Lab: CERN CMS Kchip Memory configuration: 2K x 18 bits 128 x 18 bits Detector: CMS Preshower Lab: CERN Chips submitted and tested Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 38

39 Design Support Delivery of SRAM design library Half a day design CERN Designer configures his macrocell Review the macrocell design Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 39

40 Conclusions Design Status Design meets target specifications. Macrocell has been successfully used in a number of ASIC designs. Future Plans No further development is foreseen. Design Support Contact Person: Kostas.Kloukinas@CERN.ch Information on the Web Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 40

41 Floorplanning DIn Reg Write drv. Block DIn WA RA Timing Column CLK W R WA Row Decoder (128 rows) Address Reg Read logic vdd gnd DOut WorldLine Buffers & Block Decoders Column Decoder. DOut Latch Timing PreDecoder Address Reg DIn Reg Write drv. Write drv. Block DIn RA Column CLK W R Read logic Read logic vdd gnd DOut DOut Latch Row Decoder (128 rows) Sept 12, 2002 KLOUKINAS Kostas EP/CME-PS 41