Graduate Institute of Electronics Engineering, NTU. FPGA Lab. Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB

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1 FPGA Lab Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB

2 Objective In this Lab, you will learn the basic set-up and design methods of implementing your design by ISE Create a New Project Add HDL Source & Check Syntax Create Timing / IO Constraint Implement Design and Verify Constraints Download Design to the FPGA Board P2

3 A 26-bit counter Reference Design Can be used as frequency divider clk (33MHz) rst Counter (Frequency divider) out1 (count[25]) ~1Hz out2 (count[24]) ~0.5Hz P3

4 Verilog Code (counter.v) Reference Design module counter (clk, rst, out, out2); input clk; input rst; output out; output out2; reg [25:0] count; wire out, out2; assign out = count[25]; assign out2 = count[24]; always@(posedge clk or posedge rst) begin if(rst) count <= 26'd0; else count <= count + 26'd1; end endmodule P4

5 Starting the ISE Software Start->All Programs->Xilinx ISE 10.1->Project Navigator P5

6 Create a New Project Select File->New Project P6

7 Create a New Project 1.Enter Project Name 2.Verify that HDL is selected from the Top-level Source Type list 3. P7

8 Create a New Project Fill in the properties in the table Product Category: ALL Family : Virtex 5 Device: XC5VLX110T Package:FF1136 Speed:-3 Source Type: HDL Synthesis Tool: XST Simulator: Modelsim SE Verilog Prefered Language : Verilog P8

9 Project->Add Source Add counter.v to project Add HDL Source P9

10 Add HDL Source 1.Double click on source file 2.You can edit your source file P10

11 Syntax Check You ll get a green check if your code has no errors Double Click on Check Syntax P11

12 Create Timing / IO Constraint Create Timing Constraint Double Click on Create Timing Constraint P12

13 Create Timing / IO Constraint Click on Yes to create UCF file P13

14 Create Timing / IO Constraint 2. Save UCF file 1. Set Clock period: 30ns 3. Close Timing Constraint setting (right click -> close) P14

15 Create Timing / IO Constraint You can also edit UCF file manually Content of counter.ucf NET "clk" TNM_NET = clk; TIMESPEC TS_clk = PERIOD "clk" 30 ns HIGH 50%; use Add source to add ucf file to your project P15

16 Create Timing / IO Constraint I/O Constraint (Pin Assignment) Double Click on Floorplan IO P16

17 Create Timing / IO Constraint Pin assignment 2..Save 1.Enter pin location For different IO setting, see reference[2] P17

18 Implement Design and Verify Constraints Implement the design and verify that it meets the timing constraints specified in the previous section Right Click -> RUN P18

19 Implement Design and Verify Constraints Design Summary P19

20 Download Design to the FPGA Board 1.Connect the 5V DC power cable to the power input on the FPGA board 2.Connect the download cable between the PC and FPGA board 3.PC will configurate FPGA driver automatically 5V DC power cable connector Switch FPGA download cable connector P20

21 Download Design to the FPGA Board Generate Programming File Right Click -> RUN P21

22 Download Design to the FPGA Board Right click on Configure Target Device ->RUN P22

23 Download Design to the FPGA Board Make sure your FPGA board is connected to the PC, then click finish P23

24 Download Design to the FPGA Board Click on Bypass for the first four targets, and select counter.bit for the last one (xc5vfx110t) P24

25 Download Design to the FPGA Board P25

26 Download Design to the FPGA Board Right click on target device xc5vfx110t ->Program P26

27 Download Design to the FPGA Board P27

28 Download Design to the FPGA Board If it shows Program Succeeded, your design has been download to the FPGA board correctly. Check FPGA to see whether your design works or not. P28

29 Check point Counter(Frquency Divider) on FPGA out0 /out1 GPIO LED0/GPIO LED1 Rst GPIO Switch1 P29

30 Reference [1] ISE quick start [2] XUPV5-LX110T User Manual P30

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