Learning Outcomes. Input / Output. Introduction PICOBLAZE 10/18/2017

Transcription

1 3-. Learning Outcomes 3-.2 Hardware/Software Interfacing PICOBLAZE Slides from Mark Redekopp, EE29 slide set (EE29Spiral3.pdf) adopted to suit EE354L I understand the PicoBlaze bus interface signals: PORT_ID[7:], IN_PORT[7:], OUT_PORT[7:], READ_STROBE, and WRITE_STROBE I understand how a memory map provides the agreement between addresses the software will use and that the hardware must recognize and respond to I understand how to build address decoding logic to ensure only the appropriate item/register is selected for a given PORTID For output, I can take a memory map and the PORTID and OUT_DATA bits such that the appropriate data is input or saved in a register when an OUTPUT instruction is executed For input, I can take a memory map and the appropriate PORTID bits to build logic and muxes such that the appropriate data value is present at IN_DATA when an INPUT instruction is executed Input / Output The processor connects to peripherals and other logic via the bus (address, data, and control) Software running on the processor performs loads and stores that read and write data to and from these devices based on address Processor Memory FE may signify a white dot at a particular location Video Interface A D C 254 WRITE 399 Keyboard Interface 4 4 hex 3-.3 Introduction Picoblaze (aka KCPSM6) is an 8 bit soft core processor The processor is not implemented directly in hardware on the FPGA (not a hard core) but instead it is just a Verilog description that is then synthesized along with the rest of your hardware design It provides a bus interface that can be connected to custom logic that you design and then used to control that custom logic via software executing on the processor 3-.4

2 Taken from the KCPSM6 Manual Input / Output Operations 3-.7 Exercise 3-.8 Make the register below capture data (out_data) from your Picoblaze whenever it outputs address FF hex on (address or port_id) INDATA Picoblaze Processor (software controlled) OUTDATA ADDR WS (W) D[7:] Q[7:] Reg RST 2

3 Remember: Registers w/ Enables 3-.9 Registers w/ Enables 3-. Registers (D FF s) will sample the D bit every clock edge and pass it to Q Sometimes we may want to hold the value of Q and ignore D even at a clock edge We can add an enable input and some logic in front of the D FF to accomplish this /AR D i Q i * X X X, X X Q i X Q i D /AR Y S SET D Q CLR FF with Data Enable Q The register content will change consequent to the clock edge only if the enable is active Otherwise the current Q value is maintained /AR D[3:] Q[3:] Recall Memory Interfaces We provide address and data = Overall enable (unless it is ) the memory won't read or write (we assume =) W = Write enable = Write / = read A[2:] DI[3:] W A[2:] DI[3:] W twrite M[3] Register Array DO[3:] 3-. DO[3:]??? mem[3] = mem[6] = Common asynchronous memory pinout No clock input Active low (Chip Select) Active low WE (Write Enable) Active low RD (Read Enable) commonly called (Output Enable) If they are chips, they usually have bidirectional data pins If they are inside an FPGA or an ASIC, they usually have separate data input pins and separate data output pins and perhaps active high control inputs Assume = tacc 3

4 Common asynchronous memory pinout Exercise Memory chips with bidirectional data pins and low-active control inputs KB RAM (RWM) A[9:] D[7:] WE KB ROM A[9:] D[7:] Make the register below capture data (out_data) from your Picoblaze whenever it outputs address FF hex on (address or port_id) Memory blocks in an ASIC or FPGA with unidirectional data pins and high-active control inputs KB RAM (RWM) A[9:] DI[3:] DO[7:] WE KB ROM A[9:] DO[7:] Write Strobe shall be included <= Very Important Exercise 2 Use your PicoBlaze to receive input from A given address hex and B for address x hex Since INDATA pins are dedicated input data lines, there is no harm in ignoring the READ STROBE A memory map shows what devices are assigned to a given address or address range that can then be accessed by the processor (and its software programs) Dec A7 A6 A5 A4 A3 A2 A A Assigned Device Input Switches (unused) 2 (unused) 253 LEDs 254 (unused) SegDisplay 4

5 Given an 8 bit address space (256 locations) and 3 devices that we want to interface to our microprocessor, we first must create the memory map A 64 bytes (64x8) memory A single 8 bit register A single bit D FF 3-.7 Exercise: What is a minimal set of bits that could be used to distinguish each device from the others? A 64 bytes (64x8) memory => A7 A6 =, A single 8 bit register => A7 A6 =, A single bit D FF => A7 = 3-.8 Dec A7 A6 A5 A4 A3 A2 A A Assigned Device 64x8 Memory bit Register 28 bit D FF Dec A7 A6 A5 A4 A3 A2 A A Assigned Device 64x8 Memory bit Register 28 bit D FF Memory Aliasing Given A 64 bytes (64x8) memory => A7 A6 =, A single 8 bit register => A7 A6 =, A single bit D FF => A7 = By using don't care situations the 8 bit register will respond to any address where A7 A6 =, (i.e ) and similarly the bit D FF will respond to any address where A7= (i.e ) Dec A7 A6 A5 A4 A3 A2 A A Assigned Device 64x8 Memory bit Register Note 28 bit D FF Note 3-.9 Address Decoding Address decoding refers to the process of enabling the correct device based on a specific address combination Address Decoding Logic

6 Exercise: Repeat the exercise to find a minimal set of bits that could be used to distinguish each device from the others? A 64 bytes (64x8) memory => A6 + A6'(A5+A4+A3+A2+A) A single 8 bit register => A6'A5'A4'A3'A2'A'A' A single bit D FF => A6'A5'A4'A3'A2'A'A Dec A7 A6 A5 A4 A3 A2 A A Assigned Device 8 bit Register bit D FF 2 64x8 3 Memory Address Decoding Exercise S S 8 Picoblaze Processor (software controlled) WS (W) x8 8 Memory 8 DI[7:] DO[7:] 6 A[5:] W 8-bit REG 8 8 D[7:] Q[7:] RST SET D Q -bit DFF CLR High Order Interleaving General strategy is to place devices at ranges of address divide by moresignificant bits Output Instruction Dec A7 A6 A5 A4 A3 A2 A A Assigned Device 64x8 Memory bit Register bit D FF Example: output s, FF Outputs the 8 bit number in s as data on out_port to the address (port_id) of xff 6

7 Input Instruction Example: input s8, c Places the address xc on the port_id and then grabs data from the in_port at the end of the second cycle and writes it into register s8 7