ECE 156B Fault Model and Fault Simulation

Transcription

1 ECE 156B Fault Model and Fault Simulation Lecture 6 ECE 156B 1

2 What is a fault A fault is a hypothesis of what may go wrong in the manufacturing process In fact, a fault model is not trying to model the mechanism of a manufacturing defect Instead, it is a model for us to go after So that 99% fault coverage gives us confidence that we have covered most of the defects A fault model is a guidance It facilitates test generation Practical fault models are mostly defined at the gate level Simulation at transistor level is just too costly ECE 156B 2

3 The single stuck-at fault model Stuck-at 0 Every signal line (including input and output) of a design can either stuck-at 0 or stuck-at 1 A fault is defined as signal line x stuck-at a So n lines have 2n stuck-at faults ECE 156B 3

4 How many SA faults to consider? Although we have 2n faults, many of them are either covered by others or equivalent to other faults So, we use the following two concepts to reduce the number of faults to consider Fault Equivalence The condition to set a test for fault x is the same for fault y Then, we say x and y are equivalent Fault Dominance The condition to set a test for fault x guarantees that fault y can always be detected Then, we say y is dominated (covered) by x In this case, we just need to consider x ECE 156B 4

5 How to test a fault a b Stuck-at 0 c To set the condition for testing b stuck-at 0, you will need to set a=1 b=1 If b-sa-0 does occur, you will see c=0 If b-sa-0 does not occur, you will see c=1 So you know, a test must be able to differentiate between the good circuit from the faulty circuit ECE 156B 5

6 a test In general a b Stuck-at 0 c Can a difference be observed? 1 A test is applied If b-sa-0 does occur, you will observe a at one of the outputs If b-sa-0 does not occur, you will observe not(a) at that particular output So you have a way to tell if b-sa-0 occurs or not by applying the test You need to simulate a given test to see if it can actually detect a given stuck-at fault (can any difference be produced at an output?) ECE 156B 6

7 Think of a fault as a set of tests f1 f2 Tests detect both Total test space is 2^n ECE 156B 7

8 Equivalence and Dominance f1,f2 f2 f1 Tests to detect f1 is the same as tests to detect f2 (equivalence) Detecting f1 guarantees detecting f2 ECE 156B 8

9 a b An Example How many faults? (a-sa-0, a-sa-1, b-sa-0, b-sa-1, c- sa-0, c-sa-1) Total 6 faults a-sa-1 dominates c-sa-1 b-sa-1 dominates c-sa-1 c-sa-0 is equivalent to a-sa-0 c-sa-0 is equivalent to b-sa-0 a-sa-0 is equivalent to b-sa-0 So you need only consider 3 faults a-sa-1, b-sa-1, a-sa-0 or b-sa-0 or c-sa-0 c ECE 156B 9

10 Re-convergent fanout f g d h d stuck-at fault is not the same as e stuck-at To detect d stuck-at, you need to set g=1 To detect e stuck-at, you need to set h=1 f stuck-at fault is not the same as d s and e s f stuck-at can be detected by either setting g=1 or setting h=1 or both Detecting f stuck-at does not guarantee detecting either d s stuck-at or e s stuck-at However, detecting either d s stuck-at or e s stuck-at guarantees detecing f s stuck-at So, e s stuck-at dominates f s stuck-at; so does d s stuck-at e ECE 156B 10

11 Other Fault Model f g d h e One line is short with another line Define it is an OR bridge or an AND bridge Given n lines, consider nc 2 (*2) bridging faults People often use layout tool to extract coupling capacitance between wires and then decide if the pair should be included or not ECE 156B 11

12 Other Fault Model f g d h e h is supposed to transition from 0 to 1, and is stuck-at 0 without making the transition This is called a rising transition fault You can look at it as transition with a stuck-at We need a pair of vectors to detect this fault First, set h to 0 Second, provide a vector to detect h stuck-at 0 ECE 156B 12

13 Prior Study If you can provide a high fault coverage for stuck-at faults, you will have a high fault coverage for bridging faults Hence, there is no need to explicitly prepare tests for bridging faults If you can provide a good fault coverage for stuck-at faults, you will have a good fault coverage for transition faults But may not be enough Transition faults have to be tested with a fixed clock frequency Transition fault coverage is treated as a separate quality measurement but not bridging fault coverage Industrial delay testing is based on transition faults ECE 156B 13

14 Fault Simulation C A a 0 1 c 1/0 Z1 B 1 Z2 b 1 c s-a-0 ABC=111, a test 1/0 is denoted as D, (0/1 is noted as D-bar) ECE 156B 14

15 Fault Simulation In general, the complexity of fault simulation is n times higher than logic simulation If you have n faults in the fault set It is an extremely time consuming process Hence, you can only do it at gate level Rarely this is done at transistor level Fault simulation can be combinational or sequential Unlike ATPG, the complexity of these two are not that different For verification, fault simulation is generally not used because of the high complexity They want something at RTL, rather than gate-level ECE 156B 15

16 Parallel Fault Simulation 2-bit to simulate 1 fault So, you can use 00, 01, 10, 11 to denote 0, D- bar, D, and 1 Each fault is simulated independently In one run, you can simulate 16 faults To see if the vector detect them ECE 156B 16

17 Fault Coverage Fault Coverage = (total faults detected)/(total number of faults) The total number of faults usually discounts the equivalent and dominated faults FC 100% A typical FC curve tests ECE 156B 17

18 Better FC 100% better worse unfinished A typical FC curve tests Shorter test length and higher fault coverage is better But you want to make sure that the tests are running out of steam (getting flat curve) ECE 156B 18

19 General Use of Fault Simulation Generate initial test set T Fault simulate T Produce more tests Enough fault coverage? n y done You set a fault coverage goal, and Either you achieve it Or you run out of resources ECE 156B 19

20 FlexTest Mentor Graphics has a sequential ATPG tool called FlexTest Inside FlexTest, there is a sequential stuck-at fault simulation Once you have the Verilog gate-level model and the input/output test patterns for a particular block You can run this block with FlexTest If you are interested, ask your TAs ECE 156B 20