LCD H C 1 2 GP2D PP4 MISO MOSI DIN DOUT SCK PP5 SCK D0 D1 D2 D3 D4 D5 D6 D7 DIN. Maximum SCK = 500 khz SCK D0 D1 D2 D3 D4 D5 D6 D7 DOUT

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Donna Barker
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1 38 xam 3 May 6, 999 Name: You may use one page of notes and any of the Motorola data books. Show all work. Partial credit will be given. No credit will be given if an answer appears with no supporting work. For all the problems in this exam, assume you are using an with a 6 Mz crystal, resulting in a 8 Mz processor clock. Also assume that hc.h has been included, so you can refer any register in the by name rather than by address.. Signals from six sensors are connected to bits through 7 of Port AD of a 68. The A/D reference voltages are V R =5VandV RL =V.You want to set up the A/D converter to convert all of these channels, then stop. (a) owdoyou set up the A/D converter to do this? I.e., what values do you write to which registers? i. nable A/D ( -> ADPU in ATDTL) ii. Select 8-bit mode ( -> S8M in ATDTL5) iii. Select multiple channels ( -> MULT in ATDTL5) iv. Select single conversion sequence ( -> SAN in ATDTL5) v. Always need D = ( -> D in ATDTL5) vi. Select clock rate (x -> ATDTL for fastest convert rate) (b) Write some code which will do the conversions as described above. ATDTL = x8; ATDTL = x; ATDTL5 = x5; (c) ow can you tell when the sequence of conversions is done? ffl SF bit of ATDSTAT register is set to (d) After the conversion is done, the A/D result registers have the following values: ADR ADR ADR ADR3 ADR ADR5 ADR6 ADR7 5 F7 6A A What is voltage on bit 6 of Port A/D? ffl ADR6 = x7 = 3; V = ADR 55 (V R V RL )+V RL = 3 5V =:V 55

2 . A 68 is being used to communicate with two devices over the SPI. The devices are connected as shown below: LD PP MISO MOSI DIN GPD DOUT PP5 ach byte you write to the LD chip is displayed on an LD display. The following shows how to write to the LD chip over the SPI: DIN D D D D3 D D5 D6 D7 Maximum = 5 kz The GPD device is a distance sensor. When the reads from the GPD chip, the GPD sends it abyte which tells it how far it is from an object (such asawall). The GPD sends a x when it is almost touching the object. It sends a xff when it is feet (or more) from the object. The following shows how to read from the GPD chip over the SPI: DOUT D D D D3 D D5 D6 D7 Maximum = 5 kz (a) ow doyou set up the to communicate with the LD and the GPD? xplain what values you need to write to which registers. ffl nable SPI ( -> SP in SPR) ffl Put SPI into master mode ( -> MSTR in SPR) ffl Set clock phase and polarity need POL = (clock idle high) and PA = (data valid on first edge) in SPR ffl Data on both devices comes LSB first ( -> LSBF in SPR) ffl Select normal mode ( -> SP in SPR) ffl Select clock speed. One device works at 5 kz, the other at 5 kz, so set speed to 5 kz to be compatible with both (x -> SPBR) ffl Make and MOSI outputs (can make an output also) x or x6 -> DDRS ffl Make slave select lines PP and PP5 outputs ( -> DDP and DDP5 in DDRP) ffl Deselect slaves by making PP high and PP5 low ( -> PP and -> PP5 in PORTP)

3 (b) Write some code to set up the to communicate with the LD chip and the GPD chip. DDRS = DDRS x; /* or DDRS = DDRS x6; */ DDRP = DDRP x3; PORTP = (PORTP x) & ~x; /* Deselect slaves */ SPR = x59; /* or SPR = x5b; */ SPR = x; /* Normal mode */ SPBR = x; /* 5 kz clock */ (c) Write some code to read the distance from the GPD. Make sure the LD chip is deselected while you are doing this. char distance; /* Variable to save distance value */ PORTP = PORTP x; /* Select GPD */ SPDR = x; /* Write anything to SPDR to make go */ while ((SPSR & x8)!= x8) ; /* Wait for transfer to finish */ PORTP = PORTP & ~x; /* Deelect GPD */ distance = SPDR; /* Read data from GPD */ (d) xplain how the SPIF (SPI Flag) is set. Also, explain how to clear this flag. ffl SPIF flag is set after 8 cycles in master mode, must write data to SPDR to make go; in slave mode, SPIF set after master has clocked all eight bits into slave. ffl Read SPSR (with SPIF set), then access (read from or write to) SPDR. 3. An is connected to a peripheral chip as shown: R/W PA7-7 A 3 7 A A A3 A A5 A A A 3 Y7 Y6 Y5 Y Y3 Y Y Y 7A38 S U P R I P tdsw t DW t DSW = 6 ns min (Data Setup Write) S t = ns min (Data old Write) DW WRIT S RAD = 6 ns max t DR = ns min (Data Access Read) (Data old Read) t DR (a) xplain the purpose of the 7A37 chip. ffl Port A acts as a multiplexed address and data bus. While is low, the puts address lines A5-A8 on Port A. While is high, Port A acts as D5-D8 when writing, the puts the data to write on Port A, the peripheral chip should latch the data on the falling edge of ; when reading, the peripheral chip puts the data to read on Port A, and the reads it on the falling edge of. 3

4 ffl The 7A37 chip acts as an address demultiplexer it latches the address lines A5-A8 on the rising edge of so the address will be available while is high (b) xplain the purpose of the 7A38 chip. ffl The 7A38 decodes the address,, and R/W to select the appropriate chip when (on the 38) =, and = 3 =, one of the outputs of the 38 will go low. Which output goes low depends on A, A and A of the 38. Thus, the 38 acts as a partial address decoder to select the chip the wants to talk to, and to select that chip only when is high. (c) For what range of addresses will the Super hip be selected? ffl From the diagram, you must have A5 high, A low and A3 low to select the 38. You must have A low, A high and R/W high to select Y3. The address range is xxx xxxx xxxx = x88 to x8fff (d) Is the Super hip an input or output chip? ow can you tell? ffl Since R/W must be high, the chip is select for reads only, and hence is an input chip (remember, input and output are always from the point of view of the ) (e) If the Super hip is an input chip write some code which will read a byte of data from the chip and store it in a variable called data. If the Super hip is an output chip write some code which will write a xa5 to it. ffl The is an input chip, so you need to read a byte from address x88 - x8fff (even addresses only, since even addresses are accessed on Port A, odd addresses on Port B). You need to do this with a pointer in : or char data; data = *(char *)x88; #define SUPR_IP (*(char *)x88) char data; or data = SUPR_IP; char data, *ptr; ptr = (char *)x88; data = *ptr; (f) On the above figure two timing diagrams are shown. Only one of them applies to the Super hip the upper one if the Super hip is an output device; the lower one if the Super hip is an input device. onsider the relevant diagram from your answer to the previous part. Based on the timing diagram is the Super hip compatible with the? xplain in detail draw a timing diagram which shows how the chip select is generated from the bus signals, and explain why the chip is or is not compatible based on the times in the figure above. Assume the propagation delays for the 7A37 and 7A38 chips are ns.

5 8ns 3ns ~ns ns S = 6 ns max (Data Access Read) RAD t DR = ns min (Data old Read) t DR (Data Setup Writ ffl After goes high it takes one delay for address to get through 37, and one more delay for 38 to select chip, so after goes high, it takes delays (about ns) before S goes low. From going high until Superhip puts data on bus is delays +, or ns + 6ns or 8ns. needs data on bus 3ns after goes high (circled time 3 on timing diagram). The Superhip cannot get its data on bus fast enough, so Superhip will not work. If you add one -clock stretch, circled time 3 goes to 3ns + t cyc = 3ns + 5ns = 55ns. Now the Superhip will work. ffl After goes low, it takes one delay for 38 to become deselected, so S goes high ns after goeslow. Superhip holds data on bus for t DR after S goes high, so data will stay on bus for ns + ns = 3ns after goes low. needs data to stay on bus for circled time, or ns, after goes low (i.e., Superhip cannot remove data before goes low). Since Superhip holds data for 3ns after goes low, Superhip will work with based on this time.. The following problem deals with interrupts. (a) ow doyou set up the IRQ interrupt to respond to a falling edge, and enable the IRQ interrupt? I.e., what values to you write to which registers? ffl To respond to interrupts on the falling edge, -> IRQ of INTR ffl To enable specific interrupt, -> IRQN of INTR ffl To enable maskable interrupts in general, clear I bit of R INTR = x; enable(); (b) xplain the differences between the IRQ interrupt and the XIRQ interrupt. ffl IRQ has a specific mask (IRQN bit of INTR), XIRQ doesnot ffl IRQ can respond to an edge or a level (IRQ bit of INTR); XIRQ responds only to a level ffl XIRQ is enable by X bit of R; IRQ is enabled by I bit of R (as well as IRQN bit of INTR) ffl Once X bit of R is cleared, it cannot be set again i.e., once XIRQ is enable, you cannot disable it. Once I bit of R is cleared to enable maskable interrupts, it can be set back to to disable maskable interrupts. ffl XIRQ has a higher priority than IRQ if the receives IRQ and XIRQ at the same time, it will respond to the XIRQ interrupt first. 5

spi 1 Fri Oct 13 13:04:

spi 1 Fri Oct 13 13:04: spi 1 Fri Oct 1 1:: 1.1 Introduction SECTION SERIAL PERIPHERAL INTERFACE (SPI) The SPI module allows full-duplex, synchronous, serial communication with peripheral devices.. Features Features of the SPI