Generalized Buffering of PTL Logic Stages using Boolean Division and Don t Cares

Transcription

1 Generalize Buffering of PTL Logi Stages using Boolean Division an Don t Cares Rajesh Garg Sunil P Khatri Department of ECE, Texas A&M University, College Station, TX Abstrat Pass Transistor Logi (PTL) is a well known approah for implementing igital iruits. In orer to hanle larger esigns, an also to ensure that the total number of series evies in the resulting iruit is boune, partitione Reue Orere Binary Deision Diagrams (ROBDDs) an be use to generate the PTL iruit. The output signals of eah partitione blok typially nees to be buffere. In this paper, we present a methoology to perform generalize buffering of the outputs of PTL bloks using Boolean ivision an ompatible observability on t ares (CODCs). By performing the Boolean ivision of eah PTL blok using ifferent gates in a library, we selet the gate that results in the largest reution in the epth of the PTL blok. The use of CODCs further simplifies the logi of the PTL blok. The gates serve the funtion of buffering the outputs of the PTL bloks, while also reuing the epth an elay of the PTL blok. Sine the CODC omputation is memory intensive an time onsuming, CODCs an not be ompute for large iruits. To avert this problem we also use approximate CODCs (ACODCs) whih an be ompute for arbitrary size iruit. Over a number of examples, we emonstrate that our approah (generalize buffering with ACODCs) results in a 29% reution in iruit elay an 27% reution in number of MUXes require, with an improvement of 5% in iruit area, ompare to a traitional buffere PTL implementation of the iruit. Our approah also resulte in a elay reution of 5% an an area reution of 2% over generalize buffering without on t ares. I. INTRODUCTION Pass Transistor Logi (PTL) is a iruit implementation style that has typially been use for many speifi iruit implementations, like barrel shifters. Although PTL offers great benefits for suh esigns, there has been no wiely aepte PTL esign methoology that oul be use to make PTL more broaly aeptable. There have however been several efforts at the researh level, to explore the promise of PTL. Synthesis approahes for PTL strutures typially leverage the fat that there is a iret mapping between the ROBDD [1], [2] an the PTL implementation of a iruit. In fat, eah ROBDD noe an be mappe to a MUX (whih an be implemente using NMOS or CMOS evies). Figure 1 illustrates the mapping between an ROBDD an PTL struture. In Figure 1 the soli line (ashe line) represents the positive (negative) ofator of an ROBDD noe with respet to the variable of that noe. For the PTL implementation of the ROBDD of any funtion, there is an isomorphism between the onnetivity of the ROBDD noes an the MUXes in the PTL implementation. This elegant an easy mapping between ROBDDs an PTL strutures is not without attenant problems, however. b f a 1 0 Fig. 1. b a V DD f b GND ROBDD an its PTL Implementation For one, in a bulk MOS implementation of any iruit, it is not pratial to onnet more than 4-5 evies in series, ue to the phenomenon alle boy effet, whih effetively inreases the threshol voltage V T of most of the series-onnete MOSFETs. This results in a slower esign. Boy effet is governe by the equation V T = VT 0 + γ V sb Here V T is the threshol voltage of the evie, VT 0 is the threshol voltage of the evie at zero boy bias, γ is the boy effet oeffiient, an V sb is the soure to bulk voltage of the MOSFET. When several MOSFETs are onnete in series in a PTL iruit, all but one of them is affete by boy effet. For this reason, in pratie, VLSI esigners o not stak more than 4-5 evies in series. This results in a problem for the traitional PTL implementations, whih attempte to buil monolithi ROBDDs. To solve this problem, we nee to buil ROBDDs in a partitione [3] manner, suh that if an intermeiate ROBDD has a epth greater than 4 or 5, a new variable is reate. In iruit terms, a buffer is implemente at the output of the new variable, ensuring that the iruit rive apability is regenerate every few a

2 levels in the final PTL esign. The seon problem is that ROBDDs, if built monolithially, an exhibit unpreitable memory explosion. This prelues the appliability of the PTL methoology for large esigns, as long as the ROBDDs are buil monolithially (sine it is very har to buil monolithi ROBDDs of large funtions). Again, this suggests the use of partitione ROBDDs to averts this problem. In summary, partitione ROBDD onstrution helps takle both the above problems assoiate with PTL synthesis. In suh a partitione PTL esign, the outputs of eah PTL struture is buffere, to regenerate the eletrial rive apability every 4 or 5 levels. This work esribes a new PTL synthesis approah whih performs better than buffere partitione ROBDD base PTL synthesis. In priniple, it still employs partitione ROBDDs, however, the buffering between PTL stages is one using generalize buffers. These oul be arbitrary gates in the ell library. We ahieve this by asting the problem of generalize buffering as an instane of Boolean ivision. Compatible observability on t ares (CODCs) are use along with Boolean ivision. By using more omplex gates for the buffering logi, an by aitionally using CODCs, our metho is able to signifiantly simplify the logi in the PTL struture, resulting in an improvement (about 29% on average) in total iruit elay, whih is ahieve by signifiantly reuing the total number of MUXes. Even after aounting for the inrease area of the generalize buffers, our metho omes out slightly ahea in terms of area (by about 5% on average). The above omparisons are against traitionally buffere partitione ROBDD-base PTL strutures. The on t ares (CODCs) an be ompute using full simplify in SIS [4]. However, this omputation is very memory intensive an time onsuming beause of its use of ROBDDs. As a result, the CODC omputation is typially not feasible for large iruits. The work presente in this paper is appliable for large iruits as well, sine it uses an approximation of CODCs, whih an be ompute effiiently an in a robust manner. In [5], the authors presente a tehnique to ompute approximate ompatible on t ares (ACODCs). These on t ares are an approximation of CODCs. The omputation of the ACODC of any noe n is base on extrating other noes in the transitive fanout/fanin (TFO/TFI) of n, up to a limite epth. The resulting noes inue a sub-network of the original network. The ACODC of n is simply its CODCs ompute for the inue subnetwork. ACODCs an be ompute for arbitrarily large esigns, an the time an memory utilization for the ACODC omputation is muh less (both typially 30X lower) than the orresponing values for a full CODC omputation. At the same time, the literal ount reution obtaine by ACODCs is typially about 80% of that obtaine by full CODCs. Hene, ACODCs are use in this paper, allowing the appliability of the propose approah to inustrial esigns. The remainer of this paper is organize as follows. Setion II isusses some previous work in this area. In Setion III we esribe our metho of generalize buffering of PTL strutures, base on Boolean ivision. In Setion IV we present experimental results omparing our iea with traitional buffere partitione ROBDD-base PTL esigns [6]. We have also ompare our approah with generalize buffering without CODCs [7]. Conlusions an future work are isusse in Setion V. II. PREVIOUS WORK There has been a signifiant amount of work in the area of pass transistor logi synthesis. In aition, there have been several reporte esign variations on the PTL iruit onept. A goo referene soure for publishe work in this area is [8]. The fous of our paper being logi synthesis for PTL esign, we will not isuss iruit-level variations of the PTL approah. Given the generality of our synthesis methoology, it is orthogonal to the iruit issues an ieas that are isusse in the papers referre to in [8]. In [9], Yano et al. present a synthesis tool, whih works with their PTL library of ells, maroells et. The philosophy of Mahiarulo et al. [10] is that while PTL base synthesis is well researhe, layout an bak-en tools for PTL are not foun as reaily. They esribe a layout generator, to help evelop more omplete tools for PTL esign. The approah of Rahakrishnan et al. in [11] is motivate by the nee to evelop high ensity, low power, high performane iruits using PTL. The authors report a synthesis metho, using two approahes a moifie Karnaugh map [12] approah for small iruits, an a Quine- MCluskey [13], [14] base approah for larger esigns. In [15], the authors stuy regenerative pass transistor logi (RPL), a ual rail PTL family. Their interest stems from the ompat area of these iruits. In [16], Hsiao et al. present a layout an logi synthesis approah, with the input being a logi funtion, while the output is a PTL netlist, using MUXes an inverters. After synthesizing the logi, the methoology as inverters, in orer to ensure that the longest series path of MUXes has a boune epth. In this approah, the buffering is simple (using inverters) as oppose to the generalize buffering (using arbitrary library gates) in our work. The work of [6] buils ROBDDs [1], [2] in a partitione manner [3], thereby avoiing the memory blowup that often ours while using ROBDDs. The resulting small ROBDDs are iretly mappe to PTL strutures, resulting in an effiient synthesis methoology. The ownsie of this approah is one again, the absene of generalize buffering. This approah also oes not utilizes the CODCs to simplify the logi of PTL strutures. The authors allue to performing PTL synthesis in a manner that maps some noes to CMOS gates while others are mappe into PTL bloks. However, this leaves the esigner little ontrol of the epth of these setions. In ontrast, our generalize buffering approah guarantees a fixe boun on the epth of the PTL blok, an also ensures just one level of generalize buffers

3 between PTL bloks. Our generalize buffering approah also uses CODCs to simplify the PTL bloks. In [17], an approah using multilevel gates along with PTL an transmission gates is reporte by Neves et al., prouing a regular an ense layout. This approah permits buffer inlusion. It an be viewe as an approah that ombines synthesis an layout in the PTL esign flow, an is as suh orthogonal to our approah. The work of Peron et al. in the paper [18] reports synthesis algorithms for PTL. Minimization is performe by using inomplete transmission gates. The results of synthesis using their tool PAVOS emonstrate goo quality results when ompare with manually tune PTL iruits. The work of Markovi et al. [19] reports on PTL synthesis for Complementary Pass Transistor Logi (CPL), Dual Pass Transistor Logi (DPL) an Dual Voltage Logi (DVL). Finally, the work of Shelar et al. in the paper [20] reports on a novel metho to minimize power in a PTL struture, by transforming the problem into one of ROBDD eomposition an solving it with a maxflow min-ut approah. In [21], a mixe PTL-CMOS approah was presente by Lai et al. The eomposition proess simply extrate unate variables from a sum-of-prouts (SOP) representation of a funtion an reursively ofatore these variables (reating MUXes in the proess) until unate leaves were reahe. Unate leaves were realize using library gates alone. The weakness of this approah is that it starts with a SOP representation, limiting its effetiveness for large esigns. Further, if a funtion is unate, then the entire iruit realization is purely stanar-ell base. Our approah, in ontrast, an hanle arbitrarily large esigns sine it starts with a partitione ROBDD onstrution as the first step. Also, it works equally effetively for unate esigns. Another mixe PTL-CMOS approah was presente by Yamashitas et al. in the paper [22]. In this paper, the iruit struture was a AND gate followe by a MUX. In ontrast to our approah, this sheme i not seletively ivie a library of stanar ells into the PTL struture, thereby not exploiting the flexibility available in the Boolean ivision proess. In [23], the authors present a PTL synthesis algorithm with generalize buffering. They ast the problem of generalize buffering as an instane of Boolean ivision. Their approah yiels a goo reution of total iruit elay over traitional buffering. They also obtaine a small improvement in total iruit area over traitional buffering. However, their approah oes not utilizes the CODCs to simplify the PTL bloks. In our approah, we also perform generalize buffering using Boolean ivision. However, multi-level on t ares (CODCs & ACODCs) are use uring Boolean ivision, to further simplify the PTL struture. The simplifiation of PTL strutures will results in a further reution of total iruit elay an area. III. OUR APPROACH We efine the epth of an ROBDD g as the maximum number of noes in any traversal of g to its terminal noes. Our metho reates partitione PTL strutures with a maximum epth of 5 (this number an be arbitrary, though). This ensures that there are no more than 5 transistors in series, in any PTL blok. In orer to implement generalize buffering, we employ Boolean ivision with CODCs. Algorithm 1 esribes the new PTL synthesis methoology whih uses generalize buffers an CODCs to simplify the PTL bloks. Consier a boolean network η. First the network η is optimize an eompose using 2-input gates an inverters only. This is one to ensure that the PTL struture grows in preitable manner. Let the new network be referre to as η. Now the noes of η is sorte in epth-first manner. The resulting array of noes is sorte in levelization orer, an plae into an array A. In this approah, we first buil ROBDDs of the noes of η, topologially from the inputs to the outputs by fething the noes from the array A in inex orer. Suppose we enounter a new noe n for whih we want to onstrut a ROBDD f. The ROBDD of eah of its fanins must have a support of at most 4 variables (assuming that the fanins are not partitione ROBDD variables). When onstruting the ROBDD f of n, it an initially have at most 8 ROBDD variables (sine any noe in the original network an have at most 2 fanins). In ase no ivision is possible, we an make one of the inputs of n a new variable, yieling an ROBDD of epth at most 5. If the epth of f is less than 5 then we ontinue with reating the ROBDD of the other noes in array A. However, if the epth of f is greater than or equal to 5 then we ompute the CODCs (or ACODCs) of the noe using ompute funtion. Then we attempt to ivie f with the gates in a library by alling the test ivision funtion. The etaile esription of the test ivision funtion is provie after the synthesis flow. If the ivision is suessful, then the epth of the ROBDD f will reue. If the resulting epth of ROBDD is less than or equal to 5 than we mae the noe n a ROBDD variable otherwise we bak-trak. The bak-trak proeure is esribe later. The key iea is that we will take the ROBDD of n, an attempt to ivie it with the gates in a library. If suh a Boolean ivision is possible an it is stritly epth-reuing, we selet it. The test for whether a library gate g, with an assoiate variable G, ivies the ROBDD f of n is esribe next. A pitorial view of the proess is shown in Figure 2. A. Boolean Division with Library Gates Definition 1: g is a Boolean ivisor of f if h an r exist suh that f = gh + r,gh /0. g is sai to be a Boolean fator of f if, in aition, r = /0, i.e., f = gh. In this ase, h is alle the quotient an r is alle the remainer. Note that h an r are not unique. Theorem 3.1: If f g /0, then g is a Boolean ivisor of f.

4 Algorithm 1 Pseuooe for PTL synthesis using generalize buffers an CODCs η = optimize network(η) η = eompose network(η, p) A = fs an levelize noes(η ) N = 0 i = 1 while i size(a) o n = array feth(a,i) f = ntb noe to b(n) if b epth( f ) 5 then = ompute (η,n) for g G Gate Library o f = test ivision( f,,g,g) en for if b epth( f ) > 5 then bak-trak else b reate variable(n) ontinue en if else ontinue en if en while a) Before iviing AND gate Fig. 2. b) After iviing AND gate (note epth reue otherwise the gate is rejete Diviing a Generalize Buffer into a PTL Struture Proof: If f g /0, we an write f = f g + f g f = g( f + x) + f g where x g whih is of the form f = gh + r. However, if f is an Inompletely Speifie Funtion (ISF), with on t are, then f = G( f + + g) + ( f + )g. Therefore, the upper an lower bouns (U an L) for f are: U = G( f + + g) + ( f + )g an L = ( f G + f g) As a onsequene, the test that we perform when we want to try to ivie a gate g (having a variable G) into the ROBDD f is shown in Algorithm 2. Algorithm 2 Pseuooe for Division of f by g G using CODCs test ivision( f,,g,g){ if f g 0 then L = ( f G + f g)(g G) U = ( f G + G + Gg+ f g + g)(g G) Z = b between(l,u) Z = b smooth(z,gvars) R = b ompose(z,g,g) if f R f + an b epth(z ) < b epth( f ) then Q = (g G) = V Q return(suess,z ) en if else return fail en if } In Algorithm 2, the funtions L an U are ANDe with (g G) to express the fat that g an G are not inepenent variables, but rather are relate as G g. Note that as a onsequene of this, the Gg term in line 4 of Algorithm 2 an be remove. We next fin a small ROBDD Z (using the funtion b between(), whih returns the heuristially smallest ROBDD Z suh that L Z L +U), whih is a Boolean ivisor of f. Next, we smooth out 1 the variables of g. If the resulting ROBDD Z, with g ompose bak into G, lies between f an f + an also if the epth of Z is less than the epth of f, we return Z as the quotient. If we have a vali ivision then we map the on t are of the noe n onto a new set of variables V so that it an be use uring the next iteration. The CODCs are mappe using following equations: Q = (g G) = V Q where V is the set of variables whih lie in the support of g but are not present in the support of Z. The re-mappe on t ares of n are use for further Boolean ivision, to explore aitional generalize buffering opportunities for the noe n. B. Bak-trak When we perform ROBDD onstrution, the maximum epth of the ROBDD of a noe n before ivision an be 8, as isusse earlier. Our ivision routines systematially reue this epth to below 5, by using several generalize buffers. If 1 Smoothing is also referre to as Existential Quantifiation. The existential quantifiation of f with respet to a variable x is expresse as x f = f x + f x. Smoothing a set of variables is ahieve by performing existential quantifiation, one variable at a time

5 an ROBDD is not able to be ivie (an the resulting epth after ivision is greater than 5), then we bak-trak, an make one of the fanins of n a new variable. The fanin whih is mae a new variable is the one whose topologial level is one less than that of n. The reason for this is illustrate in Figure 3. Fig. 3. a e Bak-traking uring Division Consier noe a, at topologial level n. Suppose it has two fanins an, with levels n 1 an n 2 respetively. Sine partitione ROBDD onstrution ours in topologial orer from inputs to outputs, it is possible that noe b has alreay been proesse, an ivie. Its ROBDD therefore has a epth less than 5 noes. Now suppose the ROBDD epths of an are 4 eah, an the ROBDD of a has epth 8. Suppose all ivisions for noe a fail. In that ase, we nee to bak-trak an make either or a new variable. This woul guarantee that a has a new epth 5. We selet (with level n 1) as the new variable, sine it is more likely that (whih is at a lower topologial level) has more fanouts at level n or n 1. When is mae a new variable, all its fanouts are heke. If any of them has alreay been proesse (suh fanouts must have level n), then their ROBDDs are re-ompute, an ivision is re-one. In this way, the PTL network is kept as small as possible. If this re-omputation were not performe, then the logi of the noe woul be implemente twie as a PTL struture (one for the noe b an then again for the variable orresponing to noe itself). If, after a bak-trak, the epth of the noe n is less than 5, then we ontinue to grow the orresponing ROBDD further, up to a epth 8. After attempting ivision (regarless of whether the ivision sueee or faile), the epth of n is guarantee to be less than or equal to 5, allowing for an elegant exit in ase ivision fails. In general, however, this ivision strategy yiels a number of goo generalize buffers, so this ourrene is rare. IV. EXPERIMENTAL RESULTS We implemente the new PTL synthesis algorithm with generalize buffering an on t ares in SIS [4]. Our metho reates partitione PTL strutures with a maximum epth of 5 (this number an be arbitrary, though). This ensures that there are no more than 5 transistors in series, in any PTL b blok. The oe onsiste of reaing a iruit (whih was eompose before-han into 2-input gates an inverters), an then builing ROBDDs of its noes in a topologial manner from the inputs to the outputs. When the epth of the ROBDD of any noe grew beyon 5, ivision was invoke, as esribe in the previous setion. The CODCs were ompute an use uring ivision. The CODC omputation was one in two ways: one using f ull simpli f y [4] (whih provies omplete CODCs) an another using approximate CODCs (ACODCs) as mentione in [5]. Results are presente an ompare for both styles of CODCs. The resulting library gates that were utilize for ivision, an the new ROBDDs after ivision were store within eah noe s ata struture. Sine the ROBDDs in question were small (with a maximum initial support of 8), ivision was performe exhaustively. If the resulting epth after ivision was still greater than 5, then a bak-trak step was invoke making one of the noe s fanins a new variable. After this we hek the noes whih are in the fanout of the fanin noe orresponing to the newly reate variable. If any of these fanout noes was alreay proesse, then their ROBDDs were re-ompute, an ivision was re-one. After attempting ivision (regarless of whether the ivision suees or fails), the epth of the final ROBDD is guarantee to be less than or equal to 5, allowing for an elegant exit strategy in ase ivision fails. Our library onsiste of the gates AND2, AND3, AND4, OR2, OR3 an OR4. Sine any ivie gate beomes a new variable, it is require in both its polarities. Therefore, by DeMorgan s law, we only nee non-inverting gates in our library. The MUX an all gates in the library were haraterize for elay in SPICE [24], using a 100nm BPTM [25] proess tehnology. Table I shows the elay an ative area of MUX an all gates in the library. Gate Delay(ps) Area(µ 2 ) MUX INV Buffer AND AND AND OR OR OR TABLE I DELAY OF VARIOUS GATES IN THE LIBRARY The elay of a synthesize PTL iruit was extrate by fining the longest elay path from any output to any input. Table II ompares the elay of the traitionally buffere partitione ROBDD base implementation with the generalize buffering methoology (with an without CODCs). In this table, olumn 1 lists the example uner onsieration. Column 2 reports the iruit elay, for traitional buffering. The traitional metho use for omparison was similar to that reporte in [6]. Column 3 reports elay for PTL syn-

6 thesis algorithm with generalize buffering without CODCs similar to that reporte in [7] (as a fration of the elay of the traitional metho). Column 4 an 5 report elay number for new PTL synthesis using ACODCs an CODCs respetively (again as a fration of the elay of the traitional metho). Some entries in the table are marke as -. This iniates that f ull simpli f y was not able to ompute the CODCs for that iruit. We observe that our metho (i.e. generalize buffering with ACODCs) results in a spee-up of about 29% on average ompare to the traitional metho, an about 5% over generalize buffering without CODCs. The usage of omplete CODCs using f ull simpli f y yiel a small improvement in elay of less than 1% in omparison with ACODCs. Traitional Generalize Buffering Buffering Without CODC s With ACODCs With CODCs Ckt Delay (ps) Delay Delay Delay alu alu apex C C C C C C x i x pair rot C es too large AVERAGE TABLE II DELAY COMPARISON OF GENERALIZED AND TRADITIONAL BUFFERED PTL The area alulation was performe by etermining the ative area of the MUXes an all the library ells. Table III ompares the ative area of the traitionally buffere partitione ROBDD base implementation with that of the generalize buffering methoology (with an without CODCs). In this table, Column 1 lists the example uner onsieration. Column 2 an 3 reports the iruit ative area for the traitional an generalize buffering without CODCs. Columns 4 an 5 report the area for the new PTL synthesis algorithm with generalize buffering using ACODCs an CODCs respetively. The area in Columns 3, 4 an 5 are expresse as a fration of the area of the traitional metho. Sine the generalize buffers oupy a greater area than the traitional buffers, the overall area improvement of our metho is not as high (5% on average) ompare to traitional metho. Our metho also yiels a 2% improvement in area (over generalize buffering without CODCs). In the ase of the iruit C432, when CODCs were use, the area inreases by 17% ompare to the area when ACODCs were use. This inrease in area is ue to the use of OR4 an OR3 gates uring Boolean ivision (when CODCs were use). When ACODCs were use, these gates were not utilize. Due to this, the CODC base metho exhibits a 1% area overhea over ACODC base metho (alulate over the examples for whih the CODC metho omplete). Traitional Generalize Buffering Buffering Without CODC s With ACODCs With CODCs Ckt Area (µ 2 ) Area Area Area alu alu apex C C C C C C x i x pair rot C es too large AVERAGE TABLE III AREA COMPARISON OF GENERALIZED AND TRADITIONAL BUFFERED PTL The number of MUXes is simply the sum of the sizes of eah of the partitione ROBDDs in the esign. Tables IV reports the number of MUXes use for PTL synthesis using traitional an generalize buffering. Column 1 lists the example uner onsieration. Columns 2 reports the number of MUXes require for the traitional buffering. Columns 3 reports the number of MUXes use by generalize buffering without CODCs (as a fration of the orresponing numbers for the traitional metho). Columns 4 an 5 report the number of MUXes use for generalize buffering using ACODCs an CODCs respetively (again as a fration of the orresponing numbers for the traitional metho). We observe that our metho utilizes about 27% fewer MUXes than traitional buffering an 4% fewer MUXes than generalize buffering without CODCs. Table V reports the run-time for the ifferent PTL synthesis algorithms with generalize buffering. In this table, Column 1 lists the iruit uner onsieration while Column 2 reports the run-time for generalize buffering without CODCs. Columns 3 an 4 report the run-time for generalize buffering using ACODCs an CODCs respetively. We observe from the Table V that the run-time taken generalize buffering with ACODCs is 8x more than the run-time for generalize buffering without CODCs. The run-time of our partitioning algorithm with ACODCs is slightly less than 152 seons for the largest example in our benhmark suite. The run-time for omplete CODCs was on average 76X that the run-time for ACODCs. These results iniate that generalize buffering with

7 Traitional Generalize Buffering Buffering Without CODC s ACODCs CODCs Ckt MUX MUX MUX MUX alu alu apex C C C C C C x i x pair rot C es too large AVERAGE TABLE IV NUMBER OF MUXES UTILIZED DURING TRADITIONAL AND GENERALIZED BUFFERING Generalize Buffering Without CODC s With ACODCs With CODCs Ckt Time(s) Time(s) Time(s) alu alu apex C C C C C C x i x pair rot C es too large AVERAGE TABLE V RUN-TIME FOR PTL SYNTHESIS WITH GENERALIZED BUFFERING ACODCs offers signifiantly faster esigns, with a small area benefit as well, ompare to traitionally an generalize (without CODCs) buffere PTL. The use of omplete CODCs provies minimal benefits over ACODCs. At the same time, the omplete CODC omputation took longer than the ACODCs on average. Also, omplete CODCs annot be ompute for larger iruits whereas ACODCs an be ompute for arbitrary size iruits. Therefore, the use of omplete CODCs oes not provie any pratial benefits over ACODCs. The effetiveness of our metho an be augmente by invoking ynami variable re-orering while performing ROBDD onstrution. This will allow further reution in iruit size for both the traitional an generalize buffering methoologies. V. CONCLUSIONS In this paper, we have presente a Pass Transistor Logi (PTL) iruit synthesis sheme. In orer to hanle larger esigns, an also to ensure that the total number of series evies in the resulting iruit is boune, partitione Reue Orere Binary Deision Diagrams (ROBDDs) have been use to generate the PTL iruit. Our approah utilizes partitione ROBDDs to onstrut the PTL iruit, with the interfaes between these PTL strutures buffere using library gates. Our tehnique of generalize buffering uses Boolean ivision of the PTL blok using ifferent gates in a library. In this way, we an selet the gate that results in the largest reution in the height of the PTL blok. In this manner, we an have these gates serve the funtion of buffering the outputs of PTL bloks, an also perform iruit omputations at the same time. Approximate Compatible observability on t ares (ACODCs) or omplete ompatible observability on t ares (CODCs) were use along with Boolean ivision to simplify the PTL strutures. Over a number of examples, we emonstrate that on average, our approah (generalize buffering with ACODCs) results in a 29% reution in elay, an a 5% improvement in iruit area, ompare to a traitional buffere PTL implementation. Our approah also resulte in reution in elay by 5% an reution in area by 2% over generalize buffering without on t ares. The use of omplete CODCs provies minimal benefits over ACODCs. At the same time, the omplete CODC omputation took signifiantly longer than the ACODCs. Aitionally, omplete CODCs an only be ompute for iruits with up to a few thousan gates, while ACODCs an be ompute for arbitrary size iruits. Therefore, it is better to use ACODCs over omplete CODCs. Results show that ACODCs provie enough on t ares to yiel signifiantly better PTL strutures in terms of area an elay. REFERENCES [1] R. Bryant, Graph-base Algorithms for Boolean Funtion Manipulation, IEEE Trans. Computers, vol. C-35, pp , Aug [2] K. S. Brae, R. L. Ruell, an R. E. Bryant, Effiient Implementation of a BDD Pakage, in Pro. of the Design Automation Conf., pp , June [3] R. K. Brayton, G. D. Hahtel, A. L. Sangiovanni-Vinentelli, et al., VIS: A system for verifiation an synthesis, in International Computer-Aie Verifiation Conferene (R. Alur an T. A. Henzinger, es.), vol. 1102, (New Brunswih, NJ), pp , Springer-Verlag, July August [4] E. M. Sentovih, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Salanha, H. Savoj, P. R. Stephan, R. K. Brayton, an A. L. Sangiovanni-Vinentelli, SIS: A System for Sequential Ciruit Synthesis, Teh. Rep. UCB/ERL M92/41, Eletronis Researh Lab, Univ. of California, Berkeley, CA 94720, May [5] N. Saluja an S. Khatri, A robust algorithm for approximate ompatible observability on t are (o) omputation, in Proeeings of the Design Automation Conferene, June [6] P. Buh, A. Narayan, A. Newton, an A. Sangiovanni-Vinetelli, Logi synthesis for large pass transistor iruits, in Proeeings, IEEE/ACM International Conferene on Computer-Aie Design, pp , Nov [7] Hien for blin review.

8 [8] K. Taki, A survey for pass-transistor logi tehnologies-reent researhes an evelopments an future prospets, in Proeeings of the Asia an South Paifi Design Automation Conferene (ASP-DAC), pp , Feb [9] K. Yano, Y. Sasaki, K. Rikino, an K. Seki, Top-own pass-transistor logi esign, IEEE Journal of Soli-State Ciruits, vol. 31, pp , June [10] L. Mahiarulo, L. Benini, an E. Maii, On-the-fly layout generation for ptl maroells, in Proeeings, Design, Automation an Test in Europe Conferene, pp , Marh [11] D. Rahakrishnan, S. Whitaker, an G. Maki, Formal esign proeures for pass transistor swithing iruits, IEEE Journal of Soli- State Ciruits, vol. 20, pp , April [12] E. MCluskey, Logi esign priniples : with emphasis on testable semiustom iruits. Prentie-Hall, [13] W. Quine, The problem of simplifying truth funtions, Amerian Math. Monthly, vol. 59, pp , [14] E. MCluskey, Minimization of Boolean funtions, vol. 35, pp , [15] T. Cheung, K. Asaa, an H. Wong, Design automation algorithms for regenerative pass-transistor logi, in Proeeings of 1997 IEEE International Symposium on Ciruits an Systems (ISCAS), vol. 3, pp , June [16] S.-F. Hsiao, J.-S. Yeh, an D.-Y. Chen, High-performane multiplexer-base logi synthesis using pass-transistor logi, in Proeeings of 2000 IEEE International Symposium on Ciruits an Systems (ISCAS), vol. 2, (Geneva), pp , May [17] J. Neves an A. Albiki, A pass transistor regular struture for implementing multi-level ombinational iruits, in Proeeings, Seventh Annual IEEE International ASIC Conferene an Exhibit, pp , Sept [18] C. Peron an A. Stauffer, Analysis an synthesis of ombinational pass transistor iruits, IEEE Transations on Computer-Aie Design of Integrate Ciruits an Systems, vol. 7, pp , July [19] D. Markovi, B. Nikoli, an V. Oklobzija, General metho in synthesis of pass-transistor iruits, in Proeeings. 22n International Conferene on Miroeletronis, vol. 2, pp , May [20] S. Shelar an S. Sapatnekar, An effiient algorithm for low power pass transistor logi synthesis, in Proeeings, Asia an South Paifi Design Automation Conferene an the 15th International Conferene on VLSI Design, pp , Jan [21] Y.-T. Lai, Y.-C. Jiang, an H.-M. Chu, BDD eomposition for mixe CMOS/PTL logi iruit synthesis, in Proeeings, IEEE International Symposium on Ciruits an Systems, pp , May [22] S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata, K. Rikino, an K. Seki, Pass-transistor/CMOS ollaborate logi: The best of both worls, in Digest of Tehnial Papers, Symposium on VLSI Ciruits, pp , June [23] R. Garg an S. Khatri, Generalize buffering of ptl logi stages using boolean ivision, in Proeeings of IEEE International Symposium on Ciruits an Systems (ISCAS), May To appear. [24] L. Nagel, Spie: A omputer program to simulate omputer iruits, in University of California, Berkeley UCB/ERL Memo M520, May [25] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, an C. Hu, New paraigm of preitive MOSFET an interonnet moeling for early iruit esign, in Pro. of IEEE Custom Integrate Ciruit Conferene, pp , Jun ptm.