3D Holographic Lithography

Transcription

1 3D Holographic Lithography Luke Seed, Gavin Williams, Jesus Toriz-Garcia Department of Electronic and Electrical Engineering University of Sheffield Richard McWilliam, Alan Purvis, Richard Curry School of Engineering Durham University Peter Ivey Innotec Ltd.

2 Overview Outline Numerical methods of mask computation Analytical method of mask computation Examples: Conical antenna / inductor 3d interconnect bus Through-silicon via Hemispherical micro-electrode array Mask aligner Maskless approach Application to sub-micron patterning

3 3d Lithography Challenges Proximity mask: - diffraction at mask, hence line broadening Projection lithography: - only controls diffraction in the imaging plane Photoresist deposition: - uniform thickness required over extreme topography

4 Limitations of Lithography L "!z

5 Example Simulation results based on Rayleigh-Sommerfeld solver

6 Holographic Method for Imaging a Non-Planar Substrate Holographic mask Coherent or partially-coherent UV radiation Image reconstructed at substrate surface Diffraction by mask used to define fine lines at depth

7 General 3d Mask Computation Methods Mask pattern required that will encode: Irregular routing over Irregular surface Aside: 25 x35 mm planar chip at 22 nm ~ pixels 10 x 10 x1 mm 3d structure at 1 µm ~ voxels I.e. not simple!

8 Irregular Routing on Planar Substrate E.g. Gerchberg-Saxton iterative algorithm -derives phase profile for given substrate pattern FFT Ref: Yan Borodovsky et al, Intel SPIE AL , 27,32 and 51. Mask - constant intensity - variable (quantised) phase I Substrate - required intensity distribution - any phase distribution IFFT

9 Irregular Routing on Regular 3d Surface Co-ordinate transform allows 2d iterative method to be used z = f(x,y)

10 Irregular Routing on Different Planes E.g. modified Gercheberg-Saxton algorithm -vastly increased computing time! FFT I IFFT

11 General 3d Mask Computation Method Require return to scalar wave equations (plus iteration?) hard! Define light distribution in volume? already done empirically for holographic data storage

12 Basis for Analytical Mask - the Fresnel Zone Plate x Light focused to a point Monochromatic illumination λ y z Analytical equation for generating point in space: H ( r, ) 2 & ( x + = exp $ i % ' z y 2 ) #! "

13 Line in Space Cylindrical Lens x Light focussed to a line Coherent monochromatic illumination y z Analytical equation for generating line in space: H ( x, y) = & ( y 2 exp $ i % ' z #! "

14 Non-Planar Lines H ( x, y) = & y exp $ i % ' ( 2 z x #! "

15 Mask Manufacture Function H is complex Mask should attenuate wavefront and change its phase Practical Alternatives Binary Amplitude: H is quantised to 0+j0,1+j0 Chrome on glass Binary Phase: H is quantised to -1+j0,1+j0 Patterned PMMA giving π radians phase shift If a chrome layer is added then a third quantised value is 0+j0 Binary Phase/Grey Scale Amplitude: H is quantised to n bits (e.g. 3) - that is -7/8+j0, -6/8+j0 0+j0, 1/8+j0 7/8+j0 As Binary Phase but more complex chrome patterning Continuous phase see later

16 Binary Masks Resulting image not perfect because of: Pixellation (40 µm) localisation of mask pattern within alias limit Quantisation Binary amplitude (COG) Binary phase (PSM) (enhanced signal) (y) Intensity cross-section of image formed by binary amplitude and binary phase masks I ~ sinc 2 (y) plus extra noise terms Side lobes reduce resist process window

17 Line Shape Enhancement Control of line width w diffraction pattern from a narrow slit is a sinc function, therefore modulate H with sinc function: & wy S( y) = sinc$ % ' z Line termination control diffraction pattern from a broad slit is described by the Fresnel integral, therefore modulate H with Fresnel integral: F( x) = 1 2 ( 1 ' ) 2 $! exp% i ( " d( & 2 # ( 2 (α 1 and α 2 define line length) #! " Simulated intensity distribution for binary mask Hence: 2 H & ( y ( x, y) exp i S( y) F( x) z! # = $ % ' "

18 Greyscale Amplitude/Binary Phase Encode amplitude by variation in aperture size within pixel: Lines imaged onto silicon substrate 100 µm 40um No width / termination control Section of binary phase / pseudo greyscale amplitude mask Controlled width / termination 150 µm

19 Simple mask Comparison Width/length compensated mask

20 Closely-Packed and Intersecting Lines Example: Intensity Required pattern Simple mask formed by summing 2 line patterns Position Large spike in intensity at line intersection Analytical technique fails for closely-packed and intersecting lines!

21 Example: GPS Antenna Designs Drawings taken from various patent applications

22 Example: GPS Antenna Designs All require accurate surface routing on grossly non-planar surface Manufactured by folding of flexible circuit or by direct-write

23 Mask Design for Bihelical Tracks 3d spiral & # $ * 2 H ( r, () = exp i ( r ' R ) )! ( % ) z( " R φ = radial location of line z φ = angular dependent masksubstrate separation Pattern truncated at pixel alias limit Second line defined by 180 rotation around φ axis Peripheral zone plates used for x,y,(z) alignment Binary amplitude mask

24 Illuminated Test Substrate 22 mm Representative of ultrawide band (UWB) GHz antenna Ideally requires constant angular arm width

25 Lithographically-Patterned Conical Substrate 100!m 62 µm 22 mm 100!m 100!m Patterning process: Electroless seed layer (1 µm Ni) Electrophoretic resist (10 µm PEPR2400) Exposure (λ = 405 nm, E = 150 mj/cm²) Develop Electroplate (1 µm Au) Strip Seed layer etch

26 Fully Processed Substrate This structure representative of UWB antenna

27 Illumination of Test Cone Intensity measurements through horizontal slices Strong, narrow line at prescribed z High noise, but not important because it does not intersect substrate

28 Example: Bus Over 3 mm Step 3 mm 750 µm 20 µm 20 µm Constant-width gold tracks on nickel-coated stepped machined glass-ceramic substrate Measured and simulated intensity crosssections from binary phase mask (z = 6 mm)

29 Example: Silicon Via Top 9 µm Sloping side wall Top surface 9 µm Constant-width gold track patterned down the side wall of anisotropically etched 500 µm-thick Si wafer Base Measured intensity crosssections from binary phase mask

30 Comparison Between CGH and Slit Mask (anisotropically etched silicon wafers) Broadened lines Constant width line 500 µm Slit mask CGH mask

31 Example: Interconnect for Sensor Array CGH mask Illuminated test substrate Substrate design (15 mm diameter)

32 Mask Aligner Camera Beam splitter Laser Beam expander Shutter Holographic mask Spacer Substrate 3d substrate illuminated through holographic mask x,y,z,! table Laser diode module (100 mw, 405 nm, CW, TEM00) Visible light use for exposure and alignment Coherent illumination (σ ~ 0), therefore speckle a problem (projection illumination may be used to control this)

33 A Maskless Projection System

34 To Track Over a Larger Surface

35 SLM Technology Liquid crystal on silicon (LCoS) SLM Non-twisted (1900x1080 pixels) Allows multi-level phase, cannot use 0 order image Intelligent Micro Patterning (IMP) SF-100 lithography instrument containing an SVGA (1024 x 768 pixel) micromirror device Only allows binary amplitude

36 Key Process Challenges LCoS and DMD technology at UV wavelengths Diffraction efficiency is critical High energy DMD looks promising Possible issue about reliability of mirror alignment LCoS under investigation Short wavelengths can damage LC and/or surfactants Combination of LCoS and DMD to produce amplitude/phase? Substrate preparation Photoresist layer should be 1µm or less Electrodeposition methods often limited to thicker layers We are already depositing layers below 2µm thick

37 CAD for CGH Pattern Substrate Topography CGH Pattern on substrate + +

38 Desktop Illustration Live image from camera Pattern preview Simulated pattern LCoS preview and control (256 phase levels) Live LCoS image CGH mask preview

39 Partial Coherence Experiment LED Camera Pinhole Lens CGH Intensity cross-sections from illuminated line CGH Larger hole Smaller hole Sharp line generated by laser or by suitably prepared non-laser source Reduced spatial coherence gives lower speckle

40 Application to Semiconductor Fabrication Projection lithography would allow smaller features If maskless technology is used then we will need to use projection because pixel sizes are > 1 µm Uniform resist deposition by spray or vapour deposition

41 Image Reduction Experiment Fourier CGH Real image Reduced Image

42 Result Phase CGH of a tilted line Nearest plane Middle plane Farthest plane

43 Summary 3d lithography has been demonstrated for sparse patterns on regular shapes well beyond the usual confines of lithography Enhanced numerical methods needed for dense patterns on irregular shapes Plenty of issues regarding alignment, CD, etc Technique offers alternative to direct write Enables novel interconnect R2D2 shows us how it should be done! schemes

44 Acknowledgements Jesus Toriz-Garcia Andrew Maiden Gavin Williams Richard McWilliam Richard Curry Alan Purvis Peter Ivey Funding: Engineering and Physical Sciences Research Council, UK