Introduction to Digital Signal Processing Systems

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1 Itroductio to Digital Sigal Processig Systems ( 范倫達, Ph. D. Departmet of Computer Sciece atioal Chiao Tug Uiversity Taiwa, R.O.C. Fall, 207 ldva@cs.ctu.edu.tw

2 Outlies Itroductio DSP Algorithms DSP Applicatios ad CMOS IC s Represetatios of DSP Algorithms Coclusio Refereces VLSI-DSP--2

3 Why Use Digital Sigal Processig? Robust to temperature ad process variatios Cotrolled better to accuracy oise/iterferece toleraces Mathematical represetatio Programmig capability VLSI-DSP--3

4 Commo System Cofiguratio Multimedia-Commuicatio-Biomedical Applicatios VLSI Sigal Processig Library Processor Software VLSI-DSP--4

5 VLSI Sigal Processig System Desig Spectrum (/2 Computer arithmetic Adder Multiplier Iverse square root Divisio Digital filter Multidimesioal filter Symmetry filter Adaptive digital filter LMS/DLMS (Delay LMS based RLS based Trasform Multiplier-accumulator based Recursive-filter based ROM-based: DA, CORDIC Butterfly based Processor Geeral purposed processor DSP processor Recofigurable computig processor Machie Learig Idepedet Compoet Aalysis (ICA Covetioal eural etwork (C 3D Graphics Geometry trasformatio Rasterizatio/Rederig Z-buffer compressio Texture compressio VLSI-DSP--5

6 VLSI Sigal Processig System Desig Spectrum (2/2 MIMO Detectio Grouped Detectio VBLAST K-Best Biomedical Computatio Machie Learig ICA PCA HRV Image Processig Patter Recogitio Media Filter Image Recostructio Image Ehacemet Video Processig Compressio Block Matchig Deblockig filter o-umerical operatio Error cotrol codig Viterbi Decoder Turbo Code Polyomial computatio Dyamic programmable VLSI-DSP--6

7 VLSI Sigal Processig System Publicatio Area (But ot limited IEEE Tras. o Biomedical Egieerig IEEE Tras. o Circuits ad Systems I: Regular Papers IEEE Tras. o Circuits ad Systems II: Express Briefs IEEE Tras. o Circuits ad Systems for Video Techology IEEE Tras. o Commuicatios IEEE Tras. o Computer-Aided Desig of Itegrated Circuits IEEE Tras. o Computers IEEE Tras. o Image Processig IEEE Tras. o Iformatio Theory IEEE Tras. o Multimedia IEEE Tras. o eural etworks IEEE Joural o Selected Areas i Commuicatios IEEE Tras. o Sigal Processig IEEE Joural of Solid-State Circuits IEEE Tras. o VLSI Systems IEEE Tras. o Visualizatio ad Computer Graphics Proceedigs of the IEEE ACM Tras. o Graphics Joural of Sigal Processig Systems IEICE Trasactios o Fudametals of Electroics, Commuicatios ad Computer Scieces Elsevier Itegratio - The VLSI Joural VLSI-DSP--7

8 VLSI Sigal Processig System Desig Space Cost Performace Test Power Area System Level Algorithm Level Architecture Level Logic Level Circuit Level Process Level VLSI-DSP--8

9 Outlies Features: DSP Algorithms DSP Applicatios ad CMOS IC s Represetatios of DSP Algorithms VLSI-DSP--9

10 DSP Algorithms Covolutio Algorithm: A set of rules for solvig a Correlatio problem i a fiite umber of steps. Digital filters Adaptive filters Discrete Fourier trasform Source Codig Algorithms Discrete cosie trasform Motio estimatio Huffma codig Vector quatizatio Wavelet ad filter baks FastICA Covetioal eural etwork VLSI-DSP--0

11 Sigals Aalog sigal t->y: y=f(t, y:c, t:c Discrete-time sigal ->y: y=f(t, y:c, :Z Digital sigal ->y: y=d{f(t}, y:z,:z y y y ( 2 ( ( ( 3 (0 2 (000 2 (000 2 (0 2 t Aalog Sigal Discrete-Time Sigal Digital Sigal VLSI-DSP--

12 Liear systems LTI Systems Assume x (->y ( ad x 2 (->y 2 (, where -> deotes lead to. If ax (+bx 2 (->ay (+by 2 (, the the systems is referred to as Liear System. Homogeous ad additive properties Time-ivariat (TI systems x(- 0 ->y(- 0 LTI systems y(=h(*x( Causal systems y( 0 depeds oly o x(, where <= 0 Stable systems BIBO VLSI-DSP--2

13 Samplig of Aalog Sigals yquist samplig theorem The aalog sigal must be bad-limited Sample rate must be larger tha twice the badwidth VLSI-DSP--3

14 System-Equatio Represetatio Impulse/uit sample respose h( b a Trasfer fuctio / frequecy respose H( z Differece equatios 0 u[ Y( z b X ( z a y( a y( b0 ] 0 z x( State equatios VLSI-DSP--4

15 VLSI-DSP--5 Covolutio & Correlatio Covolutio k k h k x h x y ( ( ( ( ( ( ( ( ( x a k x k a k k k x k a y ( ( ( Correlatio ( ( k x k h k

16 Liear Phase FIR Digital Filters Digital filters are a importat class of LTI systems. Liear phase FIR filter h( h( M h( 0 h(6 b0 h( h(5 b h( 2 h(4 b h( 3 b 3 2 y( b b 0 x( 0 x( b 6 b x( b x( 5 b 2 2 x( x( 2 4 b 3 x( 3 VLSI-DSP--6

17 IIR Filter Structures H b b z b z 2 ( z 0 2 a z a z 2 2 z z VLSI-DSP--7

18 Itroductio to a Adaptive Algorithm Widely used i commuicatios, DSP, biomedical, ad cotrol system Determiistic gradiet algorithm RLS algorithm Stochastic gradiet algorithm LMS algorithm, DLMS algorithm Block LMS algorithm Gradiet Lattice algorithm VLSI-DSP--8

Beamformer Lie ehacemet Image ehacemet Machie Learig

19 Adaptive Applicatios Chael equalizer System idetificatio Echo caceller oise cacellatio Predictor Beamformer Lie ehacemet Image ehacemet Machie Learig VLSI-DSP--9

20 otatio. Iput Sigal: x( 2. Desired Output: d( 3. Weight Vector: w( 4. AdaptatioFactor: μ 5. Error: e( 6. Misadjustm et: M adj 7. Tap umber : 8. Autocorrel atio Matr 9. Eigevalue :λ 0. Diagoal Matrix : ix: R VLSI-DSP--20

21 VLSI-DSP--2 LMS Algorithm ( ( ( y T x w T x x x where ] (... ( ( [ ( x T w w w ] (... ( ( [ ( 0 w ( ( ( ( ( ( ( ( ( d d y d e T T w x x w The error at the -th time is

22 LMS Algorithm A efficiet implemetatio i software of steepest descet usig measured or estimated gradiets, where the cost fuctio with gradiet is square errors. The gradiet of the square of a sigle error sample w( w( ( ˆ J ( 2 ˆ J ( 2e( x( w( Cost w( μe(x( w0, w, w0 VLSI-DSP--22

23 Summary of LMS Adaptive Algorithm (960 y( w ( x( e( d( y( T w( w( e( x( VLSI-DSP--23

24 Block Diagram of a Adaptive FIR Filter Drive by the LMS Algorithm VLSI-DSP--24

25 Uitary/Orthogoal Trasform (/4 Defiitio: (from Liear Algebra Let A be AA A A matrix that satisfies I. We call A as a uitary matrix if A has complex etries, ad we call A as a orthogoal matrix if A has real umber. VLSI-DSP--25

26 Why Orthogoal Trasformatio? (2/4 Eergy coservatio Eergy compactio Most uitary trasforms ted to pack a large fractio of the average eergy of sigals ito a relatively few compoets of the trasform coefficiets. Decorrelatio Whe sigals are highly correlated, the trasform coefficiets ted to be ucorrected (or less correlated. Iformatio preservatio The iformatio carried by sigals are preserved uder a uitary trasform. VLSI-DSP--26

27 Why Orthogoal Trasformatio? (3/ The origial sigal The DCT coefficiets Source: Lecture of Prof. Deis Deg VLSI-DSP--27

28 Why Orthogoal Trasformatio? (4/4 The auto correlatio of origial sigal The auto correlatio of DCT coefficiets Source: Lecture of Prof. Deis Deg VLSI-DSP--28

29 VLSI-DSP--29 Discrete Fourier Trasform (/9 DFT IDFT 0,,...,, ( ( 0 k W x k X k 0,,...,, ( ( 0 W k X x k k k j k j e W e W 2 2,

30 Fast Fourier Trasform (2/9 The radix-2 algorithm is the most widely used fast algorithm to compute the DFT. Without loss of geerality, we use a 8-poit DFT (=8 to illustrate the developmet of the fast algorithm. X ( k x(0 x( W W x(0 k k 7 0 x(2 W x(2 W ( x( x( W 2k x(3 W 2k 3k x(3 W k 2k x(4 W x(5 W x(4 W 4k 4k 5k x(5 W 4k x(6 W x(7 W x(6 W 6k 6k 7k x(7 W 6k VLSI-DSP--30

31 Fast Fourier Trasform (3/9 Sice 2 2 j 2k j k 2k ( / 2 k W e e W / 2 8-poit DFT => early two 4-poit DFT k k X ( k x(0 x(2 W x(4 W x(6 W W F where k ( x( ( k W k x(3 W F 2 F ( k adf2 ( k / 2 k / 2 x(5 W 2 / 2 2k / 2 x(7 W ( k, where k 0,,2,... 3k / 2 3k / 2 represet the DFT of two sequeces f( x(2 adf2( x(2 VLSI-DSP--3

32 Fast Fourier Trasform (4/9 Oe step further: (=>Two 4-poit DFT W k / 2 e 2 2 j ( k / 2 j k e k ( k, k 0,,..., / 2 X ( k F ( k W F2 j X ( k / 2 F ( k W F2 e W k ( k, k 0,,..., / 2 A -poit DFT requires 2 complex multiplicatios. The umber of complex multiplicatios required by the above algorithm is as follows. 2( / A 8-poit DFT requires 64 complex multiplicatios. k ( ad 8 k / 2 k W / 2 W / 2 VLSI-DSP--32

33 Fast Fourier Trasform (5/9 The 4-poit DFT ca be decomposed ito two 2-poit DFT i a similar way. k k k F ( k x(0 x(4 W x(2 W x(6 W x(0 V( k W / 2V2( k where V (k ad V 2 (k represet the DFT of two sequeces. As before, v x(4 W k k / 4 2 / 2 W k / 2 ( x(2 / 2 x(6 W ( f(2 ad v2( f(2 k / 4 k 3 / 2 F ( k V( k W / 2V2( k, k 0,,..., / 4 k F ( k / 2 V( k W / 2V2( k, k 0,,..., / 4 VLSI-DSP--33

34 Fast Fourier Trasform (6/9 VLSI-DSP--34

35 Fast Fourier Trasform (7/9 A 2-poit FFT, such as real additio V ( k x(0 W 2 k V ( k adv 2( k x(4, W 0 2, W 2 ivolves oly V ( 0 x( 0 W x( 4 V ( x( 0 W x( a A b W - Each butterfly requires oe complex multiplicatio ad two complex additio B VLSI-DSP--35

36 Fast Fourier Trasform (8/9 After decimatio, the sequece is i a bit-reversed order origial order decimatio decimatio VLSI-DSP--36

37 Fast Fourier Trasform (9/9 This FFT algorithm is geerally true for ay data v sequece of 2 There are /2 butterflies per stage ad stages The umber of operatios required for a FFT: (Before simplifyig Complex multiplicatio: log2 log 2 Complex additio: log2 VLSI-DSP--37

38 Image/Video Compressio Where codig? Source codig Chael codig Source codig beefits Lower bit rate Less trasmissio time Fewer storage data What kid of loss? Lossless data compressio Lossy data compressio Why ca we do compressio? Codig redudacy Iter-sample redudacy (Spatial redudacy Iter-frame redudacy (Temporal redudacy VLSI-DSP--38

39 Source Codig Spectrum Image Compressio Lossless Huffma Codig Shao Codig ArithmeticCodig Loss Predictive Codig Trasform Codig VQ Codig Subbad Codig VLSI-DSP--39

40 Image Measuremet ad Evaluatio SR(dB 0 log 2 2 0( x / PSR(dB 0log 2 2 0(255 / [ x( i, 2 i j j x( i, j] 2 where x(i,j ad xˆ (i,j deote the origal image ad recostructed image valules, respectively. VLSI-DSP--40

41 Discrete Cosie Trasform (DCTII X ( k ( k 0 (2 k x( cos[ ] 2, 0 k - 2 ( 0 ( k, for k VLSI-DSP--4

42 DCT-II Z( k, l T Z AXA IDCT-II x( m, α( 0 T / 2 ( k ( l 2 k0 X A ZA where k, l, m, 2-D DCT-II ad IDCT-II (2m k (2 l x( m, cos( cos( 2 2 m0 0 (2m k (2 l ( k ( l Z( k, lcos( cos( 2 2 l0 ad rages 2 ad α(j for from 0 to j 0. -ad VLSI-DSP--42

43 VLSI-DSP--43 How to Decide the Coefficiets? Orthogoal Property I A A AA T T Parseval s Theorem: Eergy Coservatio ( ( k k X x

44 2-D DCT/IDCT Processor (a (b VLSI-DSP--44

45 Block-Matchig Algorithm Rule: s( m, i0 j0 x( i, j u mi { ( m, s( m, } v ( m, u y( i m, j for for p m, p p m, p VLSI-DSP--45

46 Etropy Huffma Codig (/3 Iformatio Measuremet Ucertaity Measuremet Surprise Measuremet H( P q i Compressio Ratio p i log (/ p i 2 Cr ucodig bits codig bits VLSI-DSP--46

47 Huffma Codig (2/3 Iput Probability x x 2 x 3 x x x x 7 64 x VLSI-DSP--47

48 log 2 AvLe AvLe Cr H( x 2 x atural_code Huffma_Code 4 x2 8 3 ucodigbits codigbits Etropy x3 Huffma Codig (3/3 bit 6 x4 64 Data Huffma Code atural Code x 000 x x x x x x x log 24 log 28 log 26 (4xlog (4x6 2 bit bit VLSI-DSP--48

49 Outlies Features: DSP Algorithms DSP Applicatios ad CMOS IC s Represetatios of DSP Algorithms VLSI-DSP--49

50 Moore s Law Micros Tr. # (Complexity 0 0G G 00M 0M Gate Legth Device Complexity 58% / year Gap Icreases Tr. # (Productivity 00M 0M M 00K 0. M 00K 0K x x x x x x x x 2%/ year Desig Productivity 0K K K Source: Sematech The umber of trasistors per chip doubles every 8 moths. * Cordo Moore: Oe of the fouders of Itel VLSI-DSP--50

51 Evolutio of Applicatios VLSI-DSP--5

52 Chroological Table of Video Codig Stadards ITU-T VCEG H.26 (990 ISO/IEC MPEG MPEG- (993 H.263 (995/96 H.263+ MPEG-2 (H.262 (994/95 (997/98 H (2000 H.264 (MPEG-4 Part 0 MPEG-4 v (2002 (998/99 MPEG-4 v2 (999/00 MPEG-4 v3 (200 H.265 (HEVC ( VLSI-DSP--52

53 Chroological Table of Video Codig Stadards

Compariso of Video Stadards Source: http://40.7.56.

54 Compariso of Video Stadards Source: VLSI-DSP--54

55 Block Diagram of H.264/AVC Ecoder Iput Video Sigal Split ito Macroblocks 6x6 pixels - Decoder Coder Cotrol Trasform/ Scal./Quat. Scalig & Iv. Trasform Cotrol Data Quat. Trasf. coeffs Etropy Codig Itra/Iter Itra-frame Predictio Motio- Compesatio De-blockig Filter Output Video Sigal Motio Estimatio Motio Data VLSI-DSP--55

56 Block Diagram of H.265/HEVC Ecoder VLSI-DSP--56

57 Geometry Egie Raster Egie 3D Graphics System VLSI-DSP--57

58 Shadig Algorithms (/2 Gouraud shadig Per-vertex lightig Low computatio ot good shadig quality Phog shadig Per-pixel lightig Huge computatio Smooth ad more realistic highlight VLSI-DSP--58

approximate algorithms o pass Pass Mixed shadig

59 Shadig Algorithms (2/2 Existig Approximate Phog Shadig Algorithms Mixed shadig Subdivisio based approximate algorithms o pass Pass Mixed shadig Subdivisio Source: ACM/IEEE 59 VLSI-DSP /0/5

Four Area etworks From small to big: Persoal area

area etwork 資料來源 : 無線都會網路新貴 WiMAX 標準介紹, http://tech.

zcatid=34&zotesdocid=e88a9e50386245d48256f5b0028cac

60 Four Area etworks From small to big: Persoal area etwork Local area etwork Metro area etwork Wide area etwork 資料來源 : 無線都會網路新貴 WiMAX 標準介紹, VLSI-DSP--60

61 Commuicatio Stadards Evolutio (/4 Low Mobility High Mobility GSM/GPRS WCDMA HSPA 3GPP LTE WA WiMAX 802.6e WiMAX 802.6d WiMAX 802.6m MA ZigBee RFID Low data rate Bluetooth b 802.a/g 802. WiMedia a LA PA 0. Mbps Mbps 0 Mbps 00 Mbps 000 Mbps High data rate Source: UMTS Forum VLSI-DSP--6

62 Commuicatio Stadards Evolutio (2/4 VLSI-DSP--62

Commuicatio Stadards Evolutio (4/4 http://www.digitimes.com.

63 Commuicatio Stadards Evolutio (4/4 VLSI-DSP--63

64 Comparisos of Various Cellular Stadards VLSI Digital Sigal Processig Systems 行動通信技術發展 ( 資料來源 : Agilet Techologies VLSI-DSP--64

65 Compariso of LTE ad WiMax VLSI-DSP--65

66 Compariso of 802.xx

Compariso of Short-Distace Commuicatio http://www.digitimes.

67 Compariso of Short-Distace Commuicatio

Digital Commuicatios System Eablig the trasmitted sigal to withstad the effects of various chael impairmets, such as oise, iterferece, ad fadig.

68 Digital Commuicatios System Eablig the trasmitted sigal to withstad the effects of various chael impairmets, such as oise, iterferece, ad fadig. Iformatio Source Source Ecoder Ecrypter Error Cotrol Ecoder Modulator Chael Iformatio Sik Source Decoder Decrypter Error Cotrol Decoder Demodula tor VLSI-DSP--68

69 ODFM System Source: Prof. We, CCU. VLSI-DSP--69

70 Outlies Features: DSP Algorithms DSP Applicatios ad CMOS IC s Represetatios of DSP Algorithms Depedece Graph Data-Flow Graph Sigal-Flow Graph Block Diagrams VLSI-DSP--70

71 Def: A depedece graph is a direct graph that shows the depedece of the computatios i a algorithm. The ode i a DG represet computatios ad the edges represet precedece costraits amog odes. DG cotais computatios for all iteratios i a algorithm ad does ot cotai delay elemets. DG of a 3-Tap FIR Filter VLSI-DSP--7

72 Def: A data flow graph (DFG is a collectio of odes ad directed edges. The odes represet computatios (or fuctios or subtasks ad the directed edges represet data path ad each edge has a oegative umber of delays associated with it. DFG of a 3-Tap FIR Filter VLSI-DSP--72

73 Def: A sigal flow graph (SGF is a collectio of odes ad directed edges. The odes represet computatios or tasks. I digital etworks, the edges are usually restricted to costat gai multipliers or delay elemets. SFG of a 3-Tap FIR Filter VLSI-DSP--73

74 Block Diagram of a 3-Tap FIR Filter Def: A block diagram cosists of fuctioal blocks coected with directed edges. VLSI-DSP--74

75 Coclusios Briefly itroduced the followig: DSP desig issue ad desig view DSP algorithms Overview of DSP applicatios Represetatios of DSP algorithms VLSI-DSP--75

76 Refereces [] K. K. Parhi, VLSI Digital Sigal Processig Systems: Desig ad Implemetatio. Y: Wiley, 999. [2] P. Pirsch, Architectures for Digital Sigal Processig. Y: Wiley, 998. [3] A. V. Oppeheim ad R. W. Schafer, Discrete-Time Sigal Processig. Eglewood Cliffs, J: Pretice-Hall, 989. [4] S. Hayki, Adaptive Filter Theory, 3rd ed. Eglewood Cliffs, J: Pretice-Hall, 996. [5] 連國珍, 數位影像處理, 992. VLSI-DSP--76

Chapter 3 Classification of FFT Processor Algorithms

Chapter 3 Classification of FFT Processor Algorithms Chapter Classificatio of FFT Processor Algorithms The computatioal complexity of the Discrete Fourier trasform (DFT) is very high. It requires () 2 complex multiplicatios ad () complex additios [5]. As