Design of Efficient Pipelined Radix-2 2 Single Path Delay Feedback FFT

Transcription

1 IOSR Joural of VLSI ad Sigal Processig IOSR-JVSP Volume Issue Ver. I May-Ju. 0 PP 88-9 e-iss: 9 00 p-iss o. : Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT isha Laguri # Deepshiha Bharti * K. Ausudha # # M.Tech Studet Electroics Departmet of Electroics Egieerig Podicherry Uiversity * M.Tech Studet Electroics Departmet of Electroics Egieerig Podicherry Uiversity # Assistat Professor Departmet of Electroics Egieerig Podicherry UiversityPuducherry Idia Abstract: Digital Sigal Processig DSP has become a very importat ad dyamic research area. ow-aday s may itegrated circuits are dedicated to DSP fuctios. Fourier Trasform is widely used i idustrial applicatios as well as i scietific research. The performace i terms of throughput of the processor is limited by the multiplicatio. Therefore the multiplier is optimized to mae the iput to output delay as short as possible. A ew FFT architecture based o distributed arithmetic has bee developed ad is compared to a previous multiplier based FFT. A efficiet implemetatio of a pipelied Radi- Sigle Path Delay Feedbac FFT is proposed i this paper. I this Covetioal R- SDF FFT architecture comple multiplier ad multiplier-less architecture based o distributed arithmetic ad parallel prefi adder techique are eplaied. The advatages performace ad timig of the commuicatio modules after implemetatio of the proposed techique are the discussed at the ed. The compariso clearly idicates that the R- SDF FFT with the proposed architecture is efficiet tha the other implemetatios of its id. Keywords: FFT Twiddle Factor Butterfly Uit Comple Multiplier I. Itroductio Pipelie FFT processor is a specified class of processors for DFT computatio utilizig fast algorithms. It is characterized with real-time o-stop processig as the data sequece passes through the processor. It is a AT o-optimal approach with AT =O sice the area lower boud is O. The class of pipelie FFT processors has probably the smallest costat factor amog the approaches that meet the time requiremet due to its least umber Olog of Arithmetic Elemets AE. The differece comes from the fact that a AE especially the multiplier taes the much larger area tha a register i digital VLSI implemetatio. For hardware implemetatio various FFT processors have bee proposed. These implemetatios ca be maily classified ito memory-based ad pipelie architecture based. Memory-based architecture is widely adapted to desig FFT processor also ow as sigle processig elemet PE approach. This desig style is usually composed of a mai PE ad several memory uits thus the hardware cost ad power cosumptio both is lower tha the other architecture style. However this id of architecture style has log latecy low throughput ad ca ot be parallelized. O the other had the pipelie architecture style ca get rid of the disadvatages of the foregoig style at the cost of a acceptable hardware overhead. Geerally the pipelie FFT processors have two popular desig types. Oe uses sigle-path delay feedbac SDF pipelie architecture ad the other uses multiple-path delay commutator MDC pipelie architecture. Such implemetatios are advatageous to low-power desig especially for the applicatios i portable DSP devices. Based o these reasos the SDF pipelie FFT is adopted i this. The proposed architecture icludes a distributed arithmetic based comple multiplier istead of usig multiplier to store twiddle factors. I this paper a more detailed ad completed descriptio of the etire wor is provided. The rest of this paper is orgaized as follows. First a brief review of the Radi- Fast Fourier trasform is described i Sectio II. Sectio III presets the Radi- FFT architecture. Sectio IV discusses the eistig architecture. The performace evaluatio of distributed arithmetic based comple multiplier is the discussed i Sectio V. Sectio VI presets proposed architecture. Results are compared with other architectures i Sectio VII ad lastly sectio VIII provides the coclusio. II. Radi- Decimatio I Frequecy FFT Algorithm The Discrete Fourier Trasforms DFT X of a -poit discrete-time sigal is defied by: X 0 0 < Page

2 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT 89 Page here deotes the primitive th root of uity with its epoet modulo is the iput sequece ad X is the DFT. Applyig a -dimesioal liear ide map. Ad Commo factor algorithm CFA to derive a set of DFTs of legth / as H X 0 where are the ide terms of iput sample ad are the ide terms of the output sample ad where H is epressed i equatio. H j. Above equatio represets the first two stages of butterflies with oly trivial multiplicatios i SFG as BFI ad BFII. Full multipliers are required after the two butterflies i order to compute the product of the decomposed twiddle factor i equatio. Applyig this CFA procedure recursively to the remaiig DFTs of legth / i equatio the complete radi- Decimatio-i-frequecy DIF FFT algorithm is obtaied. The correspodig FFT sigal flow graph for =6 is show i Figure where small diamods represet trivial multiplicatio by- j / it ivolves oly real-imagiary swappig ad sig iversio. Figure : Radi- DIF FFT flow graph for =6 III. Radi- FFT Architecture Mappig radi- DIF FFT algorithm derived to the radi- SDF architecture a ew architecture of R- SDF approach is obtaied. Figure outlies a implemetatio of the Radi- SDF sigal flow graph for =6 ote the similarity of the data-path to RSDF ad the reduced umber of multipliers. The implemetatio uses two ids of butterflies; oe idetical to that i the RSDF the other cotais also the logic to implemet the trivial twiddle factor multiplicatio....

3 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT Due to the spatial regularity of Radi- algorithm the processor s sychroizatio cotrol is very simple. A log-bit biary couter serves two purposes: sychroizatio cotroller ad address couter for twiddle factor readig i each stage. ith the help of butterfly structures show i Figure the scheduled operatio of the R- SDF processor i Figure is as follows. O first / cycles the -to- multipleers i the first butterfly module switch to positio 0 ad the butterfly is idle. The iput data from left is directed to the shift registers util they are filled. O et / cycles the multipleers switch to positio the butterfly computes a -poit DFT with icomig data ad the data stored i the shift registers. Z Z The butterfly outputs Z ad Z + / are computed accordig to the equatio. Z is set to apply the twiddle factors ad Z + / is set bac to the shift registers to be multiplied i still et / cycles whe the first half of the et frame of time sequece is loaded i. The operatio of the secod ad third butterfly is similar to that of the first oe ecept the distace of butterfly iput sequece are just / ad the trivial twiddle factor multiplicatio has bee implemeted by real-imagiary swappig with a commutator ad cotrolled add/subtract operatios which eeds two bit cotrol sigal from the sychroizig couter. Data the goes through a full comple multiplier. Further processig repeats this patter with the distace of the iput data decreases by half at each cosecutive butterfly stages. After - cloc cycles the result of complete DFT trasform streams out to the right i bi-trasversed order. The et frame of trasform ca be computed without pausig due to the pipelied processig of each stage. Figure : Radi- SDF pipelie FFT architecture Figure : Butterfly Structure-I Figure : Butterfly Structure-II 90 Page

4 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT IV. Eistig Architecture Traditioal hardware implemetatio of FFT/IFFT processors usually employs a ROM to loo up the wated twiddle factors ad the word legth of comple multipliers to perform FFT computatio. However this itroduces more hardware cost thus a bit-parallel comple multiplicatio scheme is used to improve the foregoig issue. Sice the twiddle factors have a symmetric property the comple multiplicatios which are used i the FFT computatio ca be oe of the followig three operatio types- K. a jb b ja /. a jb b ja / / / a jb b ja /.. 9 Give the above three equatios ay twiddle factor ca be obtaied by combiatio of these twiddlefactor primary elemets. I other words arbitrary twiddle factor used i FFT ca utilize these operatio types to derive the wated value thus ca sigificatly reduce the size of ROM used to store the twiddle factors. Figure 5: Covetioal Comple Multiplier Booth multiplicatio algorithm has bee used for comple multipliers. Thus the overall latecy of the real-time implemetatio varies as the processig word legth chages. V. Distributed Arithmetic Method for Comple Multiplicatio I this sectio comple multiplicatio operatio usig DA is eplaied. DA ca be used to implemet multiplicatio operatio if either the multiplicad or the multiplier value is fied. It stores the possible combiatios of fied operad i ROM ad suitable combiatio is added ad shifted with respect to bits of other operad. The method for DA base comple multiplicatio ca be summarized as: Z jz B jb * T j T R I R I R I 0 here Z I Z R BRT BRT I R BIT BIT R I It shows that real multiplicatios ad real additios are required to compute Z R ad Z I. But these equatios ca be cosidered as oe multiply ad accumulate operatio y c. 9 Page

5 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT Let C are fied coefficiets ad are the iput words. If is M-bit fractioal umber i s complemet form the it ca be epressed i followig form- b M m b m 0 m VI. Proposed Architecture Figure 6: DA based comple multiplier I proposed architecture a pipelied Radi- SDF FFT uit is desiged without usig multipliers. All the comple multiplicatios required for this type of FFT are implemeted usig Distributed Arithmetic DA techique. The detailed architecture for comple multiplier is show i above Figure 6. The real ad imagiary parts of icomig words B R ad B I are stored i two 8 bits wide parallel i serial out register. Shiftig is carried out startig from LSB to MSB. Each output bit of these two registers is used as address lies of the ROMs. The ROM stores precalculated outcomes for both Z R ad Z I. The size of each ROM is 8. Oe of the iput to the : MUX is directly fed from the output of ROM ad the other iput to MUX is iverted. Iput ad output bit width for MUX is also 8 bits. The select lie of MUX is ci sigal ad it remais as 0 till the MSB arrives at output. If select lie ci of Mu is it selects iverted output from ROM ad it is added to the value stored i the partial product register PPR. The PPR is 8 bit wide parallel i parallel out register which also performs -bit right shift operatio. Fially the output is tae from the left shift register. VII. Parallel Prefi Adder The Bret-Kug adder is a parallel prefi adder. Parallel prefi adders are special class of adders that are based o the use of geerate ad propagate sigals. Simpler Bret-Kug adders was bee proposed to solve the disadvatages of Kogge-Stoe adders. The cost ad wirig compleity is greatly reduced. It cosidered as oe of the better tree adders for miimizig wirig tracs fa out ad gate cout ad used as a basis for may other etwors. The bloc diagram of 8-bit Bret-Kug adder is show i Fig.7. Figure 7: 8-bit Bret-Kug adder 9 Page

6 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT VIII. Result Ad Discussio The desig of Sigle Path Delay Feedbac FFT was modeled i VERILOG by maig use of a module based structure approach. Both the SDF FFT were desiged ad sythesized by usig Xili-. versio o Sparta- device. All the operatio ca be simulated at oe time; the behavioural simulatio is doe by eecutig the test bech file. Table I. Compariso betwee covetioal ad proposed comple multiplier Parameters Eistig Comple Multiplier Proposed Comple Multiplier o. of slices 00 5 Delay s Table I. shows the compariso betwee eistig ad proposed comple multiplier. There is a huge differece betwee eistig ad proposed comple multiplier because i eistig we have used multiplier blocs but i case of proposed it is without the use of multiplier it is basically made up of registers. Ad register taes less area whe compared with the multiplier. Reductio i delay because of the use of parallel prefi adder. Table II. Compariso betwee eistig ad proposed butterfly structure Type of model Parameters Butterfly-I Butterfly-II Eistig Model o. of slices Delay s Proposed Model o. of slices 5 0 Delay s Table III. Compariso betwee eistig ad proposed R- SDF FFT Type of model o. of slices Delay s o. of iputs Eistig X6 Proposed X6 From above table it ca be see that proposed FFT is better i terms of area ad delay whe compared with eistig oe. IX. Coclusio A multiplier less pipelied Radi- Sigle Path Delay Feedbac FFT has bee described i this paper. Maily area ad delay are cosidered for performace evaluatio eeded by the SDF FFT. Distributed Arithmetic based comple multiplier has bee used as a proposed model. Cosiderig the symmetric property of twiddle factors i FFT we have desiged a distributed arithmetic based comple multiplier such that the size of twiddle factor is sigificatly shru. A ew approach is proposed i this paper to reduce the area ad delay of SDF FFT. The replacemet of DA based comple multiplier with parallel prefi adder i place of covetioal comple multiplier offers great advatage. This result shows that our desig ows less area as well as less delay as compared to the eistig oe. Of course our proposed architecture ca also be adapted to high-poit FFT applicatios with lower size of twiddle-factor ROM s. Refereces []. Xue LIU Feg YU Ze-e AG A pipelied architecture for ormal I/O order FFT Joural of Computers & Electroics Spriger olie publicatio Vol. o. pp May0 []. K.Haririsha T.Rama Rao ad Vladimir A. Labay A Radi- Pipelie FFT for Ultra ide Bad Techology Iteratioal Coferece o computer & etwor Techology ICCT coferece proceedigs published by orld Scietific Press Sigapore. Cheai Idia July []. Suil P. Joshi Roy Paily Distributed Arithmetic Based Split- Radi FFT Joural of Sigal Processig System Spriger Olie Publicatio May 0 []. Omri ad Bouallegue "ew Trasmissio Scheme for MIMO-OFDM System" Iteratioal Joural of et-geeratio 9 Page

7 Desig of Efficiet Pipelied Radi- Sigle Path Delay Feedbac FFT etwors Vol. o.pp. -9 March 0 [5]. Chag Y A efficiet VLSI architecture for ormal I/O order pipelie FFT desig IEEE Tras. Circ. Syst. II: Ep. Briefs volume 55 o. pp. -8. [6]. Omri ad Bouallegue "ew Trasmissio Scheme for MIMO-OFDM System" Iteratioal Joural of et-geeratio etwors Vol. o.pp. -9 March 0 [7]. Cheg C. Parhi K.K. 007 High-throughput VLSI architecture for FFT computatio IEEE Tras. Circ. Syst. II: Ep. Briefs volume 5 o.0 pp [doi:0.09/tcsii ] [8]. Mia Sijjad Miallah Gulista Raja Real Time FFT Processor Implemetatio IEEE ICET 006Iteratioal Coferece o Emergig Techologies.Peshawar Paista - Pages: 9-95 ovember 006 [9]. isha Laguri K. Ausudha Desig of Delay Efficiet Distributed Arithmetic Based Split Radi FFT Iteratioal Joural of Egieerig Treds ad Techology Volume 5 umber 7 ovember Page