FPGA Implementation of Pipeline Digit-Slicing Multiplier-Less Radix 2 2 DIF SDF Butterfly for Fast Fourier Transform Structure

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1 FPGA Implemetatio of Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly for Fast Fourier Trasform Structure Yaza Samir Algabi,. Rozita Teymourzadeh, Masuri Othma, Md Shabiul Islam Istitute of MicroEgieerig ad aoelectroics IME, VLSI Desig Departmet, Uiversiti Kebagsaa Malaysia, 6 Bagi, Selagor, Malaysia Faculty of Egieerig, Architecture ad Built Eviromet, Electrical & Electroic Egieerig departmet, UCSI Uiversity, Kuala Lumpur, Malaysia yazasamir@yahoo.com, rozita@ucsi.edu.my, masuri.othma@mimos.my, shabiul@um.my Abstract The eed for wireless commuicatio has drive the commuicatio systems to high performace. However, the mai bottleec that affects the commuicatio capability is the Fast Fourier Trasform (FFT), which is the core of most modulators. This paper presets FPGA implemetatio of pipelie digitslicig less radix DIF (Decimatio I Frequecy) SDF (sigle path delay feedbac) butterfly for FFT structure. The approach tae; i order to reduce computatio complexity i butterfly, digitslicig less techique was utilized i the critical path of pipelie Radix DIF SDF FFT structure. The proposed desig focused o the tradeoff betwee the speed ad active silico area for the chip implemetatio. The iput data was sliced ito four blocs each oe with four bits to process at the same time i parallel. The ew architecture was ivestigated ad simulated with MATLAB software. The Verilog HDL code i Xilix ISE eviromet was derived to describe the FFT Butterfly fuctioality ad was dowloaded to Virtex II FPGA board. Cosequetly, the Virtex II FG56 Proto board was used to implemet ad test the desig o the real hardware. As a result, from the fidigs, the sythesis report idicates the maximum cloc frequecy of MHz with the total equivalet gate cout of,6 is a mared ad sigificat improvemet over Radix DIF SDF FFT butterfly. I compariso with the covetioal butterfly architecture desig which ca oly ru at a maximum cloc frequecy of. MHz ad the covetioal ca oly ru at a maximum cloc frequecy of. MHz, the proposed system exhibits better results. It ca be cocluded that ochip implemetatio of pipelie digitslicig less butterfly for FFT structure is a eabler i solvig problems that affect commuicatios capability i FFT ad possesses huge potetials for future related wors ad research areas. Key words Pipelied digitslicig less; Fast Fourier Trasform (FFT); Verilog HDL; Xilix; Radix DIF SDF FFT. I. ITRODUCTIO FFT is sigificat bloc i several digital sigal processig (DSP) applicatios such as biomedical, soar, commuicatio systems, radar, ad image processig. It is a successful algorithm to compute discrete Fourier trasform (DFT). DFT is the mai ad importat procedure i data aalysis, system desig, ad implemetatio []. May modules have bee desiged ad implemeted i differet platforms i order to reduce the complexity computatio of the FFT algorithm. These modules focus o the radix order or twiddle factors to perform a simple ad efficiet algorithm which icludes the higher radix FFT [], the mixedradix FFT [], the primefactor FFT [], the recursive FFT [5], lowmemory referece FFT [6], Multiplierless based FFT [7, ] ad Applicatio Specific Itegrated Circuits (ASIC) system [9, ]. A special class of FFT architecture which ca compute the FFT i a sequetial maer is the pipelie FFT. Pipelied architectures characterized by realtime, o stoppig processig ad preset smaller latecy with low power cosumptio [] which maes them suitable for most DSP applicatios. There are two commo types of the pipelied architectures; sigle path architectures ad multi path architectures. Several differet architectures have bee ivestigated, such as the Radix Multipath Delay Commutator (R MDC) [], Radix SiglePath Delay Feedbac (R SDF) [], Radix Sigle Path Delay Commutator (R SDC) [], ad Radix Sigle Path Delay Feedbac (R SDF) [5]. The study made o the listed architectures shows that the Delay Feedbac architecture is more efficiet tha the other delay commutator i terms of memory utilizatio. Radix has simpler butterfly as Radix ad the same multiplicative complexity as Radix algorithm [6, 7]. This maes Radix sigle path delay feedbac a attractive architecture for DSP implemetatio. The study of the digitslicig techique has bee dealt by [ ] for the digital filters. The desig ad implemetatio of slicig FFT has bee discussed by []. This paper proposed a similar idea with the oes put forth by []; but havig a differece by the use of a differet algorithm, structure ad differet platform, which helps to improve the performace ad achieve higher cloc frequecy. Recetly, Field Programmable Gate Array (FPGA) has become a applicable optio to direct hardware solutio performace i the real time applicatio. I this paper, digitslicig architecture is proposed to desig the pipelie digitslicig less Radix SDF butterfly. The FFT butterfly multiplicatio is the most crucial part i causig the delay i the computatio of the FFT. I view of the fact, the twiddle factors i the FFT processor were ow i advace hece we

2 proposed to use the pipelie digit slicig less butterfly to replace the traditioal butterfly i FFT. II. RADIX SDF FFT ALGORITHM The more efficiet architecture i terms of memory utilizatio is the delay feedbac. radix algorithm based siglepath architectures have higher utilizatio; however, radix algorithm based architectures have simpler butterflies ad cotrol logic. The radix FFT algorithm has the same multiplicative complexity as radix but retais the butterfly structure of radix algorithm [5]. That maes the R SDF FFT algorithm the best choice for the VLSI implemetatio. I this algorithm, the first two steps of the decompositio of radix DIT FFT are aalysed, ad commo factor algorithm is used to illustrate. [ ] X x[ ],,,..., x[] ad ] = Complex umbers j / e = The twiddle factor I the Equatio () the idex ad decomposed as: () The total value of ad is. whe the above substatios are applied to Equatio () the DFT defiitio ca be writte as: ] ( / ) ( / ) here: B x ] B x / ( ) () () x / For ormal radix DIF FFT algorithms, the expressio i the braces is computed first as a first stag i Equatio (5). However, i radix FFT algorithm, the mai idea is to recostruct the first stage ad the secod stage twiddle factors, as show i Equatio () as metioed i [5]. ( ) ( ) (6) (7) () ( ) ( ) ( j) Observe that the last twiddle factor i Equatio () ca be rewritte as: j j e e / By applyig Equatio () ad (9) i Equatio (5) ad expad the summatio over, the result is a DFT defiitio with four times shorter FFT legth. ( / ) here, H[ H[ ] ] x( ) ( ) ( ) ] x (9) () ( ) ( j) x ( ) x Each term i equatio () represets a Radix butterfly (), while the whole equatio represets Radix butterfly, (I) with trivial multiplicatio by (). Equatio () ow as radix SDF FFT algorithm. Fig. shows the butterfly sigal flow graph for radix FFT algorithm. Fig. shows the 6 poit R SDF FFT sigal flow graph. x[] x[/] x[/] x[/] x[] x[] x[] x[] x[] x[5] x[6] x[7] x[] x[9] x[] x[] x[] x[] x[] x[5] Fig. The butterfly structure for the radix DIF FFT Fig. 6Poit R SDF DIF FFT sigal flow graph. III. RADIX SDF BUTTERFLY STRUCTURE () ] /] /] /] ] ] ] ] ] ] 6] ] ] 9] 5] ] ] ] 7] 5] From equatio (), each stage i R SDF FFT cosists of, I, Complex s with twiddle factors. calculate the iput data flow, butterfly II calculate the output data flow from, tha multiply the twiddle factors with the output data from I, to get the result of the curret stage. Fig. shows the structure of 6 poit R SDF FFT. I Twiddle Factor I Fig. 6Poit R SDF DIF FFT Structure.

3 A. Structure Fig. shows the structure, the iput A r, A i for this butterfly comes from the previous compoet which is the twiddle factor except the first stage it comes form the FFT iput data. The output data B r, B i goes to the ext stage which is ormally the I. The cotrol sigal C has two optios C= to multiplexers direct the iput data to the feedbac registers util they filled. The other optio is C= the multiplexers select the output of the adders ad subtracters. The process of the is to store the aterior half of the poit iput series i feedbac registers, tha butterfly calculatio whe the posterior half data is comig, the result of the butterfly is B r, B i, D r, D i. B r, B i fed to the output result of the the other result D r, D i goes to the feedbac registers. B. I Structure Fig. 5 shows the I structure b. The iput data B r, B i comes from the previous compoet,. The output data from the I are E r, E i, F r ad F i. E r, E i fed to the ext compoet, ormally twiddle factor. The F r ad F i go to the feedbac registers. The multiplicatio by j ivolves swappig betwee real part ad imagiary part ad sig iversio. The swappig is hadled by the multiplexers SwapMUX efficietly ad the sig iversio is hadled by switchig betwee the addig ad the subtractig operatios by mea of SwapMUX. The cotrol sigals C ad C will be oe whe there is a eed for multiplicatio by j, therefore the real ad imagiary data will swap ad the addig ad subtractig operatios will switched. I order to ot lose ay precisio the divide by is used where the word legths imply successive growth as the data goes through adder, subtracter ad operatios. Roudig off has bee also applied to reduce the scalig errors. Ar Ai Feedbac reg. Img Feedbac reg. C Fig. The Structure. Dr Di Br Bi Br Bi Swap MUX Feedbac reg. Img Feedbac reg. Fig. 5 The I Structure. C. Complex Multiplier ormally the complex ca be realized by four real s, oe adder ad oe subtractor as show i Fig. 6. This complex structure occupies large chip area i VLSI implemetatio. (a r ja i )(b r jb i )= (a r b r a i b i ) j (a i b r a r b i ) () C C Fr Fi Er Ei ar ai bi br ar br ai bi ar bi ai br Part [ar br][ai bi] Imagiary Part [ar bi][ai br] Fig. 6 Complex with four real structure. This complex ca be realized by oly three real s ad five real adder/ subtractor based o equatio (); this will save a lot of area i hardware implemetatio as show i Fig. 7. (a r ja i )(b r jb i )={b r (a r a i )a i (b r b i )}j{b i (a r a i )a i (b r b i )}() a r b r b i a i ar ai br bi ar ai br[ar ai] bi[ar ai] ai[br bi] Part br[ar ai] ai[br bi] Imagiary Part bi[ar ai] ai[br bi] Fig. 7 Complex with three real structure. IV. FPGA IMPLEMETATIO OF PIPELIE DIGITSLICIG MULTIPLIERLESS RADIX DIF SDF BUTTERFLY Previous sectio explai i details the covetioal structure of the R SDF butterfly, this sectio discuss how to apply the digit slicig techique for the R SDF butterfly compoet i order to reduce the complexity computatio ad ehaced the throughput. The digit slicig less R SDF butterfly has bee used the same compoet of the covetioal structure except the complex which has bee replaced with the digit slicig less. The multiplicatio fuctioality is regarded as the most importat operatio for most sigal processig systems, but it is a complex ad expesive operatio. May techiques have bee itroduced for reducig the size ad improvig the speed of s. I this paper we proposed digit slicig less to improve the speed of the multiplicatio. The desig of the digit slicig complex has bee made by Matlab to prove the worig of the algorithm tha we improved the desig to be the digit slicig less. The cocept behid the digit slicig architecture is ay biary umber ca be sliced ito a few blocs of shorter biary umbers, with each bloc carryig a differet weight []. I this paper, the 6 bits fixedpoit s complemets arithmetic has bee chose to represet the iput data ad the twiddle factor, which are siged umbers with absolute value less tha oe. Let us coceder the absolute value of the complex iput data (the output of I) is x with legth of 6 bits has bee represeted i s complemet as: B x j x j () To represet the sliced data, the fudametal sliced algorithm will be preseted as followig:

4 b p ( pb) x p X j j X X () here x is sliced ito b blocs ad p is bit widths per bloc ad X,j are all either oes or zeros except for X =b, j=p which is zero or mius oe. The digit slicig architecture has bee applied for the complex iput data (the output of I) to slice the data to four groups each carryig four bits as show i Fig. ad Fig. 9., j Figure. Slicig Structure Figure 9. Slicig for the iput E r The complex realized by three real s, as metio i previous sectio the digit slicig has bee applied for the real iput data to mae the multiplicatio process parallel with the 6 bits twiddle factor as show i Fig.. Therefore the processig time will be reduced. To uderstad ad prove the digit slicig algorithm the MATLAB desig for the complex ad the digit slicig has bee made ad the result has bee compared as show i Fig. ad Fig.. 6 bit Iput data E The iput Data for the butterfly 6 bits Slicig Uit 6 bit To bit 6 bits Slicig Uit 6 to 6 bit x Leftshift by Leftshift by Leftshift by Adder E E E E Rightshift by 5 6 bit output Sice the twiddle factors i FFT are ow i advaced therefore the multiplicatio possibility for the 6 bits twiddle factor ad multiply by iput data will be 6 possibilities ca be stored i oe RAM for each twiddle factor. This desig will improve the digit slicig to be digit slicig less which has bee replaced with the covetioal as show i Fig.. Butterfly II Slicig Multiplier less Butterfly II Fig. 6poit R SDF FFT structure with digit slicig The desig of the digit slicig less cosists of oe looup table (ROM) shift ad adder to perform the output as show i Fig. ad Fig. 5. To geerate the looup table data (the multiplicatio result possibilities), which are 6 differet results, a special MATLAB program has bee writte by applyig the digitslicig algorithm for all the possible umbers for the iput data () from to to perform all the possibilities for the multiplicatio result. The storage of all these possibilities i oe ROM allows the desig to perform the multiplicatio process without ay real. 6 bit Iput data Slicig Uit 6 bit To bit ROM For all the possibilities for the multiply The iput ith 6 bit Leftshift by Leftshift by Leftshift by Adder Fig. digit slicig less structure Rightshift by 5 6 bit output 6 bit twiddle factor Fig. digit slicig structure. Fig. Desig of Complex i MATLAB. Fig. Desig of digit slicig Complex i MATLAB. Fig. 5 desig of digit slicig less i MATLAB The Verilog HDL code i Xilix ISE eviromet was derived to describe the Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly fuctioality ad was dowloaded to Virtex II FPGA board. Cosequetly, the VirtexII FG56 Proto board was used to implemet ad test the desig o the real hardware. V. RESULT Two differet modules were implemeted for R SDF DIF FFT butterfly. The first module uses the covetioal architecture for the butterfly where the twiddle factors are stored i ROM ad called by the butterfly to be multiplied with the iputs by utilisig the dedicated high speed equipped with the VirtexII FPGA. The other module uses the pipelied digitslicig less architecture to perform the multiplicatio with

5 the twiddle factor. Both modules were built ad tested i MATLAB as idicated i previous sectio, the coded i Verilog ad sythesized by usig the XSTXilix Sythesis Techology tool. The target FPGA was Xilix VirtexII XCV56FG56 FPGA. The ModelSim simulatio result of Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly is show i Fig. 6, while the sythesis results for the two models are preseted i Table, which demostrates the hardware specificatios for the desig. It idicates the maximum cloc frequecy of MHz for Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly as well as the Pipelied slicig Sigle Multiplierless for the butterfly with a performace of the maximum cloc frequecy of 69.9 MHz. Meawhile, Fig. 7 shows the RTL schematic for the Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly. Fig. 6 ModelSim simulatio result of Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly Fig. 7 RTL schematic for the Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly Table : Hardware specificatios of the digitslicig butterfly Xilix VirtaxII FPGA XCv56FG56 Total equivalet gate cout for desig Maximum Frq. MHz Covetioal butterfly.. Pipelie Slicig MultiplierLess Radix, DIF SDF Butterfly Covetioal 6 bits Multiplier..6 Pipelie Slicig Multiplier Less 6 bits VI. COCLUSIO This study preseted of FPGA Implemetatio of Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly for FFT Structure. The implemetatio has bee coded i Verilog hardware descriptive laguage ad was tested o Xilix VirtexI XCV56 FG56 prototypig FPGA board. A maximum cloc frequecy of MHz has bee obtaied from the sythesis report for the Pipelie Slicig MultiplierLess Radix DIF SDF Butterfly which is. time faster tha the covetioal butterfly. It ca be cocluded that FPGA Implemetatio of Pipelie Slicig Multiplier Less Radix DIF SDF Butterfly for FFT Structure is a eabler i solvig problems that affect commuicatios capability i FFT ad possesses huge potetials for future related wors ad research areas. REFERECES [] A. V. Oppeheim, R.. Schafer, ad J. R. Buc, Discretetime sigal processig, ed. Upper Saddle River,.J.: Pretice Hall, 999. [] G. D. Berglad, "A radixeight fastfourier trasform subroutie for realvalued series.," IEEE Tras. Audio Electroacoust, vol. 7, pp., 969. [] R. C. Sigleto, "A algorithm for computig the mixed radix fast Fourier trasform," Audio ad Electroacoustics, IEEE Trasactios o vol. 7, pp. 9, 969. [] D. P. Kolba ad T.. Pars, "A prime factor FFT algorithm usig highspeed covolutio," IEEE Tras Acoust. Speech, Sigal Process, vol. 5, pp. 9, 977. [5] A. R. VaroyiKoczy, "A recursive Fast Fourier Trasform algorithm," IEEE Tras. Circuits System, vol., pp. 666, 995. [6] Y. ag, Y., Y. J. Tag, J. G. Chug, ad S. S. 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