CAD dependent Estimation of Optimal k-value in FSM onto k-lut FPGA mappings, based on standard benchmark networks

Transcription

1 CAD dependent Estimation of Optimal k-value in FSM onto k-lut FPGA mappings, based on standard benchmark networks DOKOUZYANNIS STAVROS 1 ARZOUMANIDIS EFSEVIOS 2 Aristotle University of Thessaloniki Department of Electrical and Computer Engineering Thessaloniki GREECE Abstract: The problem of k value is a crucial one for k-lut based FPGA architectures. A digital circuit quality mapping onto a k- LUT FPGA, is basically CAD dependable, but to a great degree k value dominates over all of the mapping parameters. Namely area and level of a mapped circuit (network) are strongly dependent on k value. As k increases, the total area of a mapped circuit also increases, while the relative level decreases, leading to a faster circuit. The question is which is the optimum k value, namely the value beyond which the area tradeoff of a mapped circuit (network) is unnecessarily increased for some level gain. This problem has been extensively studied through years and resulted in architectures implemented by most FPGAs manufacturers. For years, optimum values of k are considered between 3 and 5, with k = 4 accepted as being the best choice. Our study is an experimental evaluation of above results in present times, utilizing SIS, MVSIS and ABC, academic CAD systems, from California Berkeley University (UCB). These CAD systems, especially MVSIS and the under development ABC, incorporate state of the art optimization and mapping algorithms, among many other features. We optimized and mapped 20 medium and large scale sequential benchmark networks, for k values from 2 to 6, using all three mentioned CAD systems. In all cases our outcomes verify that k should be again in the range of 3 to 5 for best results, with k=4 being the optimum value. Key-Words: FSM, optimization, LUT-FPGA, k value, mapping, SIS, MVSIS, ABC, FRAIGs 1 Introduction The mapping of complex FSM circuits and networks onto LUT based FPGAs is known to belong to the class of very complex processes. There is almost a decade, since the technological and research communities posses CAD tools, being capable to convert (i.e., to map), a large state machine to a completely designed FPGA device. In an every day digital-design foundry-practice, the FSM circuits, which are necessary to complete a full design, are fastened together to form a bundle of small and large circuits, which are necessary to be packed in one FPGA. These do not follow common design rules for one, even large, State-Output Table model, but are the combination of several design styles, descending from the final design objective; as for example, the large VHDL compiled code together with Excitation-Output State Controller Functions, produced from non VHDL CAD package(s). The class of these extremely large and non-uniformly modeled FSM circuits are called FSM networks. Most FPGAs architectures are based on blocks of Basic Logic Elements (BLE)depicted in Fig.1, [1]. Besides the D-FF, one BLE includes a build-in k- input Look-Up Table (k-lut). The k-lut is the k-input and one output ROM-type memory table, being able to implement any given k-input combinational function with one output (by following a quasi decoder/ multiplexer based design methodology). Fig. 1 Basic Logic Element (BLE) In general, as the k-value increases for a k-lut, there is a more of combinational parts of a design that can be fastened into a k-lut FPGA. So that, fewer levels are necessary to complete a design and the resulted FPGA device can work faster, with higher clock frequencies. On the other hand, however, the increasing of k results in more area, ISSN: Page 49 ISBN:

2 that is in a more hardware necessary to build the FPGA. The trade-off between the amount of the total FPGA hardware and the speed of the implemented design, is through years the basic problem in the digital design technology and research as well [13-18]. The issue of optimum k-value has been studied in the early days of FPGAs [2] [3], when minimization of mapped circuit area defined the first design priority. However presently, as FPGAs become larger and larger (nowadays there are available Xilinx FPGA with 120 thousands D-FFs and an equivalent of 5 million gates in one FPGA chip) and the need for faster and low power circuits increases, different new cost functions are defined and area is no more the first priority in the mapping process. In this paper we present the results of an experimental evaluation of optimum k value, which we carried out by mapping of 20 medium and large scale FSM benchmarks. We selected intentionally this set of benchmark circuit and networks, since these are known to have the ability to cover the most of the practical digital designs. For optimization and mapping we ve used the academic CAD tools developed at Berkeley University, that is SIS[4] package and its successors, MVSIS [5] [6] and ABC [7] [8] packages. 2 The mapping methodology The mapping of a digital circuit (network) onto a k-lut FPGA is basically a two-step procedure, (Fig.2). Regardless of the actual algorithm to be used for mapping, optimum results can only be achieved after circuit s technology independent optimization [3 ] [9] [10 ].Thus, the first step of the mapping process is the optimization of a given circuit (network); we used for this purpose SIS, MVSIS and the newly available ABC software packages. We tried some proposed optimization scripts, for every one of the mentioned packages, but we finally approved the script giving the best results. The second step of the mapping procedure is the application of specific package mapping algorithm to the optimized version of a benchmark. In the following subsections we describe in details the two mentioned steps. We run all CAD packages on a laptop computer with Pentium IV, 3.0 GHz CPU, 512 Mb RAM under Windows XP OS. 2.1 Technology independent optimization Network topology reading Technology independent Optimization (SIS, MVSIS, ABC) Application of mapping Algorithm (SIS, MVSIS,ABC ) Results analysis Fig.2 A two steps procedure for mapping onto k- LUT FPGA For every CAD package we followed exactly the same procedure for optimization; one exception was with ABC package, which uses different scripts for mapping process. We tested various proposed scripts but we found that, for SIS and MVSIS best results are obtained through the use of script.rugged and for ABC through the script resyn2. For the case of MVSIS we had to change slightly the script.rugged to make it compatible with its commands. The procedure used is as follows: (a) Read the circuit in blif format [4]. (b) Invoke the specific script repeatedly, until no further improvement or inferior results are seen. (c) Record the final results in blif format to be used in the next, second step. Apparently, the most critical part of the above procedure is the script used for optimization and the relative cost function. We used a simple cost function in all three cases. Namely in the cases of SIS and MVSIS we used the number of literals in the factorized forms [11], that is the term lits(ff) of circuit s statistics. The optimized circuit is that with the minimum lits(ff) and minimum level, and which was written in blif format and considered as independently optimized with regard to the original one. ISSN: Page 50 ISBN:

3 In the case of ABC package the original circuit is first transformed, by script resyn2, into FRAIG form [12]. It is then optimized, by minimizing the nodes and its description is given in the same form. Therefore our cost function is the number of FRAIG nodes, which we minimized by repeatedly invoking script resyn2, while keeping circuit s level as low as possible. Again the optimized circuit was written in blif format, to be used for the mapping step. 2.2 Mapping step A circuit being mappable onto a k-lut FPGA should be a k-feasible circuit, that is every node should have at most k inputs [2]. Technology independent optimized circuits are not necessarily k-feasible. For every CAD package, we first transformed the optimized circuit to a feasible one for k values from 2 to 6, and then we applied its mapping algorithm to get the mapped circuit (network). We ve considered FPGAs with fine grained architecture, consisting of BLEs, Fig.1. Thus, mapping results, for every k value, are the number of LUTs and the number of levels of the mapped circuit. To simplify the procedure and make the results comparable we did not use any post-processing. The above methodology has two main advantages: (1) It is possible to compare mapping results for some benchmark using SIS, MVSIS or ABC packages. (2) One can detect the impact of k value on the mapping, within a CAD package and between different packages. 3 The results In Table 1 we present the mapping results for the assumed k values, from 2 to 6, for all 20 benchmark FSMs and for every CAD package. The benchmark set comprises medium circuits and large size FSM networks up tp 1,500 FFs and 4,500 4-input LUTs. We give two basic parameters, namely the area and corresponding level for all circuits (networks). Since every k-lut has its own area coefficient, we preferred to present total area for every k, instead of the corresponding LUT number. It can be concluded from Table 1 that SIS gives the best results regarding to the area factor, for all k, but it is worse in level, comparably with the two other CAD packages. This means that mapping with MVSIS or ABC leads to faster circuits, with a Table 1. Total area and level for 20 benchmarks Total for SIS MVSIS ABC Area k= Level k= Area k= Level k= Area k= Level k= Area k= Level k= Area k= Level k= small area offset. On the other hand these two systems give practically equivalent results, slightly better in favor of ABC, which is also much faster, as we found during our experiments. The second conclusion from Table 1 is that all three CAD systems behave similarly as a function of k. Namely as k increases the area a of mapped circuit increases, while the level decreases. Obviously, the optimum value of k is dependent on optimization criteria. Fig.2 is an interesting plot of mean area and mean level for the 20 benchmarks, mapped by MVSIS package. As it is seen, the k=4 is a rather preferred value for the most cases; since for higher values of k the area offset is high in comparison to level gains. To further investigate this issue we plot the mean area and level for 6 medium and comparable sized benchmarks, as a function of k. These benchmark FSMs are: dk16, cse, tbk, ex1, keyb and planet, from MCNC91 suite. As depicted in Fig.3, again k=4 is the preferred value. It can be seen that between k=4 and 5 we have one unit gain in level, while area offset is more than 60%. 4 Conclusion In this paper we estimated experimentally the optimum k value for the case of FSM mapping into k-lut FPGAs. We optimized 20 medium and large benchmark circuits (and networks) from MCNC 91 suite using three Academic optimization and design CAD systems, namely SIS, MVSIS and ABC. The optimized circuits were mapped onto basic k-lut FPGA archi-tecture, for 2 k 6. Despite differences, CAD system s behavior is similar, as far as k values are ISSN: Page 51 ISBN:

4 concerned. The k=4 seems to be the best choice, if a good balance between area and level is the optimization target. This result is true for all three systems and is apparent from the drawn plots of area and level as a function of k. Our results interpret why commercial FPGA architectures mostly use LUTs with 4 inputs in their Configurable Logic Blocks (CLBs). The provided experiments confirm the results of analytical efforts being performed before one de- cade, when the first design issue was the minimization of the area occupied by a design. Nowadays, the understanding that, instead of appearing of new cost criteria for the FPGA mapping optimizations, the keeping of the k-value somewhere around to k=4, provides the formal authority for the best optimum for k-lut FPGA manufacturing, as well as, constitutes the key knowledge base for a fabrication of the present and near future FPGAs. Fig.2 Mapping results with MVSIS package as a function of k Fig.3 Mapping results with MVSIS as a function of k ISSN: Page 52 ISBN:

5 References: [1] Russell G. Tessier, Fast Place and Route Approaches for FPGAs, Ph. D Thesis MIT 1999 [2] Jason Cong - Yuzheng Ding, Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays -Tutorial and Servey Paper,ACM Transactions on Design Auto- Mation of Electronic Systems, Vol.1, No.2, April 1996, Pages [3] S.D.Brown- R.J.Francis-J.Rose-Z.G. Vranesic, Field-Programmable Gate Arrays, Kluver Academic Publishers [4] Ellen M. Sentovich et. al., SIS: A System for Sequential Circuit Synthesis, Electronics Research Laboratory Memorandum No.UCB / ERL M92/41, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA [5] Donald Chai, Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Robert Brayton, MVSIS 2.0 User s Manual, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley CA [6] Donald Chai, Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Robert Brayton, MVSIS 2.0 Programmer s Manual, Department of Electrical Engineering and Computer Sciences,University of California, Berkeley CA [7] ABC: A System for Sequential Synthesis and Verification,Currently under development by Berkeley Logic Synthesis and Verification Group. [8] Quick Look under the Hood of ABC, A Programmer s Manual, September 12, 2005, University of California, Berkeley CA [9] Richard Rudell, Tutorial: Design of a Logic Synthesis System, Synopsys, Inc., 700 E Middlefield Road, Mountain View, California [10] Prashant Sawkar and Donald Thomas, Performance Directed Technology Mapping for Look- Up Table Based FPGAs, Electrical and Computer Engineering Dept., Carnegie- Mellon University-Pittsburgh, PA [11] Wenyi Feng 1, Fred J. Meyer 2, and Fabrizio Lombardi 2, Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping, 1 FPGA Software Core Group, Lucent Technologies,1247 S Cedar Crest Blvd, Allentown PA 18103, 2 Electrical & Computer Engineering, Northeastern University, 360 Huntington, Avenue, Boston MA [12] Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton, FRAIGs: A Unifying Representation for Logic Synthesis and Verification,Department of EECS, University of California, Berkeley [13] Kara K.W. Poon, Steven J.E. Wilton, Andy Yan, A Detailed Power Model for Field Programmable Gate Arrays Proceedings of the IEEE International Conference on Field- Programmable Technology, [14] Fei Li,, Yan Lin, Lei He, Deming Chen, and Jason Cong, Power Modeling and Characteristics of Field Programmable Gate Arrays, Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No.11, November 2005, pp [15] Jason Cong, Yuzheng Ding, On Nominal Delay Minimization in LUT- Based FPGA Technology Mapping, UCLA Computer Science Department, Los Angeles, CA [16] Jason Cong 1, Yuzheng Ding 1, Tong Gao 2, Kuang- Chien Chen 3, LUT - Based FPGA Technology Mapping under Arbitrary Net- Delay Models, 1 Department of Computer Science University of California, Los Angeles, CA 90024, U.S.A., 2 Department of Computer Science University of Illinois, Urbana Champaign, IL 61801, U.S.A., 3 Fujitsu America, Inc.3055 Orchard Drive, San Jose, CA 95134, U.S.A. [17] Hao Li, Wai- Kei Mak, Srinivas Katkoori, Efficient LUT - Based FPGA Technology Mapping for Power Minimization, Department of Computer Science and Engineering University of South Florida, Tampa, FL USA.. [18] [18] Alan Mishchenko,, Satrajit Chatterjee, Robert K. Brayton, Improvements to Technology Mapping for LUT-Based FPGAs, Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No.2, February 2007, pp ISSN: Page 53 ISBN: