FPGA Power and Timing Optimization: Architecture, Process, and CAD

Transcription

1 FPGA Power and Timing Optimization: Architecture, Process, and CAD Chun Zhang, Lerong Cheng, Lingli Wang* and Jiarong Tong Abstract Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process and architecture evaluation and CAD algorithms to optimize power and delay for FPGAs I. INTRODUCTION Since being invented in 984, FPGAs have become one of the most popular implementation media for digital circuits and have grown into two billion US dollars per year industry []. The continuous scaling of silicon-based integration technology enables the ever growing number of transistors on a single chip to implement circuits and systems. For Application Specific tegrated Circuits (ASICs), the same chip can be used only for one circuit or system. This leads to a high NRE cost, measured in over one million US dollars per application for the current leading silicon technology and expected to grow with silicon scaling. On the other hand, programmable logic fabrics such as FPGAs where the same chip can be programmed or re-programmed into a variety of circuits and systems, have a much lower NRE cost and also a much shorter time to market. Therefore, FPGAs have started to gain more and more market shares from ASICs. However, in order to achieve programmability, FPGA pays the penalty with decrease of performance, power, and area. Due to the large number of transistors required for field programmability and the low utilization rate of FPGA resources (typically 6.5% []), there are a 00X energy difference, a 4.X delay difference, and a 40X area difference between FPGA designs and their ASIC counterparts [], [4]. As the process advances to nanometer technologies, power consumption is a crucial design constraint for nano-scale VLSI circuits. The power problem is more significant for FPGAs than ASICs because FPGA has higher power consumptions. There are lots of existing works on optimizing timing and power for FPGAs. this survey, we review the two major types of techniques for FPGA power and delay optimization: ) process and architecture evaluation; ) computer-aided design (CAD) algorithms. This survey is organized as follows: Section II first introduces some preliminaries of FPGAs; then Section III reviews C. Zhang, L. Wang and J. Tong are with State Key Lab of ASIC and System, Fudan University, China. Lerong Cheng is with SanDisk Corporation, CA, USA. *L. Wang is correspondence author, llwang@fudan.edu.cn Memetic Computing Society existing process and architecture evaluation techniques; Section IV presents FPGA CAD algorithms; finally Section V concludes this survey. II. PRELIMINARIES A. Conventional FPGA Architecture The most popular architecture for FPGAs is cluster-based island style FPGA architecture [5]. A cluster-based logic (see Figure ) includes several fully or partially connected Basic Logic Elements (BLEs). Each BLE includes one K- input lookup table (LUT) and one flip-flop (DFF). The logic s are surrounded by routing channels consisting of wire segments. The input and output pins of a logic can be connected to the wire segments in routing channels via a connection (see Figure (b)). A routing switch is located at the intersection of a horizontal channel and a vertical channel. Figure (c) shows a subset switch [6], where the incoming track can be connected to the outgoing tracks with the same track index. The connections in a switch (represented by the dashed lines in Figure (c)) are programmable routing switches. The routing switches can be implemented as bi-directional tri-state buffers (Figure (d)), uni-directional tri-state buffers, or pass-transistors. interconnect segment is a wire segment driven by a tri-state buffer. Usually, the LUTs are referred to as logic circuit elements, interconnect within logic s is referred to as local interconnect, and interconnect outside logic s is referred to as global interconnect. B. FPGA Power and Delay Analysis Framework Power and delay analysis framework is necessary for FPGA power and delay optimization. A popular FPGA timing evaluation tool is the static timing analysis engine in the timing driven Versatile Placement and Routing (VPR) tool [5]. VPR provides the critical path delay report after performing placement and routing for an FPGA. the past decade, there are several research work on power analysis for FPGAs [7] [0]. fpgaeva-lp [0] is one of the most popular frameworks. Figure illustrates the overall analysis for fpgaeva-lp. For a given circuit, SIS [] is used to perform the technology independent logic optimization and use Flowmap [] in RASP [] to conduct the technologymapping. Then physical design in VPR [5], including timingdriven packing, placement and routing is performed to generate the BC-netlist (Basic Circuit Netlist) back-annotated with post-layout resistance and capacitance. With the BC-netlist, cycle accurate power simulation is performed to estimate the chip level power. ICCP 00 Proceedings

2 connection 0 0 switch (a) Island style routing architecte 0 B 0 A C 0 D 0 (c) connection switch logic connection (b) Connection and connection switch A (d) Routing switches Fig. : (a) Island style routing architecture; (b) Connection ; (c) ; (d) Routing switches. B circuit elements. A new type of routing multiplexer and an input control method were developed [6] to reduce leakage of unused routing multiplexers, and a circuitry combining gate biasing, body biasing and multi-threshold techniques was designed [7] to reduce interconnect leakage. Besides leakage power reduction, dynamic power reduction is also studied. A dual-vdd FPGA architecture was studied in [8], [8] []. The dual-vdd FPGA circuits are shown in Figure and 4. these circuits, two transistors are placed between supply voltage and circuit elements to choose Vdd level. dual-vdd FPGA, most non-critical path elements are assigned low Vdd to save dynamic power. Moreover, for the low Vdd circuit elements to drive high Vdd circuit, level shifter (LS) is needed. Moreover, [] introduced dual-vdd circuit without level converters, which further reduces power and area introduced by level converters. Notice that here, dual- Vdd circuits can achieve not only Vdd selection but also power gating. Figure 5 [] compares power consumption of different FPGA circuits. It can be seen that dual-vdd technique significantly reduces FPGA power consumption. Circuit logic Logic optimization (SIS) Technology Mapping (RASP) M LC i i0 MUX M BUFF M4 M Vdd Programmable connection switch connection Arch Spec. Mapped Netlist Timing driven packing (T VPACK), placement and routing (VPR) Routing with W =. Wmin (VPR) (a) Configurable level conversion (b) Vdd programmable routing switch (c) Vdd programmable connection Fig. : (a) Configurable level shifter; (b) Vdd-programmable routing switch; (c) Vdd-programmable connection. ( stands for AM cell and LC stands for level shifter.) VPR BCG Delay/capacitance extraction and back annotation BC netlist _En _En Pass_En Logic Power estimation Fig. : FPGA power analysis framework. III. PROCESS AND ARCHITECTURE EVALUATION A. Low Power FPGA Circuits Due to the low utilization rate, the leakage power consumption is significant for FPGAs than that for ASICs. As a result, the problem of leakage power reduction was first studied in the literature. Region based power gating for FPGA logic s [4] and fine-grained power-gating (PG) for FPGA interconnects [5] were proposed. power-gating circuits, a gating transistor is placed between power supply and circuit elements to shut down the power supply for the unused (a) Vdd Programmable switch _En _En Pass_En (b) AM efficient Vdd programmable routing switch log N AM cells Connection es Vdd_Sel Decoder Dec_Disable _En Pass_En _En (c) AM efficientvdd programmable connection Fig. 4: (a) Vdd-programmable switch; (b) AM-efficient Vdd-programmable routing switch; (c) AM-efficient Vddprogrammable connection. d dn _En _En Pass_En N switches Wire tracks

3 Total FPGA Energy/Cycle (nj) % 4.6%.6% 9.5% 58.6%.7%.56% 4.00%.90% 9.78% 56.7%.9% Logic Leakage Logic Dynamic Local terconnect Leakage Local terconnect Dynamic Global terconnect Leakage Global terconnect Dynamic 6.4% 6.8% 5.0% 5.46% 7.68% 59.4% S -Vdd D-Vdd w/ LC S -Vdd w/ PG D-Vdd w/o LC 7.6% 7.% 5.76% 7.85% 9.66% Fig. 5: Energy breakdown for different FPGA circuits. 5.4% Arch Spec Logic Optimization(SIS) Tech-Mapping (RASP) Timing-Driven Packing (TV-Pack) Placement & Routing (VPR) Area Benchmark Delay Parasitic Extraction Cycle-accurate Power Simulator (Psim) Power Fig. 6: Existing FPGA architecture evaluation flow for a given device setting. B. Architecture Evaluation Besides, circuit level, FPGA architecture, including LUT size, logic size, interconnect wire segment length, switch box type, has great impact on power, delay, and area. Architecture evaluation has been performed first for area and delay. For non-clustered FPGAs, it was shown that an LUT size of 4 achieves the smallest area [] and an LUT size of 5 or 6 leads to the best performance [4]. Later on, the cluster-based island style FPGA was studied to optimize area-delay product and it showed that LUT sizes ranging from 4 to 6 and cluster sizes between 4 and 0 can produce the best area-delay product [5]. Besides area and delay, FPGA architecture evaluation considering energy was studied recently [7] [0]. An FPGA architecture evaluation flow considering area, delay, and power was introduced in [0], as shown in Figure 6. For a given benchmark set, logic was optimized and circuit was mapped to a given LUT size. Then time driven packing (TV-Pack) is used to pack the mapped circuit to a given cluster size. After packing, VPR is used to place and route the circuit. Finally, cycle-accurate power simulator [7] is used to estimate the chip level power consumption. People may apply the above flow for different FPGA architectures to obtain the timing and power. Then the optimum architecture can be chosen by evaluating the timing and power values. [6] further evaluated FPGA architectures with field programmable dual-vdd and power gating, and considering area, delay, and energy. It was shown that in 0.5µm technology, an LUT size of consumes the smallest energy [9]. 00nm technology, an LUT size of 4 consumes the smallest energy [0]. C. Process and Architecture Co-Optimization Compared to architecture and circuit design, process parameters, such as Vdd, gate channel length, dopant density, have much higher impact on circuit power and performance. To further reduce power and delay, process and architecture cooptimization is studied [7] [9]. Combining architecture and process, there are more than six parameters to be evaluated, which leads to huge amount of combinations. this case, the architecture evaluation flow discussed above is too slow to perform such evaluation. [7] [9] present a timing efficient power and delay evaluation flow called Ptrace. The basic idea is to perform traditional architecture evaluation flow (as in Figure 6) under one set of process parameters to generate the trace information and reused the trace information for other process parameters to save the simulation time. The Ptrace is shown in Figure 7. It is shown that for 65nm technology, applying architecture and process co-optimization reduces energy delay product by 55%. put Transistor Model Trace PTrace Fig. 7: Trace-based estimation flow. IV. CAD ALGORITHMS A. Deterministic CAD Algorithms put Chip Level Process Variation Reliability Compared to ASICs, the programmability of FPGAs offers a unique opportunity to perform post-silicon design optimization. Low power and high performance CAD algorithms for FPGAs have been studied for a decade. By nature, the dynamic power consumption is defined by equation (), where f is the circuit frequency, Vdd is the circuit working voltage, and C i is the load capacitance of circuit

4 4 node i. The transition density, E i, defines the frequency signal switching (either from high to low or from low to high) of each node. It is easy to observe that by reducing E i, the total power consumption can be reduced. P dyn = fv dd n i= C i E i () The interaction of a suit of power-aware FPGA CAD algorithms without changing the existing FPGAs was studied in [0]. Based on that fact that inter-clb/lut interconnects have much larger capacitance than intra-clb/lut resources, this work aims at absorbing those high transition density nodes into same CLB/LUT in different CAD tasks like technology mapping, placement, etc. that case, they re associated with lower capacitance value and lead to reduction in power consumption. Take the placement problem as an example. The original timing driven placement algorithm incorporates both wiring cost and timing cost into consideration, which are defined by equation () and (). Timing Cost = N nets Wiring Cost = i, j circuit i= q(i) [bb x (i) + bb y (i)] () Delay(i, j) Criticality(i, j) CE () The wiring cost is included to punish the appearance of long nets (i.e., nets with large bounding box), while the timing cost helps placing timing criticality components nearby to enhance the circuit performance. To make the placer power aware, a third cost component, the power cost, is also as well introduced. Equation (4) formulates the power cost function. By multiplying the bounding box and its transition density for each net, it estimates the power consumption of different nets. N nets Power Cost = i= q(i) [bb x (i) + bb y (i)] D i (4) Finally, all three cost components are incorporated into the overall placement cost function, which is given by equation (5). TimingCost Cost = α PreviousTimingCost WiringCost +β (5) PreviousWiringCost PowerCost +( α β) PreviousPowerCost The coefficients α and β adjust the importance of each cost component, thus making the trade-off among area, performance and power consumption of the final placement result. Following the same idea of reducing C i E i, similar power cost is added to technology mapping and routing algorithms as well. Later on, A configuration inversion method to reduce the leakage power of multiplexers without any additional hardware [] was investigated. As low power FPGA circuits, such as power gating, body bias and dual-vdd are introduced, there are more flexibility for CAD algorithms to reduce power and delay. Power-driven partition algorithm for mapping applications to FPGAs with different Vdd-levels [] was proposed. [0], [] propose linear programming based Vdd assignment algorithms to save power. B. Statistical CAD Algorithms As technology scales down, process variation becomes more and more significant. To handle process variation, statistical CAD algorithms are presented: [] presents a statistical FPGA placement algorithm to improve timing yield. [4] proposes a physical synthesis flow to consider both process variation and pre-routing interconnect uncertainty. [5] introduces a statistical dual-vdd assignment algorithm to improve both timing and leakage yield. Leveraging the programmability of FPGAs, [6] provides a chipwise placement flow to improve FPGA performance, as shown in Figure 8. The basic idea of this flow is to perform different placement for different chips according to the chips variation information. For a given set of FPGA chips, a set of sample chips are tested to characterize process variation. Based on such information, the potential delay improvement of chipwise placement is estimated. If the improvement is large, it is worthwhile to perform placement for each chip. this case, the variation map for each chip is generated by synthesizing test circuits for each chip. On the other hand, when the improvement is not significant, the conventional design flow, which uses the same placement and route for all chips, will be applied. It is shown that chipwise FPGA placement improves circuit performance by up to.%. Fig. 8: Design flow of variation aware chipwise placement. V. CONCLUSION This survey has reviewed the existing research works on optimizing process, architecture, and CAD algorithms to reduce power and improve performance for FPGAs. Although the optimization techniques have improved dramatically in the past decade, as CMOS technology level scales down, the fundamental questions, such as power, performance, variation, and reliability become more and more significant. It requires further studies to solve these problems.

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