Technology Dependent Logic Optimization Prof. Kurt Keutzer EECS University of California Berkeley, CA Thanks to S. Devadas
|
|
|
- Noah Goodman
- 5 years ago
- Views:
Transcription
1 Technology Dependent Logic Optimization Prof. Kurt Keutzer EECS University of California Berkeley, CA Thanks to S. Devadas 1 RTL Design Flow HDL RTL Synthesis Manual Design Module Generators Library netlist logic optimization a b 0 1 s d clk q netlist a b 0 1 d q physical design layout s clk Kurt Keutzer 1
2 Logic Optimization netlist a b 0 1 s d clk q Perform a variety of transformations and optimizations Library logic optimization netlist a b 0 1 s d clk q Structural graph transformations Boolean transformations Mapping into a physical library smaller, faster less power Kurt Keutzer 3 Combinational Logic Optimization Input: Output: Initial Boolean network Timing characterization for the module - input arrival times and drive factors - output loading factors Optimization goals - output required times Target library description Minimum-area net-list of library gates which meets timing constraints A very difficult optimization problem! Kurt Keutzer 4
3 Modern Approach to Logic Optimization Divide logic optimization into two subproblems: Technology-independent optimization - determine overall logic structure - estimate costs (mostly) independent of technology - simplified cost modeling Technology-dependent optimization (technology mapping) - binding onto the gates in the library - detailed technology-specific cost model Orchestration of various optimization/transformation techniques for each subproblem Kurt Keutzer 5 Logic Optimization -level Logic opt netlist Library logic optimization tech independent tech dependent multilevel Logic opt netlist Library Timing Constraints Kurt Keutzer 6 3
4 Closed Book Technology Library A standard cell technology or library may contain many hundreds of cells Typical cells are NAND, NOR, NOT, AOI (ANDor-Invert), OAI (Or-And-Invert) etc. A B A A C A A C AB+C B Kurt Keutzer 7 Library Contains for each cell: Functional information: cell = a *b * c Timing information: function of input slew intrinsic delay output capacitance non-linear models used in tabular approach Physical footprint (area) Power characteristics Wire-load models - function of Library Block size Wiring Kurt Keutzer 8 4
5 Elements of a library - 1 Element/Area Cost INVERTER NAND 3 NAND3 4 NAND4 5 Kurt Keutzer 9 Elements of a library - AOI1 4 Element/Area Cost AOI 5 Kurt Keutzer 10 5
6 Reasonable Library Inverter, Buffer ND-ND4; NOR-NOR4; AND- AND4; AOI1 - AOI333; OAI1 - OAI333 XOR, XNOR MUX, Full Adder Neg-Edge Triggered D-Flip-Flop Pos-Edge Triggered D-FF J-K FF Above with various clears, enables Scan versions of each of the above Most of the above in 6 different power sizes: 1x, x, 4x, 6x, 8x, 16x Kurt Keutzer 11 Input Circuit Netlist ``subject DAG Kurt Keutzer 1 6
7 Problem statement Find an ``optimal (in area, delay, power) mapping of a circuit into the technology library (simple example below): Kurt Keutzer 13 Is there a problem? Trivial Covering #1 subject DAG 7 NAND (3) = 1 5 INV () = 10 Area cost 31 Kurt Keutzer 14 7
8 Covering # INV = 4 NAND = 6 1 NAND3 = 4 1 NAND4 = 5 Area cost 19 Kurt Keutzer 15 Covering #3 Costs: 31, 19, 17 Yes, there s a problem! 1 INV = 1 NAND = 3 NAND3 = 8 1 AOI1 = 4 Area Cost 17 Kurt Keutzer 16 8
9 History of the Problem - 1 Technology mapping in 1986 was a big problem Almost every design group (e.g. AT&T) had their own library ASIC 400 cells Microprocessor/DSP 00 base cells Government 00+ cells Every group had their own approach to mapping ``Do what you have to do! handcrafted mappers tied to particular libraries and optimization tools ``Rule-based systems e.g. GE Socrates very slow ``expert systems that made no guarantee on final quality of result Kurt Keutzer 17 History of the Problem - Yes, there are two problems: Technology mapping can significant affect the area, speed, and power dissipation of a circuit There are over 00 different semiconductors each with multiple internal libraries how to create a tool that can utilize a diverse set of libraries?? Kurt Keutzer 18 9
10 A similar problem code generation Example of code generation in compilers using tree-covering Handles complex instruction sets Handles complex libraries Easily portable to other instruction sets Easily portable to Kurt Keutzer 19 Problem Formulation: DAG Covering Represent input netlist in normal form subject DAG Represent each library gate with normal forms for the logic function primitive DAGs Each primitive DAG has a cost Goal: Find a minimum cost covering of the subject DAG by the primitive DAGs Normal form: -input NAND gates and inverters K. Keutzer, DAGON: Technology Binding and Local Optimization by DAG Matching, in Proceedings of the 4th Design Automation Conference, 1987 and 5 Years of Design Automation Kurt Keutzer 0 10
11 Step 1: Extract Combinational Logic B Flip-flops inputs Combinational Logic outputs Since FF s don t need to be optimized with surrounding combinational logic we can partition them out Kurt Keutzer 1 Step : Normalize Circuit Netlist ``subject DAG Reduce the netlist into ND gates Kurt Keutzer 11
12 Step 3a: Normalize library Element/Area Cost Tree Representation (normal form) INVERTER NAND 3 NAND3 4 NAND4 5 Kurt Keutzer 3 Step 3b: Normalize library Element/Area Cost Tree Representation (normal form) AOI1 4 AOI 5 Kurt Keutzer 4 1
13 Step 4: DAG Covering Sound Algorithmic approach NP-hard optimization problem K. Keutzer, D. Richards, Computation Complexity of Logic Synthesis and Optimization, in Proceedings of the International Workshop on Logic Synthesis, 1989 multiple fanout Tree covering heuristic: If subject and primitive DAGs are trees, efficient algorithm can find optimum cover dynamic programming formulation Kurt Keutzer 5 Solution formulation 1) Partition input netlist into forest of trees ) Solve each tree optimally using tree covering 3) Stitch trees back together Kurt Keutzer 6 13
14 Resulting Trees Break at multiple fanout points Kurt Keutzer 7 For each tree - Dynamic Programming Principle of optimality: Optimal cover for a tree consists of a best match at the root of the tree plus the optimal cover for the sub-trees starting at each input of the match K. Keutzer, DAGON: Technology Binding and Local Optimization by DAG Matching, in Proceedings of the 4th Design Automation Conference, 1987 y x Kurt Keutzer 8 p z Best cover for this match uses best covers for p, z Best cover for this match uses best covers for x, y, z Choose least cost tree-cover at root 14
15 Example of Optimal Tree Covering INV 11 + = 13 AOI = 7 NAND = 11 INV NAND = 6 NAND 3 NAND 3 Kurt Keutzer 9 DAG covering in detail 1) partition DAG into a forest of trees ) normalize netlist 3) optimally cover each tree a) generate all candidate matches b) find the optimal match using dynamic programming Kurt Keutzer 30 15
16 Partition DAG into Forest of trees Each gate with fanout >1 becomes root of a new tree Kurt Keutzer 31 Normalize netlist Re-express netlist into -input Nand gates and Inverters Make each tree left-oriented Kurt Keutzer 3 16
17 Generate candidate matches - 1 subject tree At the end of this segment each gate in the subject tree is annotated with every possible library cell that could be rooted at that gate What are some ways we can generate matches? Kurt Keutzer 33 Generating candidate matches - Naïve approach - try to match each cell in the library with each node of the tree (libraries can be large! - beware of large constants!!) Better approach build tables such that only potential candidate matches are checked Best approach fancy string matching - pp Introduction to Algorithms, T. Cormen, C. Lesierson, R. Rivest, The MIT Press, Second Printing, pp What s the complexity of each approach? Kurt Keutzer 34 17
18 Optimal tree covering ``subject tree Kurt Keutzer 35 Optimal tree covering ``subject tree Kurt Keutzer 36 18
19 Optimal tree covering ``subject tree Cover with ND or ND3? 1 NAND 3 + subtree 5 Area cost 8 1 NAND3 = 4 Kurt Keutzer 37 Optimal tree covering 3b ``subject tree Label the root of the sub-tree with optimal match and cost Kurt Keutzer 38 19
20 Optimal tree covering 4a 3 Cover with INV or AO1? ``subject tree 1 Inverter + subtree 13 Area cost 15 1 AO1 4 + subtree subtree Area cost 9 Kurt Keutzer 39 Optimal tree covering 4b ``subject tree Label the root of the sub-tree with optimal match and cost Kurt Keutzer 40 0
21 Optimal tree covering Cover with ND or ND3? 8 4 ``subject tree NAND subtree 1 9 subtree 4 1 NAND 3 Area cost 16 subtree 1 8 subtree subtree NAND3 4 Area cost 18 NAND3 Kurt Keutzer 41 Optimal tree covering 5b ``subject tree Label the root of the sub-tree with optimal match and cost Kurt Keutzer 4 1
22 Optimal tree covering - 6 Cover with INV or AOI1? ``subject tree INV subtree INV AOI1 subtree 1 13 subtree 5 1 AOI1 4 Area cost 18 Area cost Kurt Keutzer 43 Optimal tree covering 6b ``subject tree Label the root of the sub-tree with optimal match and cost Kurt Keutzer 44
23 Optimal tree covering - 7 Cover with ND or ND3 or ND4? ``subject tree Kurt Keutzer 45 Cover 1 - NAND Cover with ND? ``subject tree subtree 1 18 subtree 0 1 NAND 3 Area cost 1 Kurt Keutzer 46 3
24 Cover - NAND3 Cover with ND3? 9 4 ``subject tree subtree 1 9 subtree 4 subtree NAND3 4 Area cost 17 Kurt Keutzer 47 Cover - 3 Cover with ND4? 8 4 ``subject tree subtree 1 8 subtree subtree 3 4 subtree NAND4 5 Area cost 19 Kurt Keutzer 48 4
25 Optimal Cover was Cover ND AOI1 Cover with ND3? ND3 INV ND3 ``subject tree Clear that greedy doesn t work well What s the complexity? INV ND 3 ND3 8 AOI1 4 Area cost 17 Kurt Keutzer 49 Computational Complexity To determine the optimal cover for a tree we only need to consider a best cost match at the root of the tree This is constant-time in the number of matched cells Plus the optimal cover for the sub-trees starting at each input of the match This is constant-time in the indegree/fan-in of each match What s the complexity? O(n) - amazing! y x Kurt Keutzer 50 p z Best cover for this match uses best covers for p, z Best cover for this match uses best covers for x, y, z Choose least cost tree-cover at root 5
26 Enhancements to DAG covering Many enhancements incorporated over the last decade Timing optimization incorporating load-dependent delays Rudell - UCB Optimization for low power Application to FPGAs J. Rose - Chortle J. Cong - Flowmap Optimal direct DAG covering without tree covering approximation (didn t net much) Kurt Keutzer 51 Summary of Technology Mapping DAG covering formulation Separated library issues from mapping algorithm Heuristics based on tree covering for area and delay surprisingly efficient final result - for technology/library dependent reasons Very efficient linear time Very flexible approach applicable to wide range of libraries (standard cell, gate array) and technologies (FPGAS) Best enhancement is integration of technology decomposition Also requires ``follow up rule based approaches for best final circuit efficiency Kurt Keutzer 5 6
27 Why does this approximation work well? Each gate with fanout >1 becomes root of a new tree Kurt Keutzer 53 Why does this approximation work well? Few non-tree cells XOR, MUX one-level deep Kurt Keutzer 54 7
28 Why does this approximation work well? Non-tree matching usually requires duplication rarely a benefit for area Kurt Keutzer 55 Kurt Keutzer 56 8
29 Retrospective DAG covering by tree-covering is effective for four reasons separates library definition and characterization from mapping algorithm Duplication of logic not a win in terms of area optimization. Advantage of duplication of logic for timing is very (physical) context dependent provided an efficient mapping in what appears to be a relatively flat solution space Very computationally efficient so suitable to VLSI scale (millions of gates) netlist Principal weaknesses Problems handling multiplexor-trees, full-adders, other DAG patterns Problems in performing performance optimization tricks in tight pipelined logic Kurt Keutzer 57 Extra Slides Kurt Keutzer 58 9
30 Typical library costs Kurt Keutzer 59 But what if? Kurt Keutzer 60 30
31 Strong (or Boolean) Division Given a function f to be strong divided by g Add an extra input to f corresponding to g, namely G and obtain function h as follows h DC = G g + G g h ON = f ON h DC h OFF = f ON + h DC Minimize h using two-level minimizer Kurt Keutzer 61 Typical library costs Kurt Keutzer 6 31
32 But what if? Kurt Keutzer 63 3
CSE241 VLSI Digital Circuits UC San Diego
CSE241 VLSI Digital Circuits UC San Diego Winter 2003 Lecture 05: Logic Synthesis Cho Moon Cadence Design Systems January 21, 2003 CSE241 L5 Synthesis.1 Kahng & Cichy, UCSD 2003 Outline Introduction Two-level
ECE260B CSE241A Winter Logic Synthesis
ECE260B CSE241A Winter 2007 Logic Synthesis Website: /courses/ece260b-w07 ECE 260B CSE 241A Static Timing Analysis 1 Slides courtesy of Dr. Cho Moon Introduction Why logic synthesis? Ubiquitous used almost
L2: Design Representations
CS250 VLSI Systems Design L2: Design Representations John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) Engineering Challenge Application Gap usually too large to bridge in one step,
ECE260B CSE241A Winter Logic Synthesis
ECE260B CSE241A Winter 2005 Logic Synthesis Website: / courses/ ece260bw05 ECE 260B CSE 241A Static Timing Analysis 1 Slides courtesy of Dr. Cho Moon Introduction Why logic synthesis? Ubiquitous used almost
ECE 3060 VLSI and Advanced Digital Design
ECE 3060 VLSI and Advanced Digital Design Lecture 16 Technology Mapping/Library Binding Outline Modeling and problem analysis Rule-based systems for library binding Algorithms for library binding structural
VLSI CAD Flow: Logic Synthesis, Placement and Routing Lecture 5. Guest Lecture by Srini Devadas
VLSI CAD Flow: Logic Synthesis, Placement and Routing 6.375 Lecture 5 Guest Lecture by Srini Devadas 1 RTL Design Flow HDL RTL Synthesis manual design Library/ module generators netlist logic optimization
TECHNOLOGY MAPPING FOR THE ATMEL FPGA CIRCUITS
TECHNOLOGY MAPPING FOR THE ATMEL FPGA CIRCUITS Zoltan Baruch E-mail: Zoltan.Baruch@cs.utcluj.ro Octavian Creţ E-mail: Octavian.Cret@cs.utcluj.ro Kalman Pusztai E-mail: Kalman.Pusztai@cs.utcluj.ro Computer
1/28/2013. Synthesis. The Y-diagram Revisited. Structural Behavioral. More abstract designs Physical. CAD for VLSI 2
Synthesis The Y-diagram Revisited Structural Behavioral More abstract designs Physical CAD for VLSI 2 1 Structural Synthesis Behavioral Physical CAD for VLSI 3 Structural Processor Memory Bus Behavioral
Don t expect to be able to write and debug your code during the lab session.
EECS150 Spring 2002 Lab 4 Verilog Simulation Mapping UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping
Delay Estimation for Technology Independent Synthesis
Delay Estimation for Technology Independent Synthesis Yutaka TAMIYA FUJITSU LABORATORIES LTD. 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, JAPAN, 211-88 Tel: +81-44-754-2663 Fax: +81-44-754-2664 E-mail:
ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms
ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745 RTL to
Overview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
IMPLEMENTATION DESIGN FLOW
IMPLEMENTATION DESIGN FLOW Hà Minh Trần Hạnh Nguyễn Duy Thái Course: Reconfigurable Computing Outline Over view Integra tion Node manipulation LUT-based mapping Design flow Design entry Functional simulation
Lab 3 Verilog Simulation Mapping
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences 1. Motivation Lab 3 Verilog Simulation Mapping In this lab you will learn how to use
COE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
Advances In Industrial Logic Synthesis
Advances In Industrial Logic Synthesis Luca Amarù, Patrick Vuillod, Jiong Luo Design Group, Synopsys Inc., Sunnyvale, California, USA Design Group, Synopsys, Grenoble, FR Logic Synthesis Y
ESE535: Electronic Design Automation. Today. LUT Mapping. Simplifying Structure. Preclass: Cover in 4-LUT? Preclass: Cover in 4-LUT?
ESE55: Electronic Design Automation Day 7: February, 0 Clustering (LUT Mapping, Delay) Today How do we map to LUTs What happens when IO dominates Delay dominates Lessons for non-luts for delay-oriented
Overview. Design flow. Principles of logic synthesis. Logic Synthesis with the common tools. Conclusions
Logic Synthesis Overview Design flow Principles of logic synthesis Logic Synthesis with the common tools Conclusions 2 System Design Flow Electronic System Level (ESL) flow System C TLM, Verification,
Synthesis. Other key files. Standard cell (NAND, NOR, Flip-Flop, etc.) FPGA CLB
SYNTHESIS Synthesis Involves synthesizing a gate netlist from verilog source code We use Design Compiler (DC) by Synopsys which is the most popular synthesis tool used in industry Target library examples:
Unit 4: Formal Verification
Course contents Unit 4: Formal Verification Logic synthesis basics Binary-decision diagram (BDD) Verification Logic optimization Technology mapping Readings Chapter 11 Unit 4 1 Logic Synthesis & Verification
Field Programmable Gate Arrays
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays Robert J. Francis, Jonathan Rose, Kevin Chung Department of Electrical Engineering, University of Toronto, Ontario,
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
What is Verilog HDL? Lecture 1: Verilog HDL Introduction. Basic Design Methodology. What is VHDL? Requirements
What is Verilog HDL? Lecture 1: Verilog HDL Introduction Verilog Hardware Description Language(HDL)? A high-level computer language can model, represent and simulate digital design Hardware concurrency
Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Electronic Design Automation Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No #1 Introduction So electronic design automation,
Programmable Logic Devices II
São José February 2015 Prof. Hoeller, Prof. Moecke (http://www.sj.ifsc.edu.br) 1 / 28 Lecture 01: Complexity Management and the Design of Complex Digital Systems Prof. Arliones Hoeller arliones.hoeller@ifsc.edu.br
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
ECE 4514 Digital Design II. Spring Lecture 20: Timing Analysis and Timed Simulation
ECE 4514 Digital Design II Lecture 20: Timing Analysis and Timed Simulation A Tools/Methods Lecture Topics Static and Dynamic Timing Analysis Static Timing Analysis Delay Model Path Delay False Paths Timing
ECE 565: VLSI CAD Flow + Brief Intro to HLS, Logic Optimization & Technology Mapping. Shantanu Dutt ECE Dept., UIC
ECE 565: VLSI CAD Flow + Brief Intro to HLS, Logic Optimization & Technology Mapping Shantanu Dutt ECE Dept., UIC (High-Level Synthesis or HLS network of interconnected modules: functional units [FUs],
Exploring Logic Block Granularity for Regular Fabrics
1530-1591/04 $20.00 (c) 2004 IEEE Exploring Logic Block Granularity for Regular Fabrics A. Koorapaty, V. Kheterpal, P. Gopalakrishnan, M. Fu, L. Pileggi {aneeshk, vkheterp, pgopalak, mfu, pileggi}@ece.cmu.edu
problem maximum score 1 10pts 2 8pts 3 10pts 4 12pts 5 7pts 6 7pts 7 7pts 8 17pts 9 22pts total 100pts
University of California at Berkeley College of Engineering epartment of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 2/21/03 Exam I Solutions Name: I number: This is a
Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
CS137: Electronic Design Automation
CS137: Electronic Design Automation Day 4: January 16, 2002 Clustering (LUT Mapping, Delay) Today How do we map to LUTs? What happens when delay dominates? Lessons for non-luts for delay-oriented partitioning
3. Implementing Logic in CMOS
3. Implementing Logic in CMOS 3. Implementing Logic in CMOS Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 27 September, 27 ECE Department,
PushPull: Short Path Padding for Timing Error Resilient Circuits YU-MING YANG IRIS HUI-RU JIANG SUNG-TING HO. IRIS Lab National Chiao Tung University
PushPull: Short Path Padding for Timing Error Resilient Circuits YU-MING YANG IRIS HUI-RU JIANG SUNG-TING HO IRIS Lab National Chiao Tung University Outline Introduction Problem Formulation Algorithm -
BUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
ICS 252 Introduction to Computer Design
ICS 252 Introduction to Computer Design Logic Optimization Eli Bozorgzadeh Computer Science Department-UCI Hardware compilation flow HDL RTL Synthesis netlist Logic synthesis library netlist Physical design
Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur.
Digital VLSI Testing Prof. Santanu Chattopadhyay Department of Electronics and EC Engineering India Institute of Technology, Kharagpur Lecture 05 DFT Next we will look into the topic design for testability,
CAD for VLSI Design - I. Lecture 21 V. Kamakoti and Shankar Balachandran
CAD for VLSI Design - I Lecture 21 V. Kamakoti and Shankar Balachandran Overview of this Lecture Understanding the process of Logic synthesis Logic Synthesis of HDL constructs Logic Synthesis What is this?
CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
Linking Layout to Logic Synthesis: A Unification-Based Approach
Linking Layout to Logic Synthesis: A Unification-Based Approach Massoud Pedram Department of EE-Systems University of Southern California Los Angeles, CA February 1998 Outline Introduction Technology and
Review. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/4-04. Seq. Circuit Behavior. Outline.
Review EECS 150 - Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 94-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow
More Course Information
More Course Information Labs and lectures are both important Labs: cover more on hands-on design/tool/flow issues Lectures: important in terms of basic concepts and fundamentals Do well in labs Do well
HIGH-LEVEL SYNTHESIS
HIGH-LEVEL SYNTHESIS Page 1 HIGH-LEVEL SYNTHESIS High-level synthesis: the automatic addition of structural information to a design described by an algorithm. BEHAVIORAL D. STRUCTURAL D. Systems Algorithms
Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design
Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is
EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 18 Implementation Methods The Design Productivity Challenge Logic Transistors per Chip (K) 10,000,000.10m
Spiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
EECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but
problem maximum score 1 8pts 2 6pts 3 10pts 4 15pts 5 12pts 6 10pts 7 24pts 8 16pts 9 19pts Total 120pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 3/31/09 Name: ID number: Midterm Exam This is a closed-book,
Chapter 1 Overview of Digital Systems Design
Chapter 1 Overview of Digital Systems Design SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 8, 2017 Why Digital Design? Many times, microcontrollers
TSEA44 - Design for FPGAs
2015-11-24 Now for something else... Adapting designs to FPGAs Why? Clock frequency Area Power Target FPGA architecture: Xilinx FPGAs with 4 input LUTs (such as Virtex-II) Determining the maximum frequency
Optimal Latch Mapping and Retiming within a Tree
Optimal Latch Mapping and Retiming within a Tree Joel rodstein, ric Lehman, eather arkness, erve Touati, and Bill rundmann Digital quipment Corporation, udson, M bstract. We propose a technology mapping
PINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
Eliminating Routing Congestion Issues with Logic Synthesis
Eliminating Routing Congestion Issues with Logic Synthesis By Mike Clarke, Diego Hammerschlag, Matt Rardon, and Ankush Sood Routing congestion, which results when too many routes need to go through an
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
Graphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis
Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund RTL Synthesis Purpose of HDLs Purpose of Hardware Description Languages: Capture design in Register Transfer Language form i.e. All
101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
N-input EX-NOR gate. N-output inverter. N-input NOR gate
Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It
Why Should I Learn This Language? VLSI HDL. Verilog-2
Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23
98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 1 Lecture 10: Repeater (Buffer) Insertion Introduction to Buffering Buffer Insertion
Schematic design. Gate level design. 0 EDA (Electronic Design Assistance) 0 Classical design. 0 Computer based language
1 / 15 2014/11/20 0 EDA (Electronic Design Assistance) 0 Computer based language 0 HDL (Hardware Description Language) 0 Verilog HDL 0 Created by Gateway Design Automation Corp. in 1983 First modern hardware
scription of the circuit using a high-level design language (HDL) such as VHDL or Verilog. The behavior of this description is checked using simulatio
BooleDozer : Logic synthesis for ASICs L. Stok D. S. Kung D. Brand A. D. Drumm A. J. Sullivan L. N. Reddy N. Hieter D. J. Geiger H. Chao P. J. Osler February 6, 1996 Logic synthesis is the process of automatically
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits Dr. Travis Doom Wright State University Computer Science and Engineering Outline Introduction Microelectronics Micro economics What is design? Techniques
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences. Spring 2010 May 10, 2010
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2010 May 10, 2010 Final Exam Name: ID number: This is
EECS150 - Digital Design Lecture 10 Logic Synthesis
EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
EECS150 - Digital Design Lecture 8 - Hardware Description Languages
EECS150 - Digital Design Lecture 8 - Hardware Description Languages September 19, 2002 John Wawrzynek Fall 2002 EECS150 - Lec08-HDL Page 1 Netlists Design flow What is a HDL? Verilog history examples Outline
Overview of EECS 244:
EECS 244: Overview of the IC Design Flow Prof. Kurt Keutzer EECS keutzer@eecs.berkeley.edu 1 Class News No class Monday Labor Day 2 The Purpose of the Class Project Your first couple years of graduate
ABC basics (compilation from different articles)
1. AIG construction 2. AIG optimization 3. Technology mapping ABC basics (compilation from different articles) 1. BACKGROUND An And-Inverter Graph (AIG) is a directed acyclic graph (DAG), in which a node
TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis
TOPIC : Verilog Synthesis examples Module 4.3 : Verilog synthesis Example : 4-bit magnitude comptarator Discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow.
Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2
Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely
Gate-Level Minimization
Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
Design Methodologies
Design Methodologies 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Complexity Productivity (K) Trans./Staff - Mo. Productivity Trends Logic Transistor per Chip (M) 10,000 0.1
CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
Synthesis at different abstraction levels
Synthesis at different abstraction levels System Level Synthesis Clustering. Communication synthesis. High-Level Synthesis Resource or time constrained scheduling Resource allocation. Binding Register-Transfer
CS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset
Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis
Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital
Programmable Memory Blocks Supporting Content-Addressable Memory
Programmable Memory Blocks Supporting Content-Addressable Memory Frank Heile, Andrew Leaver, Kerry Veenstra Altera 0 Innovation Dr San Jose, CA 95 USA (408) 544-7000 {frank, aleaver, kerry}@altera.com
Based on slides/material by. Topic Design Methodologies and Tools. Outline. Digital IC Implementation Approaches
Based on slides/material by Topic 11 Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
Music. Numbers correspond to course weeks EULA ESE150 Spring click OK Based on slides DeHon 1. !
MIC Lecture #7 Digital Logic Music 1 Numbers correspond to course weeks sample EULA D/A 10101001101 click OK Based on slides 2009--2018 speaker MP Player / iphone / Droid DeHon 1 2 A/D domain conversion
Question Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
SP3Q.3. What makes it a good idea to put CRC computation and error-correcting code computation into custom hardware?
Part II CST: SoC D/M: Quick exercises S3-S4 (examples sheet) Feb 2018 (rev a). This sheet contains short exercises for quick revision. Please also look at past exam questions and/or try some of the longer
Injntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder
VLSI Design 13. Introduction to Verilog
Last module: Sequential circuit design Design styles This module Synthesis Brief introduction to Verilog Synthesis in the Design Flow Designer Tasks Tools Architect Logic Designer Circuit Designer Define
Verilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
CHAPTER 3 METHODOLOGY. 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier
CHAPTER 3 METHODOLOGY 3.1 Analysis of the Conventional High Speed 8-bits x 8-bits Wallace Tree Multiplier The design analysis starts with the analysis of the elementary algorithm for multiplication by
EE-382M VLSI II. Early Design Planning: Front End
EE-382M VLSI II Early Design Planning: Front End Mark McDermott EE 382M-8 VLSI-2 Page Foil # 1 1 EDP Objectives Get designers thinking about physical implementation while doing the architecture design.
Digital Design Methodology
Digital Design Methodology Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 1-1 Digital Design Methodology (Added) Design Methodology Design Specification
Institute of Engineering & Management
Course:CS493- Computer Architecture Lab PROGRAMME: COMPUTERSCIENCE&ENGINEERING DEGREE:B. TECH COURSE: Computer Architecture Lab SEMESTER: 4 CREDITS: 2 COURSECODE: CS493 COURSE TYPE: Practical COURSE AREA/DOMAIN:
Topics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design
Topics of this Slideset CS429: Computer Organization and rchitecture Dr. Bill Young Department of Computer Science University of Texas at ustin Last updated: July 5, 2018 at 11:55 To execute a program
Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration
TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction
6.004 Computation Structures Spring 2009
MIT OpenCourseWare http://ocw.mit.edu 6.004 Computation Structures Spring 2009 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms. M A S S A C H U S E T T
RTL Synthesis using Design Compiler. Dr Basel Halak
RTL Synthesis using Design Compiler Dr Basel Halak Learning Outcomes: After completing this unit, you should be able to: 1. Set up the DC RTL Synthesis Software and run synthesis tasks 2. Synthesize a
SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road QUESTION BANK UNIT I
SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY :: PUTTUR (AUTONOMOUS) Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK Subject with Code : DICD (16EC5703) Year & Sem: I-M.Tech & I-Sem Course
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET4076) Lecture 4(part 2) Testability Measurements (Chapter 6) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Previous lecture What
ARM 64-bit Register File
ARM 64-bit Register File Introduction: In this class we will develop and simulate a simple, pipelined ARM microprocessor. Labs #1 & #2 build some basic components of the processor, then labs #3 and #4
Lecture 15: System Modeling and Verilog
Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading