A CAD Framework for MALIBU: An FPGA with Time-multiplexed Coarse-Grained Elements. David Grant
|
|
|
- Gabriel Johnson
- 5 years ago
- Views:
Transcription
1 A CAD Framework for MALIBU: An FPGA with Time-multiplexed Coarse-Grained Elements David Grant Supervisor: Dr. Guy Lemieux FPGA Feb 28, 2011
2 Motivation Growing Industry Trend: Large FPGA Circuits Often from C-to-Hardware or system generators ex. molecular dynamics, rendering, nuclear simulation Word-oriented Millions of gates 2
3 Motivation Problems with FPGAs CAD runtime can take hours or days Fixed capacity A large circuit may not fit Inefficient use of resources Resources sit idle most of the time 3
4 Motivation Benchmark: chem 4
5 Motivation Benchmark: chem Time-Multiplexing Free TM - Slow Available Spatial Parallelism 5
6 Motivation Solution Divide up the circuit and run it on an array of processors Preserve the coarse-grained features of the circuit Create coarse-grained-aware CAD tools 6
7 Time-Multiplexing Time-Multiplexed FPGAs Look-up Table (LUT) config bits inputs from other LUTs 7
8 Time-Multiplexing Time-Multiplexed FPGAs Time-multiplexed LUT Multiplexer is shared config bits time inputs from other LUTs 8
9 Datapath FPGAs Datapath FPGAs Config bit sharing 1.1x density, same performance config bits config bit a[0] a[0] b[0] b[0] a[1] a[1] b[1] b[1] a[3] a[3] b[3] b[3] Routing Mux Datapath Routing Mux 9
10 Time-Multiplexing and Datapath Where we're going Coarse-grained(datapath) time-multiplexed resources ALU is shared 32 inputs from other ALUs time 10
11 Overview Motivation Malibu Architecture Synthesis Results Traditional Island-Style FPGA 11
12 Overview Motivation Malibu Architecture Synthesis Results Malibu Architecture 12
13 Malibu Architecture Traditional FPGA CLB 13
14 Malibu Architecture Add Coarse-Grained inputs and outputs 14
15 Malibu Architecture Add an ALU and register file 15
16 Malibu Architecture Add coarse-grained communication Each CG has a schedule SL instructions Fmax = 1GHz / SL 16
17 Malibu Architecture Circuit Execution Example c b a N W CLB0 N E W CLB1 x E d S CLB0 Time CG EQ N0,W0 -> CGO0 NOP ADD N0,W0 -> E0 S CLB1 FG LUT CG EQ N0,E0 -> CGO0 XOR N0,E0 -> R0 MUX W0,R0,CGI0->E0 FG 17
18 Malibu Architecture Circuit Execution Example c b a N W CLB0 N E W CLB1 x E d S CLB0 Time CG EQ N0,W0 -> CGO0 NOP ADD N0,W0 -> E0 S CLB1 FG LUT CG EQ N0,E0 -> CGO0 XOR N0,E0 -> R0 MUX W0,R0,CGI0->E0 FG 18
19 Malibu Architecture Circuit Execution Example c b a N W CLB0 N E W CLB1 x E d S CLB0 Time CG EQ N0,W0 -> CGO0 NOP ADD N0,W0 -> E0 S CLB1 FG LUT CG EQ N0,E0 -> CGO0 XOR N0,E0 -> R0 MUX W0,R0,CGI0->E0 FG 19
20 Overview Motivation Malibu Architecture Synthesis Results Verilog Bitstream 20
21 Overview Motivation Malibu Architecture Synthesis Results Verilog M-CAD M-HOT Bitstream 21
22 Front-End Synthesis Parse and Elaborate Use Verilator Construct a CDFG Optimize Coarse-Grained Synthesis Map CDFG to Malibu instructions Various CDFG transformations Fine-Grained Synthesis Extract signals Wf Use OdinII and ABC to synthize to LUTs 22
23 Back-End Synthesis M-CAD Traditional FPGA-CAD flow Separate Placement, Routing, Scheduling M-HOT Integrated placement, routing, scheduling Divides problem into levels, place+route each level Both Approaches Can target any-sized architecture Can trade area for performance Fast 23
24 Synthesis Example assign assign assign assign c1 = (a == b)? 1'b1 : 1'b0; c2 = (c == d)? 1'b1 : 1'b0; t2 = c ^ d; x = (c1 & c2)? t1 : t2; clk) begin t1 <= a + b; end 24
25 Synthesis CDFG and ALAP output of Front-End Synthesis Level
26 Synthesis M-HOT Place, Route, Schedule each height CLB0 CLB1 5: EQ - 6: EQ - 5: EQ 8: LUT - 6: EQ 7: XOR - 5: EQ 8: AND 4: ADD 6: EQ 7: XOR 9: MUX 26
27 Overview Motivation Malibu Architecture Synthesis Results 27
28 Results Frequency (MHz) for each benchmark 28
29 Results Frequency (MHz) for each benchmark Coarse-grained circuits 29
30 Results Area vs. Performance tradeoff 30
31 Results Results (compared to Quartus II / Stratix III) M-HOT M-CAD Synthesis Time Improvement: 30.9x 77.0x User Clock Speed: 0.12x 0.07x Density: 1.48x 0.67x 10x = 10 times better than the Quartus result 1x = same as Quartus 0.1x = 1/10th the Quartus result (10 times worse) 31
32 Future Work Improve Front-End Synthesis Needs to be both coarse-grain and fine-grain aware Coarse-grained optimizations Improve M-CAD and M-HOT Possibly 2x-3x performance improvement 32
33 Thanks Purpose Implement a circuit on a coarse-grained/fine-grained architecture Malibu Architecture FPGA with time-multiplexed coarse-grained resources Can trade density for performance Synthesis (M-CAD and M-HOT) Fast, up to 250x faster than QuartusII Fmax results within 1/10th of an FPGA 33
A CAD Framework for MALIBU: An FPGA with Time-multiplexed Coarse-Grained Elements
A CAD Framework for MALIBU: An FPGA with Time-multiplexed Coarse-Grained Elements David Grant Chris Wang Guy G.F. Lemieux Department of Electrical and Computer Engineering University of British Columbia,
CAD Algorithms and Performance of Malibu: An FPGA with Time-Multiplexed Coarse-Grained Elements
CAD Algorithms and Performance of Malibu: An FPGA with Time-Multiplexed Coarse-Grained Elements by David Grant B.A.Sc. Computer Engineering, University of Waterloo, 2002 M.A.Sc. Electrical and Computer
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool Jin Hee Kim and Jason Anderson FPL 2015 London, UK September 3, 2015 2 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Homework deadline extended to next friday
Norm Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday Description Design Conception
FPGA: What? Why? Marco D. Santambrogio
FPGA: What? Why? Marco D. Santambrogio marco.santambrogio@polimi.it 2 Reconfigurable Hardware Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much
Development of tools supporting. MEANDER Design Framework
Development of tools supporting FPGA reconfigurable hardware MEANDER Design Framework Presentation Outline Current state of academic design tools Proposed design flow Proposed graphical user interface
Xilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
Logic Optimization Techniques for Multiplexers
Logic Optimiation Techniques for Multiplexers Jennifer Stephenson, Applications Engineering Paul Metgen, Software Engineering Altera Corporation 1 Abstract To drive down the cost of today s highly complex
FPGA architecture and design technology
CE 435 Embedded Systems Spring 2017 FPGA architecture and design technology Nikos Bellas Computer and Communications Engineering Department University of Thessaly 1 FPGA fabric A generic island-style FPGA
Lecture 41: Introduction to Reconfigurable Computing
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 41: Introduction to Reconfigurable Computing Michael Le, Sp07 Head TA April 30, 2007 Slides Courtesy of Hayden So, Sp06 CS61c Head TA Following
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
Programmable Logic Devices HDL-Based Design Flows CMPE 415
HDL-Based Design Flows: ASIC Toward the end of the 80s, it became difficult to use schematic-based ASIC flows to deal with the size and complexity of >5K or more gates. HDLs were introduced to deal with
ECE 636. Reconfigurable Computing. Lecture 2. Field Programmable Gate Arrays I
ECE 636 Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays I Overview Anti-fuse and EEPROM-based devices Contemporary SRAM devices - Wiring - Embedded New trends - Single-driver wiring -
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs. Jason Luu
A Hierarchical Description Language and Packing Algorithm for Heterogenous FPGAs by Jason Luu A thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate
COE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
FABRICATION TECHNOLOGIES
FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general
Outline. EECS Components and Design Techniques for Digital Systems. Lec 11 Putting it all together Where are we now?
Outline EECS 5 - Components and Design Techniques for Digital Systems Lec Putting it all together -5-4 David Culler Electrical Engineering and Computer Sciences University of California Berkeley Top-to-bottom
A Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs
A Multi-Ported Memory Compiler Utilizing True Dual-port BAMs a place of mind THE UNIVESITY OF BITISH COLUMBIA Ameer Abdelhadi and Guy Lemieux Department of Electrical and Computer Engineering University
Readings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops. Each flip-flop stores 1 bit of information.
Registers Readings: 5.8-5.9.3 Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information ff ff ff ff 178 Controlled Register Reset Load Action
ECE Digital Engineering Laboratory. Designing for Synthesis
ECE 554 - Digital Engineering Laboratory Designing for Synthesis Below is a list of coding styles that might cause synthesis problems and/or inefficient design implementation. This is not an exhaustive
A Routing Approach to Reduce Glitches in Low Power FPGAs
A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin Wong Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign This research
TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis
TOPIC : Verilog Synthesis examples Module 4.3 : Verilog synthesis Example : 4-bit magnitude comptarator Discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow.
Hybrid LUT/Multiplexer FPGA Logic Architectures
Hybrid LUT/Multiplexer FPGA Logic Architectures Abstract: Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers
DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric
DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis ISCA June 22, 2016 FPGA-Based
Note: Closed book no notes or other material allowed, no calculators or other electronic devices.
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Exam Review Note: Closed book no notes or other material allowed, no calculators or other electronic devices. One page
Designing Heterogeneous FPGAs with Multiple SBs *
Designing Heterogeneous FPGAs with Multiple SBs * K. Siozios, S. Mamagkakis, D. Soudris, and A. Thanailakis VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus
Hardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
Don t expect to be able to write and debug your code during the lab session.
EECS150 Spring 2002 Lab 4 Verilog Simulation Mapping UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping
FPGA Power and Timing Optimization: Architecture, Process, and CAD
FPGA Power and Timing Optimization: Architecture, Process, and CAD Chun Zhang 1, Lerong Cheng 2, Lingli Wang 1* and Jiarong Tong 1 1 State-Key-Lab of ASIC & System, Fudan University llwang@fudan.edu.cn
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
Parallelizing FPGA Technology Mapping using GPUs. Doris Chen Deshanand Singh Aug 31 st, 2010
Parallelizing FPGA Technology Mapping using GPUs Doris Chen Deshanand Singh Aug 31 st, 2010 Motivation: Compile Time In last 12 years: 110x increase in FPGA Logic, 23x increase in CPU speed, 4.8x gap Question:
Verilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
FPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course
EITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Introduction to FPGA design Rakesh Gangarajaiah Rakesh.gangarajaiah@eit.lth.se Slides from Chenxin Zhang and Steffan Malkowsky WWW.FPGA What is FPGA? Field
THE COARSE-GRAINED / FINE-GRAINED LOGIC INTERFACE IN FPGAS WITH EMBEDDED FLOATING-POINT ARITHMETIC UNITS
THE COARSE-GRAINED / FINE-GRAINED LOGIC INTERFACE IN FPGAS WITH EMBEDDED FLOATING-POINT ARITHMETIC UNITS Chi Wai Yu 1, Julien Lamoureux 2, Steven J.E. Wilton 2, Philip H.W. Leong 3, Wayne Luk 1 1 Dept
Verilog Hardware Description Language ROOM: B405
Verilog Hardware Description Language HONG@IS.NAIST.JP ROOM: B405 Content Lecture 1: Computer organization and performance evaluation metrics Lecture 2: Processor architecture and memory system Lecture
Introduction to VHDL Design on Quartus II and DE2 Board
ECP3116 Digital Computer Design Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE2 Board Objective To learn how to create projects using Quartus II, design circuits and
! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!
Programmable Logic Devices FPGA Architectures II CMPE 415. Overview This set of notes introduces many of the features available in the FPGAs of today.
Overview This set of notes introduces many of the features available in the FPGAs of today. The majority use SRAM based configuration cells, which allows fast reconfiguation. Allows new design ideas to
Secure Function Evaluation using an FPGA Overlay Architecture
Secure Function Evaluation using an FPGA Overlay Architecture Xin Fang Stratis Ioannidis Miriam Leeser Dept. of Electrical and Computer Engineering Northeastern University Boston, MA, USA FPGA 217 1 Introduction
OPTIMIZING COARSE- GRAINED UNITS IN FLOATING POINT HYBRID FPGA
OPTIMIZING COARSE- GRAINED UNITS IN FLOATING POINT HYBRID FPGA Chi Wai Yu 1, Alastair M. Smith 2, Wayne Luk 1, Philip Leong 3, Steven J.E. Wilton 2 1 Dept of Computing Imperial College London, London {cyu,wl}@doc.ic.ac.uk
PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES
PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES. psa. rom. fpga THE WAY THE MODULES ARE PROGRAMMED NETWORKS OF PROGRAMMABLE MODULES EXAMPLES OF USES Programmable
EECS Components and Design Techniques for Digital Systems. Lec 07 PLAs and FSMs 9/ Big Idea: boolean functions <> gates.
Review: minimum sum-of-products expression from a Karnaugh map EECS 5 - Components and Design Techniques for Digital Systems Lec 7 PLAs and FSMs 9/2- David Culler Electrical Engineering and Computer Sciences
ESE534: Computer Organization. Tabula. Previously. Today. How often is reuse of the same operation applicable?
ESE534: Computer Organization Day 22: April 9, 2012 Time Multiplexing Tabula March 1, 2010 Announced new architecture We would say w=1, c=8 arch. 1 [src: www.tabula.com] 2 Previously Today Saw how to pipeline
Design of Digital Circuits
Design of Digital Circuits Lecture 3: Introduction to the Labs and FPGAs Prof. Onur Mutlu (Lecture by Hasan Hassan) ETH Zurich Spring 2018 1 March 2018 1 Lab Sessions Where? HG E 19, HG E 26.1, HG E 26.3,
More Course Information
More Course Information Labs and lectures are both important Labs: cover more on hands-on design/tool/flow issues Lectures: important in terms of basic concepts and fundamentals Do well in labs Do well
FPGAs: Instant Access
FPGAs: Instant Access Clive"Max"Maxfield AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO % ELSEVIER Newnes is an imprint of Elsevier Newnes Contents
Lab 2: Modifying LegUp to Limit the Number of Hardware Functional Units
Lab 2: Modifying LegUp to Limit the Number of Hardware Functional Units 1 Introduction and Motivation In this lab, you will gain exposure to the scheduling and binding steps of LegUp. You will modify user
structure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
CS310 Embedded Computer Systems. Maeng
1 INTRODUCTION (PART II) Maeng Three key embedded system technologies 2 Technology A manner of accomplishing a task, especially using technical processes, methods, or knowledge Three key technologies for
Review from last time. CS152 Computer Architecture and Engineering Lecture 6. Verilog (finish) Multiply, Divide, Shift
Review from last time CS152 Computer Architecture and Engineering Lecture 6 Verilog (finish) Multiply, Divide, Shift February 11, 2004 John Kubiatowicz (www.cs.berkeley.edu/~kubitron) lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/
Exp#8: Designing a Programmable Sequence Detector
Exp#8: Designing a Programmable Sequence Detector Objectives Learning how to partition a system into data-path and control unit. Integrating Schematics and Verilog code together Overview In this lab you
Introduction to Field Programmable Gate Arrays
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
1 In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design
In the previous lecture, we examined how to analyse a FSM using state table, state diagram and waveforms. In this lecture we will learn how to design a fininte state machine in order to produce the desired
DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric
DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis ISCA June 22, 2016 FPGA-Based
HDLs and SystemVerilog. Digital Computer Design
HDLs and SystemVerilog Digital Computer Design Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction Alastair M. Smith, George A. Constantinides and Peter Y. K. Cheung Imperial College, London SW7 2BT, U.K. {alastair.smith,g.constantinides,p.cheung}@imperial.ac.uk
The Xilinx XC6200 chip, the software tools and the board development tools
The Xilinx XC6200 chip, the software tools and the board development tools What is an FPGA? Field Programmable Gate Array Fully programmable alternative to a customized chip Used to implement functions
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
Design and Implementation of FPGA Logic Architectures using Hybrid LUT/Multiplexer
Design and Implementation of FPGA Logic Architectures using Hybrid LUT/Multiplexer Krosuri Rajyalakshmi 1 J.Narashima Rao 2 rajyalakshmi.krosuri@gmail.com 1 jnarasimharao09@gmail.com 2 1 PG Scholar, VLSI,
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
Multi Cycle Implementation Scheme for 8 bit Microprocessor by VHDL
Multi Cycle Implementation Scheme for 8 bit Microprocessor by VHDL Sharmin Abdullah, Nusrat Sharmin, Nafisha Alam Department of Electrical & Electronic Engineering Ahsanullah University of Science & Technology
Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah
Mapping-aware Logic Synthesis with Parallelized Stochastic Optimization
Mapping-aware Logic Synthesis with Parallelized Stochastic Optimization Zhiru Zhang School of ECE, Cornell University September 29, 2017 @ EPFL A Case Study on Digit Recognition bit6 popcount(bit49 digit)
EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
Announcements. Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project
- Fall 2002 Lecture 20 Synthesis Sequential Logic Announcements Midterm 2 next Thursday, 6-7:30pm, 277 Cory Review session on Tuesday, 6-7:30pm, 277 Cory Homework 8 due next Tuesday Labs: project» Teams
Structured Datapaths. Preclass 1. Throughput Yield. Preclass 1
ESE534: Computer Organization Day 23: November 21, 2016 Time Multiplexing Tabula March 1, 2010 Announced new architecture We would say w=1, c=8 arch. March, 2015 Tabula closed doors 1 [src: www.tabula.com]
Soft-error and Variability Resilience in Dependable VLSI Platform. Hidetoshi Onodera Kyoto University
Soft-error and Variability Resilience in Dependable VLSI Platform Hidetoshi Onodera Kyoto University Outline: Soft-error and Variability Resilience 1 Background Overview: Dependable VLSI Platform Circuit-level
Automated Space/Time Scaling of Streaming Task Graphs. Hossein Omidian Supervisor: Guy Lemieux
Automated Space/Time Scaling of Streaming Task Graphs Hossein Omidian Supervisor: Guy Lemieux 1 Contents Introduction KPN-based HLS Tool for MPPA overlay Experimental Results Future Work Conclusion 2 Introduction
Evolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
Two hours - online EXAM PAPER MUST NOT BE REMOVED FROM THE EXAM ROOM UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
COMP 12111 Two hours - online This paper version is made available as a backup In this event, only MCQ answers written in the boxes on the exam paper will be marked. EXAM PAPER MUST NOT BE REMOVED FROM
IMPROVING MEMORY AND VALIDATION SUPPORT IN FPGA ARCHITECTURE EXPLORATION. Andrew Somerville
IMPROVING MEMORY AND VALIDATION SUPPORT IN FPGA ARCHITECTURE EXPLORATION by Andrew Somerville Bachelor of Computer Science, University of New Brunswick, 2010 A Thesis Submitted in Partial Fulfillment of
Recommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto
Recommed Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto DISCLAIMER: The information contained in this document does NOT contain
EECS150 - Digital Design Lecture 7 - Computer Aided Design (CAD) - Part II (Logic Simulation) Finite State Machine Review
EECS150 - Digital Design Lecture 7 - Computer Aided Design (CAD) - Part II (Logic Simulation) Feb 9, 2010 John Wawrzynek Spring 2010 EECS150 - Lec7-CAD2 Page 1 Finite State Machine Review State Transition
Stratix vs. Virtex-II Pro FPGA Performance Analysis
White Paper Stratix vs. Virtex-II Pro FPGA Performance Analysis The Stratix TM and Stratix II architecture provides outstanding performance for the high performance design segment, providing clear performance
FPGA VHDL Design Flow AES128 Implementation
Sakinder Ali FPGA VHDL Design Flow AES128 Implementation Field Programmable Gate Array Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure: 1. The interconnection
Introduction to Design Vision. Instructor: Prof. Shantanu Dutt. TA: Soumya Banerjee
Introduction to Design Vision Instructor: Prof. Shantanu Dutt TA: Soumya Banerjee We use Synopsys Design Vision for synthesizing the VHDL descriptions. If you are aware in the show schematic option in
An FPGA Architecture Supporting Dynamically-Controlled Power Gating
An FPGA Architecture Supporting Dynamically-Controlled Power Gating Altera Corporation March 16 th, 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca System-on-Chip Research Group Department
LAB 5 Implementing an ALU
Goals To Do Design a practical ALU LAB 5 Implementing an ALU Learn how to extract performance numbers (area and speed) Draw a block level diagram of the MIPS 32-bit ALU, based on the description in the
Performance Improvement and Size Reduction Scheme over Circuits by Using LUT/MUX Architecture
Performance Improvement and Size Reduction Scheme over Circuits by Using LUT/MUX Architecture R. Pradeepa 1, S.P. Senthil Kumar 2 M.E. VLSI Design, Shanmuganathan Engineering College, Arasampatti, Pudukkottai-622507,
DE2 Board & Quartus II Software
January 23, 2015 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours Email SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM contre47@nevada.unlv.edu Syllabus
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et
Overview. CSE372 Digital Systems Organization and Design Lab. Hardware CAD. Two Types of Chips
Overview CSE372 Digital Systems Organization and Design Lab Prof. Milo Martin Unit 5: Hardware Synthesis CAD (Computer Aided Design) Use computers to design computers Virtuous cycle Architectural-level,
Architecture and Synthesis for Multi-Cycle Communication
Architecture and Synthesis for Multi-Cycle Communication Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang Computer Science Department University of California, Los Angeles Los Angeles CA 90095 USA {cong,
Spiral 2-8. Cell Layout
2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric
Improving Reconfiguration Speed for Dynamic Circuit Specialization using Placement Constraints
Improving Reconfiguration Speed for Dynamic Circuit Specialization using Placement Constraints Amit Kulkarni, Tom Davidson, Karel Heyse, and Dirk Stroobandt ELIS department, Computer Systems Lab, Ghent
EECS150 - Digital Design Lecture 23 - High-Level Design (Part 1)
EECS150 - Digital Design Lecture 23 - High-Level Design (Part 1) April 21, 2009 John Wawrzynek Spring 2009 EECS150 - Lec24-hdl1 Page 1 Introduction High-level Design Specifies: How data is moved around
Lab #1: Introduction to Design Methodology with FPGAs part 1 (80 pts)
Nate Pihlstrom, npihlstr@uccs.edu Lab #1: Introduction to Design Methodology with FPGAs part 1 (80 pts) Objective The objective of this lab assignment is to introduce and use a methodology for designing
Reduce Your System Power Consumption with Altera FPGAs Altera Corporation Public
Reduce Your System Power Consumption with Altera FPGAs Agenda Benefits of lower power in systems Stratix III power technology Cyclone III power Quartus II power optimization and estimation tools Summary
Implementing Logic in FPGA Memory Arrays: Heterogeneous Memory Architectures
Implementing Logic in FPGA Memory Arrays: Heterogeneous Memory Architectures Steven J.E. Wilton Department of Electrical and Computer Engineering University of British Columbia Vancouver, BC, Canada, V6T
Verilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)
Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs
Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs Anurag Tiwari and Karen A. Tomko Department of ECECS, University of Cincinnati Cincinnati, OH 45221-0030, USA {atiwari,