Architecture Evaluation for

Transcription

1 Architecture Evaluation for Power-efficient FPGAs Fei Li*, Deming Chen +, Lei He*, Jason Cong + * EE Department, UCLA + CS Department, UCLA Partially supported by NSF and SRC

2 Outline Introduction Evaluation Flow Architecture Model Power Model Architecture Evaluation Results Conclusions Feb FPGA Symposium

3 Introduction Existing FPGAs are known to be power inefficient E.g. [Kusse, ISLPED 98] Design Example Xilinx XC4003A Static CMOS 100X power overhead Vdd 3.3v 4.2mW/MHz 5.5uW/MHz Need to explore power efficient FPGAs 5v Table1 8-bit adder Energy Feb FPGA Symposium

4 Evaluation Framework fpgaeva-lp fpgaeva-lp flow [Cong, et al, ICCD 00] BLIF SLIF Arch Spec Logic Optimization(SIS) Tech-Mapping (RASP) Timing-Driven Packing (TV-Pack) Placement & Routing (VPR) BC-Netlist Generator BC-Netlist Power Simulator Area Delay Power Feb FPGA Symposium

5 Architecture Model Logic Block [Ahmed-Rose, FPGA2000] BLE: Basic Logic Inputs K-input LUT D FF Out Parameters: LUT Size k Element Clock BLE #1 CLB: Cluster-Based Logic Block I Inpu ts I BLE #N N N Outputs Cluster Size N Clock Feb FPGA Symposium

6 Architecture Model Routing Structure [Betz-Rose, FPGA1999] Pass transistor routing switch Tri-state buffer routing switch Logic block Parameters: Wire segment length Switch-box type Buffer/Pass transistor distribution Connection box configuration Routing wire Logic block pin to routing connection point Feb FPGA Symposium

7 BC-Netlist Generator Mapped Netlist Layout Buffer Extraction Netlist Generation for Logic Clusters Capacitance Extraction Delay Calculation Back-annotation BC-Netlist Feb FPGA Symposium

8 Capacitance Extraction and Delay Calculation 0.28 b1 Pass transistors b2 Wires segmented by buffers and pass transistors Buffer X 0.33 b Wire segments Buffer Y Capacitance: lumped from all branches for wires, pass transistors and gates (buffers) Delay: Elmore Delay model Feb FPGA Symposium

9 Mixed-level Power Model Overview Dynamic power Switching power Short-circuit power Related to signal transitions Functional switch Glitch Static Power Sub-threshold leakage Reverse biased leakage Depending on the input vector components power sources Dynamic Static Logic Block Macro-model Macro-model Interconnect & clock Switch-level model Macro-model Feb FPGA Symposium

10 Macromodeling Dynamic Power Pre-characterized average power per access Based SPICE simulation with random input vectors Both switching power and short-circuit power Applied to LUTs that have the regularity of connection Verification SPICE simulation Our Power Model Error Total Energy (Jourl) 1.42E E % 200 random input vectors Feb FPGA Symposium

11 Macromodeling Static Power Input pattern dependent Pre-characterized average static power Input vectors are grouped into vector sets Typical vectors are simulated in each set Save SPICE simulation time Applied to both LUTs and Interconnect buffs Feb FPGA Symposium

12 Switch-level Model Interconnect Switching Power Switching power without glitches P sw 2 = 0.5 f V C E a = 0.5 f V i= 1 ( N / cycles) Effective transition number ( V 1 Nˆ i (rising) = dd 2 dd i= 1 Switching power with glitches P sw = = n n C V 2 )( V 1 + V 2 2 V dd 0.5 f 2 n V C Eˆ dd i = 1 i i 0.5 f 2 n V C Nˆ dd i = 1 i ( i / i i i i 2V dd ) cycles ) N i t 1 t 2 b V dd i ( t ) R Transition time V dd c V( t) C Feb FPGA Symposium

13 Switch-level Model Interconnect Short-Circuit Power Short-circuit power Fixed ratio between short-circuit and switching power The ratio is decided by SPICE simulation (13%) 4.50E-15 load= inv1x load=2 inv1x 4.00E-15 Dynamic Power (watt) 3.50E E E E Input Signal Transition Time (ns) Feb FPGA Symposium

14 Power Simulator BC-Netlist Random Vector Generation Cycle Accurate Power Simulation with Glitch Analysis Post-layout extracted delay & capacitance i active j idle No E = E ( n) + E ( n) cycle a s All cycles finished? Yes Power Values Mixed-level Power Model Feb FPGA Symposium

15 Experimental Settings Technology R_NMOS R_wire C_wire 0.1 µ 5300 Ohm MOhm/m 73.8 af/um Logic Block Architectures LUT Size k Cluster Size N routing_default routing_fullbuf1 routing_fullbuf2 Routing Architectures 3 7 4, 8, 12, 16, 20 wire length 4, 50% buffers and 50% pass transistors wire length 4, 100% buffers wire lengths 4 and 8, 100% buffers Feb FPGA Symposium

16 Experiments on Logic Block Architectures Total FPGA Power (normalized geometric mean) Cluster Size = 4 Cluster Size = 8 Cluster Size = Normalized Geometric Mean Total FPGA Power Critical Path Delay Power-Delay Product LUT Size Cluster Size LUT Size = 4 LUT Size = 4 is also optimal for power consumption Cluster Size = 12 is the optimal cluster size Feb FPGA Symposium

17 Experiments on Routing Architectures wire length 4, 50% buffers and 50% pass transistors wire length 4, 100% buffers wire lengths 4 and 8, 100% buffers routing_default achieves lowest power Total FPGA Power (normalized geometric mean) routing_default routing_fullbuf1 routing_fullbuf2 Critical Path Delay (normalized geometric mean) routing_default routing_fullbuf1 routing_fullbuf LUT Size 0.8 Cluster Size = LUT Size Feb FPGA Symposium

18 Power Breakdown Cluster Size = 12, LUT Size = 4 Cluster Size = 12, LUT Size = 6 Clock Power 22% Logic Block Power 19% Clock Power 15% Logic Block Power 40% Interconnect Power 59% Interconnect Power 45% Interconnect power is dominant Feb FPGA Symposium

19 Power Breakdown Cluster Size = 12, LUT Size = 4 Cluster Size = 12, LUT Size = 6 Leakage Power 42% Leakage Power 52% Dynamic Power 58% Dynamic Power 48% Leakage power becomes increasingly important Feb FPGA Symposium

20 Conclusions Developed an architecture evaluation framework fpgaeva-lp for power efficiency Performed quantitative analysis for parameterized FPGA architecture Identified future directions for FPGA power optimization Interconnect power is dominant Leakage power is becoming important Feb FPGA Symposium