Introduction to PowerVR Ray Tracing Tuesday 18th March, GDC. James A. McCombe

Transcription

1 Introduction to PowerVR Tracing Tuesday 18th March, GDC James A. McCombe

2 What are we launching today?

3 Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array System Memory Interface Pixel Data Master Compute Data Master Course Grain Scheduler 0 Texture Unit... 1 Core Management Data Master n-1 Texture Unit n Memory Cache Unit Tracing Unit Intersection Processor Array Coherency Engine Scene Frame Hierarchy Accumulator Generator Cache System Memory Bus Tiling Coprocessor Pixel Co- Processor 2D Core (PTLA)

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6 What are the applications for this?

7

8 Augmented Reality Image and Diagram Copyright Peter Kán 2012

9 Virtual Reality a.k.a Multi-persective rendering Lens distortion and aberration correction Lenticular Displays Ultra-low latency rendering

10 Hybrid rendering in games Shadows Reflections Transparency Better scaling with multiple dynamic lights Real-time light map updates for the rasteriser Easy to bolt on

11 Fully ray traced graphics Brute force path tracing Produces photo realism easily Pretty much requires all the 3D content to be ray traced Possible in todays technology in console / desktop using Wizard Probably not practical for fully real-time use in mobile for a couple more generations. Fine for sub-realtime use.

12 Non-graphics Better in-game AI Collision Detection 3D spatial search

13 Overview of PowerVR

14 Power and Bandwidth 300W 300Gb/s 270Gb/s 240Gb/s 225W 210Gb/s 180Gb/s 150W 150Gb/s 120Gb/s 90Gb/s 75W 60Gb/s 30Gb/s 0W 0Gb/s Workstation Mobile Workstation Laptop Light Laptop Tablet Graphics Watts Graphics Bandwidth

15 Capability of our mobile graphics 150 Shader GFlops Almost 5x compute capability 4x vec4 MAD 16x Scalar 2xMAD Gtexels/s OpenGLES 3.0 Support

16 Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array System Memory Interface Pixel Data Master Compute Data Master Course Grain Scheduler 0 Texture Unit... 1 Core Management n-1 Texture Unit n Memory Cache Unit Tiling Coprocessor Pixel Co- Processor 2D Core (PTLA) System Memory Bus

17 Vertex Data Master Vertex Task 32 Instances Unified Shading Cluster Array Pixel Data Master Pixel Task Compute Task 32 Instances CGS 0 n-1 Texture Unit Texture Unit 1 n Compute Data Master 32 Instances An instance is a vertex, pixel or OpenCL thread All instances in the task share Program, Uniforms, Parameters, etc.

18 Shader Uniforms and Constants Common Store Registers (Shared across instances in the task) Common Instruction ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU Per Pixel / Vertex data and shader temps Unified Store Registers (Private registers per instance) (not exact)

19 Source 0 ABS, NEG, etc. 2 Flops Source 1 Source 2 ABS, NEG, etc. ABS, NEG, etc. Integer Math Format Conversions Output 0 Comparison Format Conversions Source 3 ABS, NEG, etc. Source 4 ABS, NEG, etc. 2 Flops Output 1 Source 5 ABS, NEG, etc. 12 Cycles of Latency (not exact)

20 Common Store Registers (Shared across instances in the task) Common Instruction ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU ALU varying vec2 texcoord; void main() { if (texcoord.x > 0.5) { } else { } Unified Store Registers (Private registers per instance)

21 Overall capability Series6 gives you over 100Gflops for shading on latest mobile devices OpenGL ES 3.0 support Massive capability gain allowing math heavy shaders Mobile graphics is where the actual innovation is happening Try it!

22 A Technical introduction to Wizard

23 Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array System Memory Interface Pixel Data Master Compute Data Master Course Grain Scheduler 0 Texture Unit... 1 Core Management Data Master n-1 Texture Unit n Memory Cache Unit Tracing Unit Intersection Processor Array Coherency Engine Scene Frame Hierarchy Accumulator Generator Cache System Memory Bus Tiling Coprocessor Pixel Co- Processor 2D Core (PTLA)

24 Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array System Memory Interface Pixel Data Master Compute Data Master Course Grain Scheduler 0 Texture Unit... 1 Core Management Data Master n-1 Texture Unit n Memory Cache Unit Tracing Unit Intersection Processor Array Coherency Engine Scene Frame Hierarchy Accumulator Generator Cache System Memory Bus Tiling Coprocessor Pixel Co- Processor 2D Core (PTLA)

25 Source 0 ABS, NEG, etc. 2 Flops Source 1 Source 2 ABS, NEG, etc. ABS, NEG, etc. Integer Math Format Conversions Output 0 RAM Comparison Format Conversions Source 3 ABS, NEG, etc. Source 4 ABS, NEG, etc. 2 Flops Output 1 RAM Source 5 ABS, NEG, etc. 12 Cycles of Latency (not exact)

26 New shader type Shaders are invoked when a ray intersects a triangle Shaders types can emit any number of rays OpenRL has a frame shader to emit primary rays Existing fragment / pixel shaders can emit rays also! GLSL Programming model is the same Built-in functions, parameters, etc.

27 Primitive Objects Encapsulate the rendering state for one mesh Includes VBOs, uniforms, shader programs, texture bindings, etc. tracing unit sorts rays into tasks with common primitive objects Persistent between frames Mutable objects by the client

28 Constraints / Limitations Shaders cannot wait for results of individual ray trace operations Shaders must provide a worst case estimate on number of child rays Per-ray user data payload must be carefully managed

29 Task 0 Parallelism is on rays NOT pixels Task 1 Common Instruction ALU ALU ALU ALU Task 2 (In this example, ALU width is 4 to make the diagram smaller) Task 3

30 Parallelism is on rays NOT pixels

31 Relief: Quick ray emission demo

32 Intersection Processor Array or Who needs Fixed Function?

33 :AABB Test Fast -Axis Aligned Bounding Overlap Tests with Plucker Coordinates. Jeffrey Mahovsky and Brian Wyvill 6 lines form the silhouette of the AABB 6 planes from the ray origin and each edge vector Dot product of plane normal and ray direction vector 6 signs must match and be negative.

34 distance setup Translation Plane Setup Plane tests Test Combine XB 0 >7 voxel_center_x origin_x! shift_center_x7+/! AX0min BX0max cov_convert Octant(0) XA XB XA ri(31) ri invert ri(31) >7 origin_x_miss invert ri(31) ri(31) dirx ray_distance diry ray_distance x x ri rj voxel_center_y origin_y! shift_center_y7+/! AY0min BY0max cov_convert Octant(1) YB YA YB YA rj(31) rj(31) 0 rj >7 invert rj(31) >7 invert rj(31) endpt_x_miss origin_y_miss endpt_y_miss origin_z_miss MISS Hit or Miss dirz ray_distance x rk! ZB 0 >7 endpt_z_miss voxel_center_z origin_z! shift_center_z7+/! AZ0min BZ0max cov_convert Octant(2) ZA ZB ZA rk(31) rk invert rk(31) >7 invert 3 MUL 6 SUB 6 ADD 12 MUL 6 bitwise OR rk(31) rk(31)

35 instruction group packing LD MUL ADD MUL OR LD MUL ADD MUL LD MUL ADD MUL OR LD SUB ADD MUL 26 Instructions LD LD SUB SUB SUB SUB ADD ADD MUL MUL MUL MUL OR OR (32 if using compressed data formats) SUB MUL OR MUL MUL OR MUL

36 Triangle Triangle Tester and s Tester and s Triangle Triangle Tester and s Tester and s Child Address Free Queue Hits Coherence Cache Old Count Update Existing Queue Existing Queue Queue Packer Inst Data Inst Data Update New Queue Coherence Queue RAM 44x less area for this function

37 The Tracing Unit and Coherence Engine

38 Data Master Course Grain Scheduler Unified Shading Cluster Array 0 Texture Unit 1 System Memory Interface n-1 Texture Unit n s grouped by PrimitiveObject (Shader + Resources) s in arbitrary order Tracing Unit Intersection Processor Array Coherency Engine System Memory Bus

39 AABB Blocks Vertex Blocks Varyings Ascending Virtual Memory Addresses ( around 100Mbytes for 1M triangles including varyings )

40 Primitive Object 1 Primitive Object 2 PrimitiveObject 0

41 node_ node_17094 node_13580 node_17097 node_13627 node_17101 node_13567 node_17104 node_13619 node_17108 node_13571 node_13574 node_17113 node_13623 node_22218 node_13227 node_18727 node_13233 node_18728 node_18732 node_13270 node_18735 node_13262 node_13064 node_18644 node_13182 node_18645 node_18649 node_13056 node_18652 node_13175 node_17181 node_11676 node_17186 node_11707 node_17188 node_11680 node_17191 node_11710 node_19786 node_13225 node_18690 node_18693 node_13223 node_18699 node_18706 node_13260 node_18720 node_18714 node_12173 node_22242 node_22251 node_18863 node_18868 node_5790 node_5792 node_18870 node_5788 node_5785 node_12226 node_5883 node_18875 node_6403 node_6405 node_6208 node_6212 node_6221 node_6216 node_18881 node_6401 node_6200 node_6204 node_13363 node_6399 node_6192 node_6196 node_18894 node_18899 node_5801 node_5805 node_18902 node_5794 node_5799 node_18906 node_6232 node_6419 node_6421 node_6238 node_6242 node_18914 node_6222 node_6228 node_6407 node_6417 node_22256 node_18804 node_18807 node_13257 node_18812 node_12204 node_5773 node_12202 node_5775 node_18815 node_6166 node_13331 node_6389 node_6162 node_13335 node_6387 node_18821 node_12196 node_12189 node_12192 node_18825 node_13323 node_13315 node_13319 node_6160 node_18836 node_18841 node_12220 node_5781 node_12218 node_5783 node_18844 node_1221 node_5777 node_12210 node_5779 node_22290 node_22294 node_22300 node_16820 node_16823 node_10766 node_22307 node_22311 node_22317 node_22323 node_22431 node_22438 node_11100 node_16838 node_11102 node_11104 node_16841 node_11106 node_22446 node_10782 node_16827 node_10804 node_10833 node_16831 node_10853 node_22451 node_11094 node_19643 node_10965 node_11031 node_11096 node_11098 node_22459 node_22467 node_16854 node_16857 node_22474 node_22480 node_16850 node_16843 node_16846 node_11108 node_19254 node_19259 node_7692 node_13760 node_7710 node_7688 node_13764 node_7706 node_19264 node_7634 node_13681 node_7672 node_13685 node_7670 node_7626 node_7628 node_19272 node_13750 node_7686 node_13754 node_7704 node_1 node_13671 nod node_13945

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43 Primitive Object 1 Primitive Object 2 PrimitiveObject 0

44 (coherence queues) Primitive Object 1 Primitive Object 2 PrimitiveObject 0

45 Automatically finds coherence paths

46 The Scene Hierarchy Generator

47 Vertex Data Master Course Grain Scheduler Unified Shading Cluster Array 0 Texture Unit 1 System Memory Interface n-1 Texture Unit n World-space Triangles and associated varyings Scene Hierarchy Generator System Memory Bus

48 Limitations Scene is represented by triangles same as today BVH is in a defined format optimised for construction and traversal Triangle order must generally follow a spatially coherent flow An approximate scene scale estimation is needed Geometry shaders are not inline with the ray tracing pipeline

49 Strengths Shading cluster workload is no higher than a vertex shader Only needs to process geometry that actually moved in world space Unique algorithm constrains working set to internal registers only Single pass operation: in-line with vertex shader execution Handles the long skinny triangles problem well Streaming writes to external memory Losslessly compressed output formats due to build algorithm Compact logic

50 Built on sparse log2 oct-tree scaffolding Level = 1 Level = 2 Level = 3

51 For each triangle Select LOD VBExtents Foreach VBNode in LOD v2 Compute Parent Voxel v1 v0 VBNode Pool Per LOD VBNode linked list head pointers On VoxelCache HIT Leaf VoxelCache On eviction Add VBNode GenerateVBNode() On eviction Tree VoxelCache Output Scene Acceleration Structure ProcessTriangle() AssembleParents()

52 After some triangles... LOD10 LeafCount=3 TreeCount=0 Leaf Head Tree Head LOD14 LeafCount=0 TreeCount=0 Leaf Head Tree Head LOD15 LeafCount=3 TreeCount=0 Leaf Head Tree Head LOD16 LeafCount=8 TreeCount=0 Leaf Head Tree Head

53 Assembling parents... LOD10 LeafCount=3 TreeCount=0 Leaf Head Tree Head VBNode Pool Add VBNode to linked list of VBNodes for its LOD GenerateVBNode() LOD14 LeafCount=0 TreeCount=0 LOD15 LeafCount=3 TreeCount=0 LOD16 LeafCount=8 TreeCount=0 Leaf Head Tree Head Leaf Head Tree Head Leaf Head Tree Head On eviction Tree VoxelCache Flush Leaf Nodes

54 After parents for one level have been assembled... LOD10 LeafCount=3 TreeCount=0 Leaf Head Tree Head LOD14 LeafCount=0 TreeCount=0 Leaf Head Tree Head LOD15 LeafCount=3 TreeCount=0 Leaf Head Tree Head A B C LOD16 LeafCount=8 TreeCount=0 Leaf Head Tree Head A0 A1 B0 C0 C1 B1 B2 C2

55 Performance Expectations

56 Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array System Memory Interface Pixel Data Master Compute Data Master Data Master Course Grain Scheduler 0 n-1 Texture Unit Inst/ray (512flops peak) Texture Unit n Core Management Memory Cache Unit Tracing Unit 1-2 clk/ray 6 clk/tri 1-2clk/accum Intersection Processor Array Coherency Engine 64 AABB/ray 16 Tri/ray Scene Frame Hierarchy Accumulator Generator Cache System Memory Bus Tiling Coprocessor Pixel Co- Processor 2D Core (PTLA)

57 Get early access to the programming concepts at: Talk immediately after this on Hybrid rendering See the demos at Imagination Booth #402 South Hall

58 QA

59 Thank you