PowerVR Graphics - Latest Developments and Future Plans

Transcription

1 PowerVR Graphics - Latest Developments and Future Plans Latest Developments and Future Plans

2 A brief introduction Joe Davis Lead Developer Support Engineer, PowerVR Graphics With Imagination s PowerVR Developer Technology team for ~6 years PowerVR Developer Technology SDK, tools, documentation and developer support/relations (e.g. this session ) 2

3 Company overview

4 About Imagination Multimedia, processors, communications and cloud IP Driving IP innovation with unrivalled portfolio Recognised leader in graphics, GPU compute and video IP #3 design IP company world-wide* Ensigma Communications Processors MIPS General Processors SoC fabric PowerVR Graphics & GPU Compute Processors PowerVR Video Processors PowerVR Vision Processors 4 * source: Gartner

5 About Imagination Our IP plus our partners know-how combine to drive and disrupt Smart Security Wearables Gaming & VR/AR Advanced Automotive Wearables Retail ehealth Smart homes 5

6 About Imagination Business model Licensees OEMs and ODMs Consumers 6

7 About Imagination Our licensees and partners drive our business 7

8 PowerVR Rogue Hardware

9 PowerVR Rogue Recap Tile-based deferred renderer Building on technology proven over 5 previous generations Formally announced at CES 2012 USC - Universal Shading Cluster New scalar SIMD shader core General purpose compute is a first class citizen in the core while not forgetting what makes a shader core great for graphics 9

10 TBDR Tile-based Tile-based Split each render up into small tiles (32x32 for the most part) Bin geometry after vertex shading into those tiles Tile-based rasterisation and pixel shading Keep all data access for pixel shading on chip 10

11 TBDR Deferred Deferred rasterisation Don t actually get the GPU to do any pixel shading straight away HW support for fully deferred rasterisation and then pixel shading Rasterisation is pixel accurate 11

12 TBDR Bandwidth savings Bandwidth savings across all phases of rendering Only fetch the geometry needed for the tile Only process the visible pixels in the tile Efficient processing Maximize available computational resources Do the best the hardware can with bandwidth 12

13 TBDR Power savings Maximizing core efficiency Lighting up the USC less often is always going to be a saving Minimizing bandwidth Texturing less is a fantastic way to save power Geometry fetch and binning is often more than 10% of per-frame bandwidth Saves bandwidth for other parts of your render 13

14 Rogue USC Architectural Building Block Unified Shading Cluster Basic building block of the Rogue architecture Laid out in pairs, with a shared TPU 1, 0.5 and 0.25 USC designs are special Different balance in the design Tend to find their way into non-gaming applications 14

15 Rogue USC Shader Architecture 16-wide in hardware 32-wide branch granularity We run half a task/warp per clock Scalar SIMD Optimized ALU pipeline Mix of F32, F16, integer, floating point specials, logic ops 15

16 Rogue USC Pipeline datapaths Configurable in the IP core F16 paths were sometimes optional, thankfully not any more F16 paths performance increased significantly after the first generation Performance in your shader F32 paths are dual FMAD F16 paths can do different things per cycle depending on shader ISA is available for you to interrogate though, with disassembling compilers 16

17 Rogue USC Scalar Scalar ALUs Hard to understate what a benefit this is Seems obvious to do, right? Vector architectures are just hard to program well Scalar isn t a free lunch Makes performance a lot more predictable for you 17

18 Rogue USC Programmable output registers The pixel output registers in the ISA are read/write One per pixel Width depends on IP core We expose it programmatically with Pixel Local Storage Worked closely with ARM (thanks, Jan-Harald!) 18

19 Evolution Health Warning: Really Bad Diagrams

20 Rogue Evolution Architecture has changed quite a bit over time Rogue in 2010 still mostly looks like a Rogue today Significant evolutionary changes across the architecture Lots of it driven by developers before the IP is baked Lots of it driven by also analysing your stuff anyway 20

21 PowerVR Series6XT Rogue Host CPU Bus Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array USC0 Texture Unit USC1 Tiling Co-Processor Pixel Data Master Coarse Grain Scheduler ASTC* PVRTC Pixel Co-Processor Compute Data Master USCn-1 Texture Unit USCn 2D Core (TLA) System Memory Bus System Memory Interface Core Mgmt Unit Multi-level Memory Cache Unit (MCU) System Memory Bus * Extra low power GFLOPS Supports both LDR and HDR ASTC formats

22 Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline FLOP ALU core (FP32) FLOP PowerVR Series6XT Unified Shading Cluster Array PowerVR Series6XT USC USC Pipeline FLOP ALU core (FP32) FLOP USC FLOP FLOP ALU core (FP16) ALU core (FP16) FLOP FLOP FLOP FLOP ALU core (FP16) ALU core (FP16) FLOP FLOP Special function FLOP 16 pipelines 8 clusters

23 Series6 to Series6XT Lots of lessons learned Improved scheduler Streamlined ISA Improved compute task efficiency Completely new F16 datapath Improved front-end for sustained geometry performance ASTC 23

24 PowerVR Series7XT Host CPU Bus Host CPU Interface Vertex Data Master Control and Register Bus Unified Shading Cluster Array USC Texture Unit USC Tiling Co-Processor Pixel Data Master Coarse Grain Scheduler ASTC LDR + HDR PVRTC Pixel Co-Processor Compute Data Master USC Texture Unit USC Tessellation Co-Processor System Memory Bus System Memory Interface Core Mgmt Unit Multi-level Memory Cache Unit (MCU) System Memory Bus 2D Core (TLA) Extra low power GFLOPS

25 Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline PowerVR Series7XT Unified Shading Cluster Array PowerVR Series7XT USC USC USC FLOP ALU core (FP32) FLOP Pipeline FLOP ALU core (FP32) FLOP FLOP ALU core (FP16) FLOP FLOP ALU core (FP16) FLOP + Special function FLOP FLOP ALU core (FP16) FLOP FLOP ALU core (FP16) FLOP FLOP 16 pipelines ALU core (FP64) FLOP 2-16 clusters Optional

26 Series6XT to Series7XT Adding features and smoothing off rough edges Changed how the architecture scales Improved USC Streamlined ISA Features Hardware tessellation DX11-compliant USC (precision mainly) FP64 26

27 Into the future Exciting changes being worked on across the architecture USC Front-end Scaling Stuff you want! You can help We love feedback about the architecture and how it could best fit what you re doing Don t be shy 27

28 PowerVR Wizard Ray Tracing Update

29 What is Ray Tracing? Ray tracing is the ability for the shader program for one object to be aware of the geometry of other objects. 29

30 PowerVR Architecture PowerVR Series 6XT Host CPU Bus Host CPU Interface Vertex Data Master Pixel Data Master Compute Data Master Coarse Grain Scheduler Control and Register Bus USC Unified Shading Cluster Array USC Shared Texture Unit USC USC Shared Texture Unit System Memory Interface Core Management Unit Multi-level Memory Cache Unit (MCU) System Memory Bus Tiling Coprocessor Pixel Coprocessor 2D Core (TLA)

31 PowerVR Graphics Wizard Architecture PowerVR GR6500 Host CPU Bus Host CPU Interface Vertex Data Master Pixel Data Master Compute Data Master Ray Data Master Coarse Grain Scheduler Control and Register Bus USC Unified Shading Cluster Array USC Shared Texture Unit USC USC Shared Texture Unit System Memory Interface Core Management Unit Multi-level Memory Cache Unit (MCU) System Memory Bus PowerVR Ray Tracing Unit (RTU) Ray Intersection Processor Coherency Engine Scene Hierarchy Generator Tiling Coprocessor Pixel Coprocessor Frame Accumulator Cache 2D Core (TLA)

32 3 Unique Features of Wizard Fixed-function Ray-Box and Ray-Triangle testers Coherence-Driven Task-Forming and Scheduling Streaming Scene Hierarchy Generator 32

33 Fixed-Function Ray-Box and Ray-Triangle Testers 44x Less Area for Box Testing

34 Coherence-Gathering The Coherency Engine lets us process all these rays at the same time

35 Streaming Scene Hierarchy Generator

36 What is Ray Tracing? Ray tracing is the ability for the shader program for one object to be aware of the geometry of other objects. 36

37 Just a few use cases Hybrid Shadows, Reflections, etc. Augmented Reality Production- Order-Independent Quality Renders Transparency Ambient Occlusion Asset creation / compression Global Illumination Physics & Collision Detection Virtual Reality Lens correction, Ultra-low latency rendering, Lenticular Displays A.I. & Line of Sight Calculations Rapid photoquality output 37

38 GRays/s Ray Tracing Requirements Sustained Ray Throughput at 1080p, 60fps Physics / AI / etc. Technique vs Ray throughput In-Engine Lightmap baking Hybrid, Reflections Hybrid, Soft Shadows, 1 light Dynamic AO Interactive GI, (Light Probes) Lens Effects, e.g. DOF, AA, etc. Fully ray traced game 38

39 PowerVR developer tools

40 PowerVR Tools Asset Optimization Development Debugging and Profiling + PVRGeoPOD PVRTexTool + PVRVFrame PVRShaderEditor PVRShaman + PVRTune PVRTrace PVRMonitor 40

41 PowerVR Tools Release schedule PowerVR Tools release process Minor revision roughly every 6 months Recent/upcoming releases 3.5 SDK (April 2015) 4.0 SDK (due September 2015) 41

42 PVRTrace What is PVRTrace? OpenGL ES API tracer OpenGL ES 1.x, 2.0 and 3.x recording libraries GUI for analysis Features Inspect, analyse and playback captured data 42

43 PVRTrace New render state & data inspectors 43

44 PVRTune What is PVRTune? PowerVR graphics core performance analyser GUI for analysis On-device server Features Real-time performance data 44

45 PVRTune Real-time GPU profiler New counters GPU clock speed, triangles culled, Hidden Surface Removal efficiency, SLC memory reads/writes and more GUI changes Simplified setup and navigation Graphics and Compute modes Tree view for counters (Overview, Tiler, Renderer etc.) 45

46 PVRShaderEditor Shader editor & offline profiler (with disassembly!) 46

47 Rogue graphics driver

48 Rogue graphics driver Release schedule DDK (Driver Development Kit) release process Reference driver source code released to PowerVR IP licensees Minor revision roughly every 6 months Top-tier customers engage early. Drivers in products shortly after official DDK release 48

49 Rogue graphics driver 1.4 DDK Release date Q (release 1) Q (release 2) OpenGL ES: Key features (release 1) OpenGL ES 3.1 Compute shaders, shader storage buffer objects, draw indirect and more OpenGL ES: Key features (release 2) Android Lollipop support 49

50 Rogue graphics driver 1.5 DDK Release date Q2/Q OpenGL ES: Key features Android Extension Pack (AEP) ASTC, blend equation advanced, GPU shader model 5 and more srgb PVRTC Pixel local storage 128/256 bits per-pixel on-chip 50

51 Rogue graphics driver 1.6 DDK Release date Q OpenGL ES: Key features Bicubic texture filtering Shader group vote Polygon offset clamp Pixel local storage 2 Simultaneously write to pixel local storage and a framebuffer attachment 51

52 52

53 Vulkan About What is Vulkan? New open standard API developed by the Khronos group Designed for high-efficiency access to graphics and compute on modern GPUs Key features Minimizes driver overhead and enables multi-threaded GPU command preparation Designed for mobile, desktop, console and embedded platforms Designed for all GPUs - tile based GPUs are first-class citizens! SPIR-V binary intermediate language for shaders 53

54 Vulkan PowerVR driver status PowerVR Vulkan driver Driver development on-going Working with key partners on initial content bring up More details at SIGGRAPH 2015 Khronos BoF: Vulkan, OpenGL, OpenGL ES - 5:30 PM - 7:30 PM 54

55 PowerVR Graphics Future roadmaps What drives our roadmaps? Market analysis Customer feedback Developer feedback 55

56 Upcoming events idc-uk Imagination Developers Connection 2015 UK 1 st October, SOHO Hotel, London UK Register here: Agenda A full developer day including optimization tips, how to use ray tracing with raster graphics and more Also includes guest talks from Google and Digital Legends 56

57 Questions?

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