1 Construct implication chart, one square for each combination of states. 2 Square labeled S i, S j, if outputs differ than square gets X (0).

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1 Advanced Digital Logic Design EECS 33 FSM design overview Teacher: Robert Dick Office: L477 Tech Phone: State diagram for FSM State table Derive variable and output functions Simplify and implement the functions 4 Robert Dick Advanced Digital Logic Design Word description to diagram Sometimes, system specified in way that naturally maps to FSM Sometimes, path from specification to FSM is unclear Transform the specifications so they can naturally be represented as FSMs E.g., regular expression NFA DFA FSM It s fine to go directly to FSM Use transformations when they help you Design a vending machine controller that will release (output signal r) an apple as soon as 3 have been inserted The machine s sensors will clock your controller when an event occurs. The machine accepts only dimes (input signal d) and quarters (input signal q) and does not give change When an apple is removed from the open machine, it indicates this by clocking the controller with an input of d The sensors use only a single bit to communicate with the controller 5 Robert Dick Advanced Digital Logic Design 6 Robert Dick Advanced Digital Logic Design Word description to diagram Word description to diagram We can enumerate the inputs on which an apple should be released For d, i =, for q, i = ddd + ddq + dq + qd + qq d(dd + dq + q) + q(d + q) d(d(d + q) + q) + q(d + q) (( + ) + ) + ( + ) (( + ) + ) + ( + ) X C/ B/ A/ E/ X D/ X 7 Robert Dick Advanced Digital Logic Design 8 Robert Dick Advanced Digital Logic Design State diagram to table Implication chart algorithm next current i= i= output (r) A B E B C D C D D D A A E D D Construct implication chart, one square for each combination of s taken two at a time. 2 Square labeled S i, S j, if outputs differ than square gets X (). Otherwise write down implied pairs for all input combinations. 3 Advance through chart top-to-bottom and left-to-right. If square S i, S j contains next pair S m, S n and that pair labels a square already labeled X (), then S i, S j is labeled X. 4 Continue executing Step 3 until no new squares are marked with X (). 5 For each remaining unmarked square S i, S j, then S i and S j are equivalent. 9 Robert Dick Advanced Digital Logic Design Robert Dick Advanced Digital Logic Design

2 Implication chart minimization Implication chart minimization B BC, DE C BD, DE CD D E BD, DE CD A B C D D any other B C D E A B C D Easy Merge C and E 2 Robert Dick Advanced Digital Logic Design 3 Robert Dick Advanced Digital Logic Design Minimization can be more complicated Incompletely specified Moore reduction Incompletely specified machines are difficult to minimize Therefore, some merges can block others Need a formulation amenable to backtracking s s q A D B B X A X C A X D B C Consider merging A and B or B and C 4 Robert Dick Advanced Digital Logic Design 5 Robert Dick Advanced Digital Logic Design is difficult Assign values to s Keep variable functions and output variable functions simple Allow cubes to be reused among different variable functions Assuming p s and k variables (2 k )! (2 k possible assignments p)! Let s simplify that, assume p is an even power of two and k = lg 2 p then, 2 k = p 7 Robert Dick Advanced Digital Logic Design 8 Robert Dick Advanced Digital Logic Design is difficult Therefore, we have p! (p p)! = p!! = p! / = p! possible assignments...and that s a loose bound p! O (2 p ) has a huge solution space It s also a hard problem Allow the extraction of common cubes for different variable functions State variables States connected by transitions should be adjacent Output functions States with equivalent outputs should be adjacent Heuristic assignment popular Mustang is popular Attraction between s based on ability to extract common cubes 9 Robert Dick Advanced Digital Logic Design 2 Robert Dick Advanced Digital Logic Design

3 State map Can do reasonably good assignment by following guidelines. Make s have adjacent assignments (differing by only one bit) if: They have the same next (child) in the diagram for the same input They have the same previous (parent) in the diagram They have the same output for the same input Recall that Karnaugh maps help us visualize adjacency Use maps to visualize adjacency Recall that we have n s, so we require lg 2 (4) bit variables lg 2 (4) = 2 What if we hadn t done minimization? Five s three variable bits required 2 Robert Dick Advanced Digital Logic Design 22 Robert Dick Advanced Digital Logic Design State map A C E G B D a, b, and c are variable bits A, B, C, etc. are s F H State maps help select adjacent assignments for adjacent s 23 Robert Dick Advanced Digital Logic Design (( + ) + ) + ( + ) X X C/ B/ A/ D/ 24 Robert Dick Advanced Digital Logic Design guidelines States with same child for same input: {B,C} States with same parent: {B,C}, {C,D} States with same output: {A,B,C} Prioritize: {B,C}, {C,D}, {A,B,C}, etc. A B D C 25 Robert Dick Advanced Digital Logic Design 26 Robert Dick Advanced Digital Logic Design Symbolic table State table next current i= i= output (r) A B C B C D C D D D A A next current (j (jk) k + ) i= i= output (r) 27 Robert Dick Advanced Digital Logic Design 28 Robert Dick Advanced Digital Logic Design

4 Logic function definitions State variable and output simplification Use Karnaugh maps (or other methods) to simplify functions j + (j,k,i) k + (j,k,i) r(j, k) 3 Robert Dick Advanced Digital Logic Design 3 Robert Dick Advanced Digital Logic Design State variable and output simplification State variable and output simplification 32 Robert Dick Advanced Digital Logic Design 33 Robert Dick Advanced Digital Logic Design Implementation Moore block diagram outputs combinational logic Implement the variable functions in combinational logic Use sequential elements along feedback paths Implement the output variable functions in combinational logic sequential elements feedback combinational logic inputs 34 Robert Dick Advanced Digital Logic Design 35 Robert Dick Advanced Digital Logic Design Mealy block diagram with Don t-cares outputs sequential elements combinational logic feedback Can use advanced technique introduced in previous lecture Find the maximal compatibles Use these to generate the prime compatibles Write expression in POS form Multiply to get SOP form Formulate as a binate covering problem This technique is optimal but difficult for incompletely specified machines is a hard problem inputs 36 Robert Dick Advanced Digital Logic Design 38 Robert Dick Advanced Digital Logic Design

5 Incompletely specified Moore reduction Maximal compatibles s + s q A D B B X A X C A X D B C B C D AB A B C Choosing the compatible sets is not straight-forward Some combinations block potential future combinations Know conflicting s from the compatibility table From Hachtel and Somenzi s Logic Synthesis and Verification Algorithms 39 Robert Dick Advanced Digital Logic Design 4 Robert Dick Advanced Digital Logic Design Compatibles and implications Class sets B C D AB A B C {C, D}, {B, C}, {A, B} The combination of a pair of s may require the combination of another pair Thus, using the maximal compatibles is insufficient Need additional prime compatibles that have smaller class sets Starting from the maximal compatibles, which are primes, generate other primes In order of decreasing compatible size, if the compatible has a non-empty class set, enter all subsets that are not already contained in other prime compatibles with empty class sets in the table 4 Robert Dick Advanced Digital Logic Design 42 Robert Dick Advanced Digital Logic Design Prime compatibles Prime compatible selection B C D AB A B C A, B B, C C, D AB D Once the prime compatibles are known, it is necessary to select a subset that Has minimal number of selected prime compatibles Covers all s Would be unate covering Contains all class sets implied by the selected prime compatibles This makes it binate covering Recall unate covering, similar solution works Branch and bound 43 Robert Dick Advanced Digital Logic Design 44 Robert Dick Advanced Digital Logic Design Binate covering {C,D} {A,B} {C,D} + {A,B} {A,B} need to include A ({A,B} + {B,C}) need to include B ({B,C} + {C,D}) need to include C ({C,D} + {D}) need to include D ({C,D} + {A,B}) {C, D} class set requirements 45 Robert Dick Advanced Digital Logic Design Binate covering J = {A, B} J 2 = ({A,B} + {B, C}) J 3 = ({B,C} + {C,D}) J 4 = ({C,D} + {D}) J 5 = ({C,D} + {A,B}) term prime compatible A, B B, C C, D D J J 2 J 3 J 4 J 5 46 Robert Dick Advanced Digital Logic Design

6 Binate covering Additional examples term prime compatible A, B B, C C, D D J J 2 J 3 J 4 J 5 CS NS(I) Out A A C B B B X C A C Find a set of columns, S, such that, for every row A -column in the row is in S or......a -column in the row is not in S 47 Robert Dick Advanced Digital Logic Design 48 Robert Dick Advanced Digital Logic Design Today s Topics General CAD references FSM design example (trying to use more examples) with don t-cares If you will be working in digital circuit design, bookmark these sites Designers talk about the current of CAD and circuit design Electronics design trade journal Won t find current research Will find industry trends 49 Robert Dick Advanced Digital Logic Design 5 Robert Dick Advanced Digital Logic Design Recommended reading Next lecture Jayaram Bhasker. A VHDL Primer. Prentice-Hall, NJ, 992 Chapter Chapter 2 Design representations VHDL for combinational and sequential systems 52 Robert Dick Advanced Digital Logic Design 53 Robert Dick Advanced Digital Logic Design

Advanced Digital Logic Design EECS 303

Advanced Digital Logic Design EECS 303 http://ziyang.eecs.northwestern.edu/eecs303/ Teacher: Robert Dick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 Outline 1. Finite state machines