Routing. Routing. Routing in design flow. Problem. Objectives

Transcription

1 Routing Routing Problem Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect the terminals of the nets Levels of abstraction: o Global routing o Detailed routing Objectives Cost components: o Area (channel width) min congestion in prev levels helped o Wire delays timing minimization in previous levels o Number of layers (fewer layers less expensive) o Additional cost components: number of bends, vias [Bazargan] 2 Routing in design flow B A C Netlist INV AND OR Routing Floorplan/Placement 3

2 The Routing Problem Apply it after floorplanning/placement Input: Netlist Timing budget for, typically, critical nets Locations of blocks and locations of pins Output: Geometric layouts of all nets Objective: Minimize the total wire length, the number of vias, or just completing all connections without increasing the chip area. Each net meets its timing budget. 4 Routing Constraints Examples: Placement constraint Number of routing layers Delay constraint Meet all geometrical constraints (design rules) Physical/Electrical/Manufacturing constraints: o Crosstalk o Process variations, yield, or lithography h issues? 5 Top view Routing Anatomy 3D view Symbolic Layout Metal layer 3 Via Metal layer 2 Metal layer [Bazargan] Note: Colors used in this slide are not standard 6 2

3 Global vs. Detailed Routing Global routing Input: detailed placement, with exact terminal locations Determine channel (routing region) for each net Objective: minimize area (congestion), and timing (approximate) Detailed routing Input: channels and approximate routing from the global routing phase Determine the exact route and layers for each net Objective: valid routing, minimize area (congestion), meet timing constraints Additional objectives: min via, power [Bazargan] Figs. [ Sherwani] 7 Routing Environment Chip architecture Full-custom: o No constraint on routing regions Standard cell: o Variable channel height? o Feed-through cells connect channels FPGA: o Fixed channel height o Limited switchbox connections o Prefabricated wire segments have different weights [Bazargan] Channel Tracks Feedthroughs Failed net Failed connection Figs. [ Sherwani] 8 Taxonomy of VLSI Routers Routers Global Detailed Specialized Graph Search Steiner Iterative Maze Restricted River Switchbox Channel General Purpose Maze Line Probe Line Expansion Power/Gnd Clock Hierarchical Greedy Left-Edge [Bazargan] [ Keutzer] 9 3

4 Global Routing Stages Routing region definition Routing region ordering Steiner-tree / area routing Grid Tiles super-imposed on placement Regular or irregular Smaller problem to solve, higher level of abstraction Terminals at center of grid tiles Edge capacity Number of nets that can pass a certain grid edge (aka congestion) On edge E, Capacity(E ) Congestion(E ) [Bazargan] [ Sarrafzadeh] M2 M M3 0 Grid Graph Coarse or fine-grained Vertices: routing regions, edges: route exists? Weights on edges How costly is to use that edge Could vary during the routing (e.g., for congestion) Horizontal / vertical might have different weights t t2 t3 t4 t t2 t3 t4 t t2 t3 t4 2 2 [Bazargan] [ Sherwani] Global Routing Graph Search Good for two-terminal nets Build grid graph (Coarse? Fine?) Use graph search algorithms, e.g., Dkstra Iterative: route nets one by one How to handle: Congestion? Critical nets? Order of the nets to route? Net criticality Half-perimeter of the bounding box Number of terminals [Bazargan] 2 4

5 Maze Routing 3 Maze Routing Problem Given: A planar rectangular grid graph. Two points S and T on the graph. Obstacles modeled as blocked vertices. Objective: Find the shortest path connecting S and T. This technique can be used in global or detailed routing (switchbox) problems. 4 Grid Graph S T S X X T S X X T Area Routing Grid Graph (Maze) Simplified Representation 5 5

6 Maze Routing S T 6 Lee s Algorithm: Basic Idea An Algorithm for Path Connection and its Application, C.Y. Lee, IRE Transactions on Electronic Computers, 96. A Breadth-First Search (BFS) of the grid graph. Always find the shortest path possible. Consists of two phases: Wave Propagation Retrace 7 Maze routing Problem: find a connection from A to B A B Different grid boundaries may have different costs Quite useful for two pin nets, rip-up-and-reroute, etc. 8 6

7 Lee s algorithm T S A more space-efficient version Global Routing Maze Routing Similar to breadth-first search Very simple algorithm Works on grid graph Time complexity: grid size (NxN) Algorithm Propagate a wave from source s until hit the sink (implemented using a queue) Trace back to find the path Guaranteed to find the optimal solution Usually multiple optimal solutions exist More than two terminals? For the third terminal, use the path between the first two as the source of the wave [Bazargan] 5 5 t

8 Schemes to Reduce Run Time. Starting Point Selection: T S S T 2. Double Fan-Out: 3. Framing: S T S T 22 Multi-Terminal Nets For a k-terminal net, connect the k terminals using a rectilinear Steiner tree with the shortest wire length on the maze. This problem is NP-Complete. Just want to find some good heuristics. 23 Multi-Terminal Nets This problem can be solved by extending the Lee s algorithm: Connect one terminal at a time, or Search for several targets simultaneously, or Propagate wave fronts from several different sources simultaneously. 24 8

9 Extension to Multi-Terminal Nets st Iteration S 0 2 T T 3 2nd Iteration S S S S T Maze Routing Key to popularity: Simplicity Guaranteed to find the optimal solution Can realize more complex cost functions too (e.g., number of bends in a path) Weakness: Multiple terminals not handled efficiently Dependent on grid, a two dimensional data structure Different variations exist Soukup s alg: o First use DFS, when get to an obstacle, use BFS to get around o No guarantee to find the shortest path [Bazargan] 26 BFS based Maze Routing (A*) Need to search whole space? Guide the search to the goal explicitly A* search is faster if you need good path, not perfect path Use priority queue C(n) = F(n)+H(n) o F(n) is a computed cost from source to current location. o H(n) is a predicted cost from current location to target. o If H(n)=0, it becomes maze routing! Optimal (shortest path) when H(n) <= H (n) (no overestimation) o H (n) is the exact cost o H(n)=0 never overestimates! 27 9

10 Maze vs A* routing (I) 28 Maze vs A* routing (II) 29 Multiple Terminal Nets: Steiner Tree Steiner tree (aka Rectilinear Steiner Tree RST): A tree connecting multiple terminals o Original points: demand points set D o Added points: Steiner points set S Edges horizontal or vertical only Steiner Minimum Tree (SMT) Similar to minimum spanning tree (MST) But finding SMT is NP-complete Many good heuristics introduced to find SMT Algorithm Find MST Pass horizontal and vertical lines from each terminal to get the Hannan grid (optimal solution is on this grid) Convert each edge of the MST to an L-shaped route on Hannan grid (add a Steiner point at the corner of L) [Bazargan] 30 0

11 Steiner Tree Based Algorithms For multi-terminal nets. Find Steiner tree instead of shortest path. Construct a Steiner tree from the minimum spanning trees (MST) 3 Steiner Tree Heuristics (Contd.) Separable MST s MST with the property that bounding boxes of nonadjacent edges must not overlap Can show that a separable MST always exists Procedure: Find separable MST Use dynamic programming to maximize overlap O(n) algorithm Worst-case: 3/2 factor Nonseparable Separable J. M. Ho, G. Vayan and C. K. Wong, New algorithms for the rectilinear Steiner tree problem, IEEE Trans. Comput.-Aided Design, Vol. 9, pp , February Steiner Tree Hannan grid reduces solution space (smaller grid) For min length RST, Steiner points always on Hannan grid Convert MST to rectilinear paths Length bounded by.5 times optimal SMT length Use alternate L routes to find the minimum tree Steiner point MSP (length=) Error here: this length should be > Steiner tree length [Bazargan] Steiner tree (len=3) [ Sherwani] 33

12 Steiner Tree Routing Can apply different costs to different regions (or horizontal/vertical preference) Order of the nets Sequential o Use # of terminals, criticality, etc. to determine order Parallel o Divide the chip into large regions, perform the routing in parallel Key to popularity Fast (not theoretically, but practically) Bounded solution quality Shortcomings Difficult to predict or avoid congestion [Bazargan] 34 Steiner Tree Heuristics Iterated -Steiner heuristic (Not based on MST/SMT ratio) In each iteration, add one Steiner point o Consider all O(n 2 ) candidate Steiner points o Construct MST s for each one and choose the mincost point o Cost = O(n 2 ) O(n log n) = O(n 3 log n) per -Steiner point o Number of Steiner points = O(n) Alternative approach (Georgakopoulous/Papadimitriou) o O(n 2 ) cost per -Steiner point Performance: within a factor of 4/3 of optimal for Steiner trees that are unions of pluses (instead of 3/2) For details, see A. B. Kahng and G. Robins, On Optimal Interconnections for VLSI, Kluwer Academic Publishers, 995, and references therein. 35 Global Routing Approaches A combination of different approaches might be used in chip-level routing Route simple nets (2-3 pins in local area) directly (e.g., L-shaped or Z-shaped) Use close to optimal Steiner Tree algorithms to route nets of intermediate length Route remaining big nets using a maze router Ordering Some ordering is chosen, if can route all, then done, otherwise: Rip-up and Re-route [Bazargan] [ Keutzer] 36 2

13 Motivation Can now build a global route for a single net Problem Actual routing cost depends on other nets (congestion, criticality, etc.) Possibilities o Route the nets one by one - suboptimal o Route them simultaneously Ideal algorithm: optimal Real algorithm that works in a reasonable time: not guaranteed optimal, but less suboptimal than routing the nets one by one 37 Congestion 38 Measuring congestion Importance of congestion Possible transformations to reduce congestion Rerouting Changing the placement Resynthesis Important t issue: prediction of congestion Accuracy of the predictor depends on how much information is available 39 3

14 Introduction Congestion prediction Evaluation of Floorplans Fast Useful within Placers or Routers Floorplanning Placement Routing Congestion Prediction [Westra] 40 A simple predictor Consider a region with G gates that communicate with the rest of the system through T terminals If the boundary is perturbed to add G more gates, the number of extra terminals T could reasonably be predicted as T/G =p(t/g) p corresponds to the fact that some of the new connections will be intra-block, so that p <. Write as a differential equation dt/dg = p (T/G) i.e., dt/t = p dg/g T = t.g p G gates 4 Rent s rule A predictor for interconnect wires corresponding to a cell/block T = A G p T = number of terminals G = number of gates in the block A = constant p = constant (Rent s exponent) Based on the idea of self-similarity 42 4

15 Typical Rent s curve Region II does not follow the rule because of external I/O limitations [Christie and Stroobandt, TVLSI 2/00] 43 Example: applying Rent s rule Three blocks of gates: A, B, C with T A, T B, T C terminals, respectively A T A +T B +T C =T AtoC +T AtoB +T BtoC +T ABC i.e., T AtoC = T A +T B +T C -T ABC -T AtoB -T BtoC T AtoB = T A +T B -T AB T BtoC = T B +T C -T BC C This implies that T AtoC = T AB + T BC T B T ABC = A[(G A +G B ) p + (G B +G C ) p G Bp (G A +G B +G C ) p ] n AtoC = T AtoC where = ½ for a two-pin net = more (e.g., k/k+) for a k-pin net, k>2 44 Estimating congestion with more information Given a rectangular grid with cells of size WxH Horizontal capacity = H all layers (/L hi ) Vertical capacity = W all layers (/L vi ) L hi [L vi ] = horizontal [vertical] pitch in layer I Assumptions All nets are routed with the shortest length (no detours) All nets make at most one change of direction per grid No change of direction in the grid with pins Two-pin net model: assume first Pins at lower left and upper right corner of bounding box Bounding box is at least 2 rows, 2 columns No routing blockages 45 5

16 Example Six routes between the two points Lower middle grid 3 routes Route : horiz track, 0 vert tracks Routes 2, 3: ½ horiz, vertical Total : 2 horiz, 2 vert Probabilistically o 6 routes in all /3 horiz, /3 vert usage in this grid Can construct a probabilistic usage matrix (,) (2,2) 6 (3,3) (2,2) (2,2) (2,2) (3,3) (2,2) (,) 46 Calculating the total # routes F(m,n) = number of routes in an mxn grid F(m,) = F(,n) = F(m,n) = F(m-,n)+F(m,n-) Can calculate F(m,n) as: F(m,n) = n = m n = 2 j(n-2)=tom j(n-3)=toj(n-2) j=toj2 j n 3 Can similarly derive a recursive equation for the usage, and therefore find the usage probability matrix 47 Another interpretation Alternative [simpler] expression (m+)x(n+) grid Need to traverse a distance n+m Need to take n horizontal steps corresponds to n+m C n possibilities Can also interprete as: need to take m vertical steps corresponds to n+m C m possibilities; n+m C m = n+m C n Comparison with previous expression F(m,n) = F(m-,n)+F(m,n-) n+m C m = n+m- C n + n+m- C n- [easy to show] 48 6

17 Counting paths in the presence of blockages Can generalize the previous method The dual of a grid is a grid graph In the presence of blockages: remove corresponding edges Counting the number of paths: can be done by graph traversal However, this is not a closed form expression now! 49 Previous work / Motivation Lou et al.: Estimating Routing Congestion using Probabilistic Analysis ISPD 200 Buckets have fixed capacity Consider all detour-free paths Spread net over paths with equal probability [Westra] 50 Previous work / Motivation cont d 5x5 grid: 70 detour-free paths Consider as bitstring: 0000 #permutations = (m+n-2)! (m-)! (n-)! = Horizontal usage Vertical usage (max) usage [Westra] 5 7

18 Model (max) usage Previous work / Motivation cont d Reality Most density around diagonal Most density on edges!!! [Westra] 52 Routing statistics 6 benchmarks, up to nets, buckets Wirelength minimization: detoured:.40% Via minimization: #bends>2:.2% %nets x2 L-shapes Z-shapes R #segments ( )box > 2x2 #Ls α = ( ) #Ls + #Zs 0.50 α 0.67 α = 0.60 Only L- and Z-shapes matter! [Westra] 53 create empty maps foreach net n do pin-pairs MST(n) end foreach pin-pair pp do if pp is short do add short-usage(pp) elseif pp is flat do add flat-usage(pp) else do add α L-usage(pp) add (-α) Z-usage(pp) end end Algorithm [Westra] 54 8

19 Probabilistic usages U h = x right W bucket U h = U v = y total W bucket w n U h = x W bucket U v = ½ v y bottom H bucket U v = ½ w n = 3 U h = 0 [Westra] 55 Probabilistic usages cont d x = U h consists of two terms: Bend Bend to the right Two orientations: #Z v = w n -2 #Z h = h n -2 U h = Uv = wn -2 w n -2 ½ + y top H bucket w n -x-2 w n -2 U v = wn -2 [Westra] scale factor: w#z n -2 v #Z w n v +h+ n #Z -4 h 56 Results Prediction Global routed Detailed routed [Westra] 57 9

20 Results experiment prediction-global prediction-detailed global-detailed %buckets %error %buckets %error %buckets %error [Westra] 58 Results experiment 2 prediction-global prediction-detailed global-detailed %buckets %error %buckets %error %buckets %error [Westra] 59 Blockages Spread usage over surrounding buckets weight = 2 -d n Line blockages: break net up Too many / too complex blockages? Forget it! [Westra] 60 20

21 Extraction and Timing Analysis After global routing and detailed routing, information of the nets can be extracted and delays can be analyzed. If some nets fail to meet their timing budget, detailed routing and/or global routing needs to be repeated Net Ordering In sequential approach, we need some net ordering. A bad net ordering will increase the total wire length, and may even prevent com-pletion of routing for some circuits which are indeed routable. A B A B B A B first (Good order) B A A first (Bad order) 63 2

22 Criteria for Net Ordering Criticality of net - critical nets first. Estimated wire length - short nets first since they are less flexible. Consider bounding rectangles (BR): A B B A B is in A s BR Which one should be routed first and why? (Note that this rule of thumb is not always applicable.) 64 Net Ordering (cont d) 65 Rip-Up and Re-route It is impossible to get the optimal net ordering. If some nets are failed to be routed, the rip-up and re-route technique can be applied: Cannot route C So rip-up B and route C first. Finally route B. A A A A A A B B B B B B C C C C C C 66 22

23 Typical routing graph Routing region tessellated into a number of tiles Routing graph as shown below, superimposed over tiling Each boundary has a capacity 67 Flow-based methods Formulate problem as a multicommodity flow problem Illustrate on two-pin nets (Shragowitz and Keel, 987) Each net corresponds to transporting a flow from the source to the sinks A demand of unit is to be shipped from the source to the destination along multiple possible routes 68 Flow based methods (Contd.) Formulation Each edge e has a cost c(e) and a capacity u(e) Constraints o Sum of flows through an edge should not exceed capacity o Flow preservation (what goes in must equal what comes out) o 0- constraints on flows Formulation 69 23

24 Concurrent Approach Consider all the nets simultaneously. Formulate as an integer program. Given: Nets net : : net n Set of possible routing trees T, T 2,..., T k : : T n, T n2,..., T nkn L = Total wire length of T C e = Capacity of edge e Determine variable x s.t. x = if T is used x = 0 otherwise. 70 Integer Program Formulation Min. st s.t. n ki i j ki j i, j x x L x s.t. e T 0 or x C for all i,, n e i, j for all edge e 7 Concurrent Approach: Example Solution 3 2,2 a b,3 d Possible trees: net : ,3 c,2 net 2: C a = C b = C c = C d =2 net 3: 2 2 Min. 2x 3x 2 3x 3 2x 3x 3x 2x x x2 x3 ; x2 x22 x23 ; What are the constraints s.t. x3 x32 ; for edge capacity? x 0 or i, j; x2 x3 x2 x23 x x C a

25 Integer Programming Approach Standard techniques to solve IP. No net ordering. Give global optimum. Can be extremely slow, especially for large problems. To make it faster, a fewer choices of routing trees for each net can be used. May make the problem infeasible or give a bad solution. Determining a good set of choices of routing trees is a hard problem by itself. 73 Hierarchical Approach to Speed Up Integer Programming Formulation For Global Routing M. Burstein and R. Pelavin, Hierarchical Wire Routing, IEEE TCAD, vol. CAD-2, pages , Oct Hierarchical Approach Large Integer Programs are difficult to solve. Hierarchical Approach reduces global routing to routing problems on a 2x2 grid. Decompose recursively in a top-down fashion. Those 2x2 routing problems can be solved optimally by integer programming formulation

26 Hierachical Approach: Example Solving a 2xn routing problem hierarchically. Level Level 2 Level 3 Solution: 76 Types of 2x2 Routing Problems Type Type 7 Type 2 Type 8 Type 3 Type 9 Type 4 Type 0 Type 5 Type Type 6 77 Objective Function of 2x2 Routing Possible Routing Trees: T, T 2, T 2, T 22,..., T,,..., T,4 # of nets of each type: n,..., n Determine x : # of type-i nets using T for routing. y: i # of type-i nets that fails to route. yi x,, j ni i Want to minimize y. i i 78 26

27 B ab C a B da C b a b c d C d Constraints of 2x2 Routing B bc C c B cd Constraints on Edge Capacity: x C i, j s.t. at i, j s.t. bt i, j s.t. ct i, j s.t. dt a x C b x C c x C Constraints on # of Bends in a Region: i, j s.t. T has a bend in region ab i, j s.t. T has a bend in region bc i, j s.t. T has a bend in region cd i, j s.t. T has a bend in region da d x B ab x B bc x B cd x B da 79 Pop Quiz If you have two nets, one with 2 pins, the other with 4 pins with a zero capacity edge What is going to be the result? C= C=0 y i j x n Want tominimize i i,, i i y. Type Type 80 ILP Formulation of 2x2 Routing Min. y i i s.t. yi x ni i j,, x 0, y 0 i, j i, i, j s.t. at i, j s.t. bt i, j s.t. dt i j s.t. ct x C a x C b x C c x C d i, i, j s.t. T has a bend in region ab i, j s.t. T has a bend in region bc j s.t. T has a bend in region cd i, j s.t. T has a bend in region da x B ab x B Only 39 variables (28 x and y i ) and 9 constraints (plus 38 non-negative constrains). Problems of this size are usually not too difficult to solve. bc x B cd x B da 8 27

28 Buffered Interconnects 82 Buffer insertion Consider Vs A buffer effectively isolates the downstream capacitance 83 Intuition behind adding buffers l Wire resistance = a.l Wire delay = a.b.l 2 Wire capacitance = b.l l l 2 l 3 l n Now, wire delay = a.b.l i 2 < a.b.l 2 since a.b.(l 2 + l l n2 )< a.b.(l + l l n ) 2 Weaknesses in the argument? Buffer R, C, intrinsic delay discounted 84 28

29 RATs RAT = required arrival time at a node of the tree We called this RT earlier in the class 85 Simple Buffer Insertion Problem Given: Source and sink locations, sink capacitances and RATs, a buffer type, source delay rules, unit wire resistance and capacitance Buffer RAT 4 RAT 3 s 0 RAT RAT 2 86 Simple Buffer Insertion Problem Find: Buffer locations and a routing tree such that slack at the source is minimized q( s0) min i4{ RAT ( si ) delay( s0, si )} RAT 4 RAT 3 s 0 RAT 2 RAT 87 29

30 Slack Example slack = -200 RAT = 500 delay = 400 RAT = 400 delay = 600 slack = +00 RAT = 500 delay = 350 RAT = 400 delay = RC delay calculations Delays can be calculated easily For example: RC driven by a step excitation R V(t) C Response V(t) = ( - e -t/rc ) Time constant = RC Time constants for more complicated circuits? 89 Elmore delay for an RC tree T D, k R C i j ipath( k ) jdownstream ( i) Rd Rb Cd Root Ra Cb Re Ca Rc Ce Cc Elmore Delay to node e = Ra.(Ca+Cb+Cc+Cd+Ce) + Rb.(Cb+Cd + Ce) + Re.Ce 90 30

31 Elmore Delay R R A B C 2 C C ( C C2) Delay( A C) R R C Optimizing medium/long interconnects Delays of interconnects may become very large Wire sizing helps to control the delay Repeater insertion is another effective technique Effects of a buffer Isolates load capacitances of different stages Adds a delay Subtree capacitance C L C buf Subtree capacitance C L2 Downstream capacitance here is C L2 + C buf (C L is isolated by the buffer) 92 Common Approaches Iteratively insert buffers Closed-form solutions (2 pin nets) Dynamic programming Simultaneous constructions 93 3

32 Van Ginneken s Classic Algorithm Optimal for multi-sink nets Quadratic runtime Bottom-up from sinks to source Generate list of candidates at each node At source,,pick the best candidate in list 94 Key Assumptions Given routing tree Given potential insertion points 95 Generating Candidates () (2) (3) 96 32

33 Dynamic Programming Approach Traverse the tree bottom-up At each step, consider adding a buffer If buffer placement is provably suboptimal, discard this combination Otherwise, store all non-suboptimal combinations and proceed up in the tree Basic step k Required time R k = min(t i -D i ) o D i = delay spec at a sink i? o T i = actual delay from node k to i in partial tree Subtree T Subtree T 2 97 Combining Two (or more) Trees If a buffer is inserted Load L k = C buf + c.l T k = min(t desc ) [D buf + R buf L desc + r.c.l 2 /2] If no buffer is inserted Load L k = L desc + c.l T rcl k = min(t desc ) [r.l. L desc + r.c.l 2 /2] Delay of buffer+wire Delay of wire, no buffer k? L k T k Subtree T Subtree T 2 98 Combining the Options Draw a plot of all (L k, T k ) pairs for both children (assuming binary tree)? T m T n L(n) L(combined) L(m) T(n) T(m) T(combined)

34 Pruning Candidates (3) (a) (b) Both (a) and (b) look the same to the source. Throw out the one with the worst slack (4) 00 Candidate Example Continued (4) (5) 0 Candidate Example Continued After pruning (5) At driver, compute which candidate maximizes slack. Result is optimal

35 Merging Branches Left Candidates Right Candidates 03 Pruning Merged Branches Critical With pruning 04 Van Ginneken Example Buffer C=5, d=50 C=5, d=30 (45, 50) (5, 0) (20,00) (5, 70) Buffer C=5, d=30 (30,250) (5, 220) Wire C=5,d=200 C=5,d=20 (30,250) (5, 220) Wire C=0,d=50 (20,400) (20,400) (20,400) 05 35

36 Van Ginneken Example Cont d (45, 50) (5, 0) (20,00) (5, 70) (30,250) (5, 220) (20,400) (5,0) is inferior to (5,70). (45,50) 50) is inferior to (20,00) Wire C=0 (30,0) (5, -0) (20,00) (5, 70) (30,250) (5, 220) (20,400) Pick solution with largest slack, follow arrows to get solution 06 Van Ginneken Recap Generate candidates from sinks to source Quadratic runtime Adding a buffer adds only one new candidate Merging branches additive, not multiplicative Optimal for Elmore delay model 07 Optimal Extensions Multiple buffer types Inverters Polarity constraints Controlling buffer resources Capacitance constraints Blockage recognition Wire sizing 08 36

37 Multiple Buffer Types () (2) Time complexity increases from O(n 2 ) to O(n 2 B 2 ) where B is the number of different buffer types 09 Inverters () (2) Maintain a + and a - list of candidates Only merge branches with same polarity Throw out negative candidates at source 0 Polarity Constraints Some sinks are positive, some negative Put negative sinks into - list - list - list + list 37

38 Controlling Buffering Resources Before, maintain list of capacitance slack pairs (C, q ), (C 2, q 2 ), (C 3, q 3 ) (C 4, q 4 ), (C 5, q 5 ) (C 6, q 6 ), (C 7, q 7 ), (C 8, q 8 ) (C 9, q 9 ) Now, store an array of lists, indexed by # of buffers (C, q, 3), (C 2, q 2, 3), (C 3, q 3, 3) (C 4, q 4, 2), (C 5, q 5, 2) (C 6, q 6, ), (C 7, q 7, ), (C 8, q 8, ) (C 9, q 9, 0) Prune candidates with inferior cap, slack, and #buffers 2 Buffering Resource Trade-off 000 (ps) Slack # of Buffers 3 Capacitance Constraints Each gate g drives at most C(g) capacitance When inserting buffer g, check downstream capacitance. If bigger than C(g), throw out candidate Total cap = 500 ff 4 38

39 Blockage Recognition Delete insertion points that run over blockages 5 Other Extensions Simultaneous driver sizing Modeling effective capacitance Higher-order interconnect delay Slew constraints Noise constraints 6 Driver Sizing 7 39

40 Driver Sizing Driver behaves like buffer Pick driver with the best slack Implications upstream in timing graph Delay penalty for large input capacitance 8 -Models Van Ginneken candidate: (Cap, slack) R C C n C f Replace Cap with -model (C n, R, C f ) Total capacitance preserved: C n + C f = C R represents degree of resistive shielding 9 Computing Gate Delay When inserting buffer, compute effective capacitance from -model C eff Use effective instead of lumped capacitance in gate delay equation Optimality no longer guaranteed 20 40

41 Extensions Recap Multiple buffer types, including inverters Polarity constraints Controlling buffer resources Slew, capacitance, and noise constraints Blockage recognition Driver sizing Higher-order delay modeling Wire sizing 2 4