A fixed-point 3D graphics library with energy-efficient efficient cache architecture for mobile multimedia system

Transcription

1 MS Thesis A fixed-point 3D graphics library with energy-efficient efficient cache architecture for mobile multimedia system Min-wuk Lee Semiconductor System Laboratory Department Electrical Engineering and Computer Science Korea Advanced Institute of Science and Technology [KAIST] Min-wuk Lee 1

2 Introduction Motivation Outline MobileGL: Mobile 3D graphics library Energy-efficient CPU cache Energy-efficient texture cache Conclusion Min-wuk Lee 2

3 Introduction(1/2) Embedded mobile system Mobile 3D graphics system Optimized code for speed Draw off the best H/W performance Model Interface Transformation Gouraud Shading Depth Compare Input Software system Hardware system Output Lighting Perspective Projection Screen Clipping Alpha Blending Triangle Setup Texture Mapping Low energy consumption Good quality, high performance Model CPU MobileGL 3D Rendering Engine Memory Pixel Performance-energy co-optimization for mobile 3D graphics Software system : High speed graphics library (MobileGL) Hardware system : Energy-efficient Cache architecture Min-wuk Lee 3

4 Target system Introduction(2/2) Application processor Graphics library CPU cache Mem Low-cost target Application processor Graphics library CPU cache Texture cache Frame cache Depth cache 3D graphics SoC Low-cost target High speed graphics library Energy-efficient CPU cache system High quality target High speed and good quality graphics library Energy-efficient CPU cache, texture cache system R.E. System bus controller High quality target Mem Min-wuk Lee 4

5 For low-cost target Previous work PC, workstation platform graphics library Too huge GL supported by FPU, special graphics engine Embedded platform graphics library : Fixed point arithmetic Yoshida s work[1] Limited operation (Without texturing) No research on memory bandwidth bottleneck Previous work in our group Analysis with memory-only, without cache system For high quality target Texture cache in PC platform Hakura s work[2] Analysis based on miss rate Did not consider energy, execution time, system limitation [1] : K.Yoshida, Consumer Electronics, IEEE Transactions on,1998. [2] : Ziyad s. Hakura, ISCA,1997. Min-wuk Lee 5

6 Motivation Graphics library of this work Extended operation Lighting, Texturing, Alpha blending, Face culling, etc. Optimization of memory transaction 3D graphics characteristic Analysis with cache system Texture cache of this work Energy-efficient texture cache in embedded system With negligible performance degradation Min-wuk Lee 6

7 Introduction Motivation Outline MobileGL: Mobile 3D graphics library Energy-efficient CPU cache Energy-efficient texture cache Conclusion Min-wuk Lee 7

8 Mobile 3D graphics library A fixed-point arithmetic 32bit integer Optimized memory transaction To reduce instruction and data traffic Selective pipeline Applications To reduce branch 45KB total code size MobileGL(1/6) Model Lighting enable Lighting disable View transformation Lighting Perspective projection Clipping Perspective division Screen mapping Cull face Rendering stage Lighting and Texturing Lighting only Pixel View transformation X Perspective projection Clipping Perspective division Screen mapping Cull face Rendering stage Texture-only Include r,g,b,a calculation Exclude r,g,b,a calculation MobileGL block diagram Min-wuk Lee 8

9 MobileGL(2/6) Disabling option for perspective correction of texture address Due to small screen size Trade-off between correctness and speedup View transformation X Perspective projection Clipping /Perspective divison u,v/ w u,v On Off Screen mapping Cull face Triangle setup execution time /1K Polygons % reduction Horizontal setup 0 Pixel interpolation u,v/w u,v Triangle setup Horizontal setup Texturing Conventional This work StrongARM at 200 MHz Min-wuk Lee 9

10 MobileGL(3/6) Division reduction in interpolation Use shift instead of reciprocal High probability of 1,2 or 4 in denominator value 1st Top Direction_y 1 Mid Line1 3rd Line3 Line2 start Line4 Direction_x end Bot 2nd is 1, 2 or 4, using shift Execution time(ms) per 1000 Polygons ROD Triangle setup Horizontal setup Texturing 27 % reduction 200 MHz Min-wuk Lee 10

11 Z comparison in advance To avoid unnecessary shading and texturing[3] MobileGL(4/6) Selective precision of matrix multiplication 67% stage #2 #1 Unnecessary operation for #2 Should extend to 64bit for result 32 bit 4bit A Texturing Depth test Blending Standard OpenGL pipeline 64 bit B A MULL B Depth test Texturing Blending Z comparison in advance 32 bit 4bit Speed improvement A Z_fail / Z_access B (%) A MUL B [3] : Ramchan Woo, ISSCC 2003 Min-wuk Lee 11

12 Library performance MobileGL(5/6) 67K texture only application due to several optimization steps Original C code 67K Polygons/sec Polyons / milli sec Optimized code 6.7 times Performance improvement 0 80MHz 200MHz 200MHz Previous work[1] Min-wuk Lee 12

13 Implementation result MobileGL(6/6) Min-wuk Lee 13

14 Introduction Motivation Outline MobileGL: Mobile 3D graphics library Energy-efficient CPU cache Energy-efficient texture cache Conclusion Min-wuk Lee 14

15 Energy-efficient efficient CPU cache (1/4) Simulation environment Application Programs 3D Graphics Library From ARM SDK : 1, memory transaction From cache model using memory transaction : 2, 3 ARM SDK ARM Processor Memory CPU execution time Memory transaction file CACHE_MODEL Target Hardware Platform TOTAL EXECUTION TIME Memory_access_time T T exe_ total exe_ CPU = T = exe_ CPU instruction _ counts + memory T 3 _ access _ time exe_ instruction K = 1 K = cache_ hit _ counts CPU 2 _ cycle Min-wuk Lee 15

16 Energy-efficient efficient CPU cache (2/4) Cache model : about execution time Processor core hit_time Data cache Instruction cache Memory memory_access_time hit _ time = clock _ period core memory _ access _ time trcd + CAS _ latency + clock _ period == clock _ period L( burst _ access) mem mem L( non _ squential _ access) miss _ time == memory _ access _ time + hit _ timek( read) memory _ access _ timel( write) Min-wuk Lee 16

17 Energy-efficient efficient CPU cache (3/4) Energy modeling Tool and research documentation based model Cache hit energy : from CACTI 3.0 [4] Cache miss energy : from Power & Energy Characterization of the Itsy Pocket Computer by Compaq Western Research Laboratory 4.70nJ / bus_clock [5], [6] [4] : CACTI 3.0 : An integrated cache timing, power, and area model, Compaq Western Research Laboratory [5] : Power and energy characterization of the Itsy pocket computer [6] : A simulation framework for energy-consumption analysis of OS-driven embedded applications, TCAS 2003 Min-wuk Lee 17

18 Energy-efficient efficient CPU cache (4/4) Simulation results Direct mapped data cache, 8E/line (32B line size) Miss rate(%) Normalized execution time Normlizated@ 1 Normalized energy consumption Normlizated@ KB 4KB 8KB 16KB 2KB 4KB 8KB 16KB 2KB 4KB 8KB 16KB cache size cache size cache size 16KB data cache, 32B line size Miss rate(%) Normalized execution time Normlizated@ 1 1% performance degradation Normlizated@ Normalized energy consumption 13% energy saving DM 2WAY 4WAY 8WAY DM 2WAY 4WAY 8WAY DM 2WAY 4WAY 8WAY Using 2-way cache, 13% energy saving, 1% performance degradation compared with conventional 4-way cache Min-wuk Lee 18

19 Introduction Motivation Outline MobileGL: Mobile 3D graphics library Energy-efficient CPU cache Energy-efficient texture cache Conclusion Min-wuk Lee 19

20 Energy-efficient efficient texture cache (1/12) Texture mapping (Introduction) F(x,y,z) = (s,t) Map from 3D surface to 2D texel domain (image) Texture coordinate Lookup color in image y z x t s Lookup method 2D texture diagram Nearest texel Interpolation of surrounding texles MIPMAP Image pyramid Level 0 d axis Image pyramid Min-wuk Lee 20

21 Energy-efficient efficient texture cache (2/12) Texture filtering methods (Introduction) Point sampling, Bilinear filtering, Bilinear MIPMAP, Trilinear MIPMAP LOD 0 1st 1. Point sampling LOD 0 1st LOD = 1.XX 2nd 3rd 2nd 1st 2nd 3rd LOD 1 LOD 2 LOD 3 3rd Bilinear interpolation 2. Bilinear filtering 3. Bilinear MIPMAP Bilinear interpolation Bilinear interpolation 4. Trilinear MIPMAP Linear interpolation Texture space Screen space Texture space Min-wuk Lee 21

22 Energy-efficient efficient texture cache (3/12) Obstacle of texture mapping Requirement of extremely high bandwidth Texture cache To reduce the off-chip memory access bottlenecks Image conversion (texture map representation) : Reduce conflict miss Address conversion unit (A few logical operations and two additions) External memory 3D Rendering engine Address conversion Texture cache Image conversion Texture cache system Min-wuk Lee 22

23 Energy-efficient efficient texture cache (4/12) Simulation models Tiny Stealth Alien 6833 polygons 542 polygons 854 polygons Tiny :LOD[0:1] 80%, LOD[1:2] 10% Stealth :LOD[0:1] 67%, LOD[1:2] 15% Alien :LOD[0:1] 48%, LOD[1:2] trilinear MIPMAP Min-wuk Lee 23

24 Energy-efficient efficient texture cache (5/12) Proposed texture map representation Reduce conflict miss at bank change Miss rate reduction, energy saving (17.4%), execution time reduction (15.2%) Blocked representation Recursive Sub Block Min-wuk Lee 24

25 Energy-efficient efficient texture cache (6/12) Address conversion unit for RSB2X2 Use one-to-one correspondence and find rule Hardware implementation : only thirteen 2:1mux in trilinear MIPMAP Address conversion unit of this work : RSB 2X2 old11 old9 old7 old5 old3 old1 old10 old8 old6 old4 old2 old0 old11 old9 old7 old5 old3 old1 old10 old8 old6 old4 old2 old0 core request address core request address converted address new10 new8 new6 new4 new2 new0 new11 new9 new7 new5 new3 new1 converted address new10 new8 new6 new4 new2 new0 new11 new9 new7 new5 new3 new1 256 X 256, RSB 2X2 64 X 64, RSB 2X2 old11 old9 old7 old5 old3 old1 old10 old8 old6 old4 old2 old0 old11 old9 old7 old5 old3 old1 old10 old8 old6 old4 old2 old0 core request address core request address converted address new10 new8 new6 new4 new2 new0 new11 new9 new7 new5 new3 new1 converted address new10 new8 new6 new4 new2 new0 new11 new9 new7 new5 new3 new1 128 X 128, RSB 2X2 32 X 32, RSB 2X2 Min-wuk Lee 25

26 Energy-efficient efficient texture cache (7/12) Texture cache model using bank interleaved A0 Texture cache (1 bank) A0 A1 A2 A3 Texture cache (4 bank) Texture cache for even, odd LOD (4 bank) A0 A1 A2 A3 A4 A5 A6 A7 EvenLOD$ OddLOD$ D0 Point sampling D3 D2 D1 D0 Bilinear filtering Bilinear MIPMAP D7 D6 D5 D4 D3 D2 D1 D0 Trilinear MIPMAP Morton order representation previous work Proposed RSB2X2 also free from bank conflict Min-wuk Lee 26

27 Energy-efficient efficient texture cache (8/12) Performance and Energy comparison between filtering method Energy consumption, Execution time Point sampling < Bilinear filtering < Bilinear MIPMAP < Trilinear MIPMAP Trade off point : Image quality (aliasing criterion) Normalized energy P.S. B.F. B.M. T.M. 2KB, 16entries/line, Tiny_model D.M. 2WAY 4WAY Min-wuk Lee 27

28 Energy-efficient efficient texture cache (9/12) Image quality analysis Textile model LOD[0:1] : 44%, LOD[1:2] : 40% in MIPMAP Point smapling Bilinear filtering Bilinear mipmap Trilinear mipmap DCT analysis Low frequency term in top-left Point smapling Bilinear filtering Bilinear mipmap Trilinear mipmap Min-wuk Lee 28

29 Energy-efficient efficient texture cache (10/12) Image quality metric in terms of aliasing criterion image_ quality _ 0.5 π / 2 π / 2 fx= 0 fy= 0 = π π fx= 0 fy= 0 amplitude amplitude 0 image _ quality _ 0.75 PI fx 3π 4 3π 4 fx = 0 fy = 0 = π π fx = 0 fy = 0 amplitude amplitude Index Q, Index E To find relative value PI Normalize from 0 to 1 Index Q = cur Q max Q min min Q Q fy Index E = max max E E cur min E E Min-wuk Lee 29

30 Energy-efficient efficient texture cache (11/12) Index = Index Q + Index E Almost same quality between B.M. and T.M. in QVGA Large different energy between B.M. and T.M. Poor image quality in P.S. Bilinear MIPMAP get the largest score. Index Q 1 8E,(Q_0.5) 16E,(Q_0.75) P.S. B.F. B.M. T.M Index E P.S. B.F. B.M. T.M. 8E 16E Index Q +Index E P.S. B.F. B.M. T.M. 8E,(Q_0.5) 16E,(Q_0.5) 8E,(Q_0.75) 16E,(Q_0.75) 2-way set associative, 2KB texture cache Min-wuk Lee 30

31 Energy-efficient efficient texture cache (12/12) Simulation results 1.2 Normalized energy Tiny Stealth Alien E 16E K 2K 4K 8K 1K 2K 4K 8K 1K 2K 4K 8K Energy comparison while changing cache 2-way, using bilinear MIPMAP 4KB texture cache, 16B line size (2B per 1texel) energy-efficient, low cost, high-quality Min-wuk Lee 31

32 Introduction Motivation Outline MobileGL: Mobile 3D graphics library Energy-efficient CPU cache Energy-efficient texture cache Conclusion Min-wuk Lee 32

33 Conclusion For performance-energy co-optimization in Mobile3D graphics MobileGL / Cache architecture MobileGL : Mobile 3D graphics library 67K polygons/sec 66.1% performance improvement in average Energy-efficient CPU cache 2-way set associative cache to save energy Energy-efficient texture cache Proposed texture map representation Bilinear MIPMAP shows good quality to energy ratio 16B line size, 4KB size cache is the optimal point Min-wuk Lee 33

34 Supplemental Materials Min-wuk Lee 34

35 Geometry stage Graphics pipeline Rendering stage Camera direction 1st Top Camera position z z x View frustum Unit-cube x z x View transform Projection Clipping 1/w Screen mapping Direction_y Mid 3rd Line1 Line2 start Line3 Direction_x end 2nd Bot Triangle setup : For line1, line2, line3 using1st, 2nd, 3rd Horizontal setup : For line_x using start, end Line_x Rendering stage Pixel interpolation : Each pixel shading, texturing Min-wuk Lee 35

36 Energy portion of cache ARM920T and M*CORE : Caches consume 50% of total pr ocessor system power (Segars 01,Lee et.al. 99) >50% Min-wuk Lee 36

37 Blocked representation Conventional texture map representation (16X16blocked) Conflict block change A path : 2 B path : 16 C path : 16 B C A Block : Square region that texels are ordered consecutively Assumptions 1. Bilinear filtering block block Cache size = block size 3. 16entries / 1 line X16 conventional block texture map Min-wuk Lee 37

38 Proposed texture map representation Recursive Sub Block texture map representation (RSB4X4) Conflict change A path : 4 B path : 4 C path : 4 Assumptions 1. Bilinear filtering 2. Cache size = block size B A C block entries/ 1line block block recursive sub-block 4X4 method Min-wuk Lee 38

39 Simulation between representation methods Simulation results between texture representations Bilinear filtering, 2-way, 1KB texture cache 27% performance improvement in average Low miss rate doesn t mean high performance 8entries/line or 16entries/line shows good performance Miss rate Tiny Stealth Alien 4X4 8X8 16X16 RSB2X2 Normalized performance Tiny Stealth Alien 4X4 8X8 16X16 RSB2X E 8E 16E 32E 4E 8E 16E 32E 4E 8E 16E 32E 0.5 4E 8E 16E 32E 4E 8E 16E 32E 4E 8E 16E 32E Min-wuk Lee 39

40 Simulation between representation bilinear filtering Low miss rate doesn t mean low energy consumption RSB accomplish 17.4% energy saving compared to the best of conventional point sampling 25% performance improvement in average Normalized energy Tiny Stealth Alien 17.4% energy saving 4E 8E 16E 32E 4E 8E 16E 32E 4E 8E 16E 32E 4X4 8X8 16X16 RSB2X2 Normalized performance Tiny Stealth Alien 4E 8E 16E 32E 4E 8E 16E 32E 4E 8E 16E 32E 4X4 8X8 16X16 RSB2X2 Bilinear filtering, 1KB cache, 2way Point sampling, 1KB cache, 2way Min-wuk Lee 40

41 Morton order Multi-ported cache To access more than 1 texel in the same cycle Interleaving the cache lines across multi-banks Morton order RSB4X4 : Not free from bank conflict RSB2x2 Trilinear filtering : Not free from bank conflict Cache for even, odd LOD 4X4 block map Morton order LSB 2bits LSB 2bits LSB 2bits D0 D1 D2 D3 3 Not free from bank conflict Bank conflict free 2 D4 D5 D6 D Not free from bank conflict LSB 2bits Min-wuk Lee 41

42 Proposed texture map representation RSB2X2 map representation Bank conflict free A Conflict bank change A : B : C : B C RSB 4X4 block block RSB recursive sub-block 2X2 method Min-wuk Lee 42