A 120mW Embedded 3D Graphics Rendering Engine with 6Mb Logically Local Frame-Buffer and 3.2GByte/s Run-time Reconfigurable Bus for PDA-Chip

Transcription

1 A 120mW Embedded 3D Graphics Rendering Engine with 6Mb Logically Local Frame-Buffer and 3.2GByte/s Run-time Reconfigurable Bus for PDA-Chip Ramchan Woo*, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Kangmin Lee, Yong-Ha Park and Hoi-Jun Yoo Semiconductor System Laboratory Department of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST)

2 Outline Introduction Frame Buffer and Bus Architecture Line Block Memory Mapping Power Reduction Techniques Implementation Results Conclusion 2

3 Mobile Multimedia Era Realtime Audio Polygon Data over Wireless Network - 3D Fax - 3D Game - 3D Advertisement Multimedia PDA Realtime Video 3D Graphics 3

4 3D Graphics on PDA edram RISC 3D Rendering MPEG-4 I/O Peripherals PDA-Chip Low Power Small Area High Performance 4

5 Rendering Engine Overview Polygon Data 8-pixel-parallel rendering at every clock cycle Fetch & Control L R EP RGB out SAM (1.5Kb SRAM) C2 C1 Z 512kb 512kb 512kb 512kb A0 B0 512kb 512kb 512kb 512kb A1 B1 768bits 1280bits 640bits 8 PPs 6Mb edram Frame Buffer R2bus Rendering Logic 5

6 Conventional Frame Buffers - 1 Local Frame Buffer PP 0 Local Memory 0 PP 1 Local Memory 1 embedded DRAM PP n Local Memory n Periphery Cell High Memory Bandwidth Parallel access via local routes Low Power Selective Activation Large Area Poor DRAM Cell Efficiency 6

7 Conventional Frame Buffers - 2 Global Frame Buffer Bank 0 PP Bank 1 embedded DRAM Bank n Periphery Cell Smaller Area High Cell Efficiency Low Memory Bandwidth at Low Clock Sequential Access with bank interleaving Large Power Consumption Rectangular memory mapping 7

8 Logically Local Frame Buffer EP PP 0 PP 1 Macro A0 Macro A1 Macro B0 Z-Buffer Color Buffer A Color Buffer B embedded DRAM 512kb 512kb 512kb PP 7 Macro B1 Periphery Cell Small Area High DRAM Cell Efficiency High Memory Bandwidth Parallel access through R2bus Low Power Selective Activation 8

9 Line Block Memory Mapping - 1 Screen Each adjacent Line Block is mapped onto different macro unit Macro A0 Macro B Line Block = 8x1 screen pixels GWL drv GWL drv Macro A1 GWL drv GWL drv Macro B1 9

10 Line Block Memory Mapping - 2 V2 A0 B0 #3 #4 V3 A1 B1 Write V4 V5 V6 A0 A1 A0 B0 B1 B0 Read Write Read V7 A1 B1 V8 A0 B0 V9 A1 B1 Selective Activation to Reduce Power edram Clock (100MHz) Logic Clock (20MHz) #1 #2 #3 #4 Macro A0, B0 Macro A1, B1 Modify V1 READ V2 WRITE Modify V2 READ WRITE Modify V3 READ V4 WRITE Modify V4 READ WRITE Continuous Pixel Processor Operation Simultaneous Read-Modify-Write 10

11 Power Reduction Techniques - 1 Selective Macro Activation (SMA) Macro A# Macro B# Macro #0 A0 B0 Macro #1 A1 B1 More than 90% lines in polygons require only one macro activation P1 P2 P3 Screen A0 A1 Activate only #0 B0 B1 A0 B0 A0 A1 B1 A1 Activate both #0 and #1 B0 B1 A0 B0 A1 B1 Activate only #1 11

12 Power Reduction Techniques - 2 Partial Wordline Activation (PWA) XDP One Line Block activates only one Sub-Wordline GWL drv SWL drv GWL SWL SWL drv SWL drv RX /GWL PA SWL drv LXA AA SWL GWL GWL driver SWL address S/A S/A S/A GWL SWL driver S/A DB edram Macro 12

13 Power Reduction Techniques - 3 Partial I/O Activation (PIA) GWL SWL DBSA /REN DB I/O GWL drv SWL drv SWL drv REN SWL drv SWL drv S/A S/A /DB REN S/A S/A DBSA Disable Unnecessary DBSA by I/O Mask Inactive I/O Bus active I/O Bus edram Macro 13

14 Run-time Reconfigurable Bus Bidirectional Memory Bus x1280 Cascaded 2-to-2 MUX (inter-bus) 16-to-8 Bus-Shifter (intra-bus) Omnidirectional PP Bus x640 ctrl01 ctrlabread A0 (x320) A1 (x320) to PP-Read-Bus (x320) ctrl01 ctrlabwrite B0 (x320) B1 (x320) from PP-Write-Bus (x320) 1280bits Bus 20MHz = 3.2GByte/s 14

15 Operations of R2bus Rendering Logic Rendering Logic Rendering Logic A0 B0 A1 B1 A0 B0 A1 B1 A0 B0 A1 B1 (a) Normal Rendering (b) Individual Activation (c) Broadcasting 15

16 Area and Power Reduction Area (mm 2 ) Power (mw) edram Peri edram Core Logic R2bus edram Peri edram Core Logic 25% Area Reduction edram Peri and I/O Bus edram Core Logic Peri I/O Core Logic 70% Power Reduction Local Frame Buffers Logically Local Frame-Buffer Without SMA, PWA, PIA With SMA, PIA, PWA 16

17 Rendering Engine in PDA-Chip External Polygon Database - External Memory - Wireless Network 32bit RISC BEQ (SRAM) Other Hardware Blocks Rendering Logic R2bus Frame Buffer LCD - 24bit RGB Data Embedded 3D Graphics Rendering Engine 17

18 Rendering Engine Features Process Power Consumption Area Power Supply Components Data Rate 3D Rendering Features 0.18um CMOS EML with 3-poly 6-metal 120mW 24mm 2 Rendering Logic edram 190,231 logic transistors 6Mb edram 3.2GByte/s 20MHz 100MHz 2.22Mpolygons/s Gouraud Shading 16bit Depth-Comparison Alpha-Blending Double-Buffering Direct Video Transfer through SAM 24bit true-color on 256x256 18

19 Microphotograph SAM Frame Buffer 6Mb edram Macros DLL R2bus Rendering Logic ramp-ii Multimedia PDA-Chip 3D Rendering Personal Information Management MP3 Audio MPEG-4 Video PDA-Chip E3GRE PDA-Chip : ISSCC2001 TP

20 Measured Waveforms REclk Sclk Dout[0] Dout[1] 100ns

21 Conclusion 3D Graphics for PDA-Chip 24bit True Color on 256 x 256 LCD screen 2.2Mpolygons/s Embedded 3D Graphics Rendering Engine 6Mb Logically Local Frame Buffer 3.2GByte/s Run-time Reconfigurable Bus 25% Area Reduction 70% Power Reduction 24mm 2, 120mW 21

22 Top REclk Sclk Dout[0] Test Slide SAM Frame Buffer 6Mb edram Macros DLL R2bus Rendering Logic PDA-Chip Dout[1] 100ns E3GRE Left Center Right SS L Semiconductor System Lab Bottom 22