WB_INTERFACE - Pin Description

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Gertrude Cunningham
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1 WB_NTERFACE - Pin Description Frozen Content Modified by Admin on Sep 13, 2017 The following pin description is for the WB_NTERFACE component when used on the schematic. n an penbus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface. The component's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying penbus System. The pin description includes examples of each supported interface item and the pins involved (both Read & Write where applicable). The actual pins in the interface will vary, depending on the number and type of items added, and how those items have been configured. Table 1. WB_NTERFACE pin description. Name Type Control Signals CLK_ Rise Polarity/ Bus size Description External (system) clock signal RST_ High External (system) reset Host Processor nterface Signals STB_ High CYC_ High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers

2 ACK_ High Standard Wishbone acknowledgement signal. When this signal goes high, the WB_NTERFACE (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated ADR_ 0-32 (see note 1) Standard Wishbone address bus, used to address the items of the customized interface. nternal registers and command sets each occupy a single address. External address ranges occupy an address range corresponding to their configured address bus widths. DAT_ DAT_ WE_ Level Custom nterface Signals (Example tems) Whole nternal Register (R) RName_ RName_ Sliced nternal Register (R) - 2 slices shown RName_Slice1Name_ 8/16/32 (see note 2) 8/16/32 (see note 2) 1-32 (see note 3) 1-32 (see note 3) Data to be sent to host processor Data received from host processor Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write Data input from connected logic Data output to connected logic Slice 1 data input from bits of data will be loaded into the relevant bits of internal register RName, as defined by register slice Slice1Name.

3 RName_Slice1Name_ Slice 1 data output to bits of data in internal register RName, as defined by register slice Slice1Name, will be sent to the connected RName_Slice2Name_ Slice 2 data input from bits of data will be loaded into the relevant bits of internal register RName, as defined by register slice Slice2Name. RName_Slice2Name_ Slice 2 data output to bits of data in internal register RName, as defined by register slice Slice2Name, will be sent to the connected Command Set (CS) - Single command class configured with 2 commands and 2 operands CSName_CmdClassName_Cmd1Name_ CSName_CmdClassName_Cmd2Name_ High High utput pin for command Cmd1Name, which is part of the command class CmdClassName, within the defined command set CSName. utput pin for command Cmd2Name, which is part of the command class CmdClassName, within the defined command set CSName. CSName_CmdClassName_p1Name_ (see note 5) utput pin for command operand p1name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class.

4 CSName_CmdClassName_p2Name_ (see note 5) utput pin for command operand p2name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class. CSName_ACK_ High Acknowledge signal. This pin will be present if, when defining the command set, the mmediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_NTERFACE'S ACK_ line to the host processor. External Address Range (EAR) EARName_ADR_ EARName_DAT_ 1-32 EARName_DAT_ 1-32 EARName_RD_ High EARName_WR_ High EARName_ACK_ High 0-32 (see note 6) Address bus. Data input from connected Data output to connected Read enable for the connected Write enable for the connected Acknowledge signal. This pin will be present if, when defining the external address range, the mmediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_NTERFACE'S ACK_ line to the host processor.

5 Notes 1. Automatically determined based on the items defined for the interface. 2. The width of the data bus for the Wishbone interface to the host processor is specified as part of the component's configuration. t must be greater than, or equal to, the largest data width specified for items in the interface. 3. The width of the data bus for an internal register is defined as part of its configuration. t must be less than, or equal to, the width specified for the Wishbone data bus of the WB_NTERFACE component. 4. Each slice must be a contiguous group of bits and no slices can overlap. For the single register RName, the bit ranges defined for each of the constituent slices (e.g.,,...,range N ) can not exceed the defined data width for the register. 5. The bit ranges of operands in the same command class must comprise of contiguous bits and can not overlap. The usable operand bit ranges in a particular command class will be dependent on the data width specified for the command set and how many commands are defined in that set. 6. The width of the address bus for the external address range is defined as part of its configuration. f only one address is defined (0 bits) there will be no EARName _ADR_ pin. The maximum width of the address will depend on the number of items defined in the custom interface. Source URL:

WB_INTERFACE Custom Wishbone Interface

WB_INTERFACE Custom Wishbone Interface Summary This document provides detailed reference information with respect to the WB_INTERFACE peripheral component. This component enables you to build custom Wishbone