WB_MP3DEC - Wishbone MP3 Decoder

Transcription

1 WB_MP3DEC - Wishbone MP3 Decoder Frozen Content Modified by on 13-Sep-2017 Parent article: FPGA Peripheral Components - Wishbone WB_MP3DEC - Wishbone MP3 Decoder. The Wishbone MP3 Decoder component (WB_MP3DEC) facilitates the decoding of MPEG-2 Layer 3 encoded audio data ('MP3') into dual-channel 16-bit signed samples. The WB_MP3DEC features the optional ability to connect to external 'scratch' memory of your choosing. If use of such memory is not specified, Block RAM internal to the FPGA will be used instead. In less official terms, the WB_MP3DEC could be called an MPEG-1 Audio Layer 3 decoder. It's formal designation would be a limited accuracy ISO/IEC Layer 3-only constant bit-rate audio decoder. This is, however, not an official category of decoder recognized by the ISO/IEC standards. The nearest comparable decoder, recognized by the ISO/IEC, would be a limited accuracy ISO/IEC Layer 3 audio decoder which, however, is required to decode Layer 1/2 as well. The WB_MP3DEC does not support decoding of Layer 1/2 encoded data. Furthermore, 'free format' support (a rare option that allows higher and non-standard bit-rates) and emphasis are not currently implemented for the WB_MP3DEC. The WB_MP3DEC can decode all 'MP3' audio data with sample rates of 32/44/48kHz and bit-rates of kbit/s. It does not, however, decode ISO (MPEG-2 Audio Layer 3) low bit-rate extensions, with bit-rates down to 8/16/24kbit/s and sample rates of 16/205/24kHz.

2 The WB_MP3DEC can be used with any of the 32-bit processors available in Altium Designer. Features at-a-glance DMA interface to read input and write output Separate memory access to 'Scratch' memory Supported MP3 audio data sample rates: 32/44/48kHz Supported MP3 audio data bit-rates: kbit/s Wishbone-compliant Availability From an OpenBus System document, the MP3 Decoder component can be found in the Peripherals region of the OpenBus Palette panel. From a schematic document, the WB_MP3DEC component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation. Pin Description The following pin description is for the WB_MP3DEC component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System. Work In Progress Configuration The WB_MP3DEC can be configured after placement on the OpenBus System document, or schematic sheet, using the associated configure dialog. Access to this dialog depends on the document in which you are working: In the OpenBus System document access the dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Alternatively, double-click on the component to access the dialog directly. In the Schematic document simply right-click over the device and choose the Configure command from the context menu that appears. Alternatively, click on the Configure button, available in the Component Properties dialog for the device.

3 Configuration dialog (accessed from OpenBus System). Use the dialog to specify whether external 'scratch' memory is to be used. If this option is disabled, Block RAM internal to the FPGA will be used. Operational Overview The following sections outline procedures for initialization of the WB_MP3DEC and subsequent decoding of MP3 data. Decoding MP3 Data The (first part of the) MP3 data must be available in memory, as well as an output buffer (576 x 32-bit words). Both must be accessible over the data memory bus Reset the core by writing '1' to STATUS.Reset. Write SCRATCHADDRESS if required. Write READSTARTADDRESS with the start address of the MP3 data area. Write READENDADDRESS with the end address of the MP3 data area. Write WRITEADDRESS with the start of the output data buffer. Start the core by writing '1' to STATUS.Start. Now monitor (either by polling or by interrupt) the STATUS.ReadEmpty and STATUS.WriteReady flags. If STATUS.WriteReady is set a new frame audio has been decoded: Process the audio. Continue decoding by writing '1' to STATUS.WriteReady.

4 If STATUS.ReadEmpty is set, the core has no more data to process. If there is any more data available from the same MP3 stream, load it into the data area and: Write READSTARTADDRESS with the start address of the MP3 data area. Continue decoding by writing '1' to STATUS.ReadEmpty. Double Buffering By using multiple input and output buffers, MP3 data can be read, and output audio can be processed, while the core is busy decoding. In this case the processing of the WriteReady and ReadEmpty flags should be extended. If STATUS.WriteReady is set: 3. Process the audio. Write WRITEADDRESS with the start address of the new output buffer. Continue decoding by writing '1' to STATUS.WriteReady. If STATUS.ReadEmpty is set: 3. Write READSTARTADDRESS with the start address of the new MP3 data area. Write READENDADDRESS with the end address of the new MP3 data area. Continue decoding by writing '1' to STATUS.ReadEmpty. DMA Interface The data DMA interface consists of a 32-bit wishbone compliant master bus, from which the lower 2 bits are fixed to '0'. Reads and writes always are either word-wide or halfword-wide. Depending on VERSION.LittleEndian, data is either big-endian or little-endian. The scratch DMA interface consists of a 32-bit wishbone compliant master bus, from which the lower 2 bits are fixed to '0'. Reads and writes always are always word-wide (M2_SEL_O[3..0] are fixed to '1'). Data on this bus is for internal use of the core only. This interface is only available if the core is configured to use external scratch memory, if not the core will use FPGA block memory invisible to the user. Register Interface Main article: WB_MP3DEC - Accessible Internal Registers Address Name Function 0000 (0h) STATUS Status and control 0001 (1h) INTMASK Interrupt mask 0010 (2h) READADDRESS Start of Read area 0011 (3h) READENDADDRESS End of Read area

5 0100 (4h) WRITEADDRESS Start of Write area 0101 (5h) SCRATCHADDRESS Start of Scratch area 0110 (6h) HEADER Header word of last MP3 frame 1111 (Fh) VERSION Core version and endianness Software Platform Support The WB_MP3DEC is fully supported by the Software Platform. All registers of the peripheral are described in per_mp3dec.h, a device driver is available in drv_mp3dec.c and drv_mp3dec.h. See online documentation for a full description of its interface. Hardware wrapper and driver for the WB_MP3DEC, as part of a defined Software Platform. Resource Usage The MP3 decoder needs quite a lot of scratch memory currently bit words and a lot of bandwidth to access it. In the current incarnation of the core this is accessed over a separate memory bus making it possible to put it in either BLOCK RAM, separate off-chip RAM or using a multi-master shared with the CPU. Performance-wise, it is able to handle a 320k bit-rate, 48kHz stereo MP3 file at 34MHz without any problem. Naturally if using external scratch memory this will also be dependent on the amount of wait states and bus traffic. Example Reference Design Two example designs, demonstrating the use of the MP3 Decoder peripheral, are included as part of your Altium Designer installation: MP3_Decoder.PrjFpg located in the \Examples\Soft Designs\Audio\MP3 Decoder folder. NB3000_MP3_Decoder.PrjFpg located in the \Examples\Soft Designs\Audio\NB3000

6 MP3 Decoder folder. Source URL: