WB_INTERFACE Custom Wishbone Interface

Transcription

1 WB_INTERFACE Custom Wishbone Interface Summary This document provides detailed reference information with respect to the WB_INTERFACE peripheral component. This component enables you to build custom Wishbone peripherals in a design. The Custom Wishbone Interface component (WB_INTERFACE) enables you to build a custom Wishbone peripheral in a design, extending your 32-bit FPGA systems through the creation of custom FPGA logic. The Custom Wishbone Interface component has a fully configurable interface for transferring data to/from connected logic, and a Wishbone bus to interface with a host processor. The individual units of this configurable interface are referred to as 'items'. The interface can include a combination of one or more of the following items: Internal Registers which allow values to be read from, and/or written to, connected logic. Command Sets which allow operations to be enabled on connected logic. External Address Ranges which allow access to blocks of addresses on connected logic. Customization is performed through configuration dialogs associated with the component, after placement on the OpenBus System or Schematic document. In addition to making the task of building custom Wishbone peripherals far easier, the Custom Wishbone Interface component also provides the ability to generate C code based on the items specified in the interface simplifying interaction with the component from the embedded code running on the host processor. Features Fully customizable Wishbone peripheral component - Configurable interface to connected custom logic - Wishbone interface to host processor Supports 3 interface item types: - Internal Registers - Command Sets - External Address Ranges Completely configurable from the OpenBus System document or Schematic sheet Requires no knowledge of Wishbone bus or HDL to use Ability to generate C code for use in embedded projects Available Components From an OpenBus System document, the Custom WB Interface component can be found in the Peripherals region of the OpenBus Palette panel. From a schematic document, the WB_INTERFACE component can be found in the FPGA Peripherals integrated library (FPGA Peripherals.IntLib), located in the \Library\Fpga\ folder of the Altium Designer installation. Version (v1.0) Apr 28,

2 Concepts The FPGA-ready Wishbone-compliant components supplied with Altium Designer can be thought of as an extensive set of building blocks. For many 32-bit processor-based designs, these will be sufficient for the design task. However, you may need to implement other pieces of hardware that don't exist among these pre-packaged blocks. This can be achieved, for example, by using generic logic components on a sub-sheet, or a referenced C or HDL (VHDL/Verilog) file. The role of the Custom Wishbone Interface component is to provide the means by which to hook that hardware into your existing Wishbone system so that it can be 'seen' and communicated with, by a processor therein. The Custom Wishbone Interface component achieves this by enabling you to build your own customized Wishbone peripheral, without having to learn any of the intricacies of the Wishbone bus itself. Figure 1 illustrates the concept of the Custom Wishbone Peripheral in a design. Custom Wishbone Peripheral Custom Logic Customizable Interface Custom Wishbone Interface (WB_INTERFACE) Wishbone Interface To processor via Interconnect Figure 1. The Custom Wishbone Peripheral concept. The interface to your custom logic is fully customizable you tailor it to meet the needs of your custom logic, for example to interrogate some registers, or issue commands to make something in your logic happen. The advantage of this is that you are not constrained to build logic that has to connect to a rigidly defined interface. You build your logic and then tailor the interface to suit your needs. The interface to your main processor system is simply a standard Wishbone interface. Connect directly to an Interconnect component in your system. The width of the Address bus is handled automatically for you, depending on the configuration of any external address range items in your customized interface. All you need to do is set a width for the Data bus! Example Usage The best way to illustrate the concept of a customizable Wishbone interface component, and how it can be used to enhance and extend your FPGA designs, is to look at an example. Consider the custom logic component in Figure 2, which represents a set of 16 banks of registers. Each register bank comprises 32 x 32-bit registers. Such a component might be used in a CPU as shadow registers, to optimize context switching. Version (v1.0) Apr 28,

3 Custom Logic Component BANK 0 BANK 1 BANK 15 Reg 0 Reg 1 Reg 2 Reg 0 Reg 1 Reg 2 Reg 0 Reg 1 Reg 2 Reg 3 Reg 3 Reg 3 Reg 4 Reg 4 Reg 4 CLK_I CUR_REG_BANK_O[3..0] CHANGE_REG_BANK_I BANK_NUM_I[3..0] ACK_O Reg 27 Reg 27 Reg 28 Reg 28 Reg 29 Reg 29 Reg 30 Reg 30 Reg 31 Reg 31 Reg 27 Reg 28 Reg 29 Reg 30 Reg 31 REG_ADR_I[4..0] REG_DAT_O[31..0] REG_DAT_I[31..0] REG_RD_I REG_WR_I Figure 2. Example custom logic component (high-level illustration). Considering the operation of this component and how each of its pins are used: Only one register bank can be active at a time. The currently active register bank is indicated by the value at the CUR_REG_BANK_O output. The active bank can be changed by driving the CHANGE_REG_BANK_I signal High and specifying the required bank at the BANK_NUM_I input. The component's ACK_O signal is driven High to indicate the successful switching of register banks. The value of a register in the currently active bank can be written by: - Driving the REG_WR_I pin High - Specifying the required register using the REG_ADR_I input - Specifying the value to be written to this register at the REG_DAT_I input The value of a register in the currently active bank can be read by: - Driving the REG_RD_I pin High - Specifying the required register using the REG_ADR_I input - Reading the value made available at the REG_DAT_O output. This is quite a handy little piece of hardware custom logic that is not available as a pre-packaged component delivered with the software. Suppose now that we wish to interact with this component from a 32-bit Wishbone-compliant processor in an FPGA design. The component itself is not Wishbone-compliant. It is possible however, to build a custom Wishbone peripheral without the need to know any details of the Wishbone bus and that's where the Custom Wishbone Interface component (WB_INTERFACE) comes in. As a quick reminder, the WB_INTERFACE component has a Wishbone bus and a fully customizable interface for transferring data to/from connected logic. The individual units of this configurable interface are referred to as 'items'. The interface can include a combination of one or more of the following items: Internal Registers which allow values to be read from, and/or written to, connected logic. Command Sets which allow operations to be enabled on connected logic. External Address Ranges which allow access to blocks of addresses on connected logic. For our example custom logic device, the Custom Wishbone Interface component can be used as outlined in Figure 3. Note that the custom logic device (not shown) is defined in a sub-sheet, referenced by a sheet symbol on the top-level schematic. Version (v1.0) Apr 28,

4 Figure 3. Configure the Wishbone Interface to communicate with your custom logic as required and extend the capabilities of your design. The interface to the custom logic device is configured to have the following three items: CUR_REG_BANK (Internal Register item) this item is configured as a read register for reading the value of the currently active register bank. CHANGE (Command Set item) this item is configured with a command, BANK, which tells the custom component to switch register banks. It has an associated operand, BANK_NUM, which is the desired register bank to switch to. REG (External Address Range item) this item is configured to handle the reading and writing of values to the desired registers in the currently active register bank. The index of the desired register is output on the item's REG_ADR_O line. Data is transferred to/from the custom logic component using the item's REG_DAT_O and REG_DAT_I lines. Version (v1.0) Apr 28,

5 Designing with the WB_INTERFACE Use of a WB_INTERFACE component within an FPGA design is a straightforward procedure simply place the component, configure it in accordance with your design requirements, and wire it up to the applicable circuitry of the design. Symbol Figure 4. Symbols used for the Wishbone Interface peripheral in both schematic (left) and OpenBus System (right). Note: The schematic-based symbol shown in Figure 4 reflects the WB_INTERFACE component configured with the following example interface items: Internal register (CUR_REG_BANK) 4-bit wide, Read only Command set (CHANGE) with one command and one operand External address range (REG) 32-bit data bus, 5-bit address bus, Read and Write. For more details on defining the interface, see the section Configuring. When initially placing the WB_INTERFACE on the schematic (or placing the Custom WB Interface component in an OpenBus System), the component will be configured with a single internal register item 8-bit, Write only. Pin Description The following pin description is for the component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interface. The component's external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System. Note: The pin description includes examples of each supported interface item and the pins involved (both Read & Write where applicable). The actual pins in the interface will vary, depending on the number and type of items added, and how those items have been configured. Table 1. WB_INTERFACE pin description Name Type Polarity/ Bus size Description Control Signals CLK_I I Rise External (system) clock signal RST_I I High External (system) reset Host Processor Interface Signals Version (v1.0) Apr 28,

6 STB_I I High Strobe signal. When asserted, indicates the start of a valid Wishbone data transfer cycle CYC_I I High Cycle signal. When asserted, indicates the start of a valid Wishbone bus cycle. This signal remains asserted until the end of the bus cycle, where such a cycle can include multiple data transfers ACK_O O High Standard Wishbone acknowledgement signal. When this signal goes high, the WB_INTERFACE (Wishbone Slave) has finished execution of the requested action and the current bus cycle is terminated ADR_I I Standard Wishbone address bus, used to address the items of the customized interface. Internal registers and command sets each occupy a single address. External address ranges occupy an address range corresponding to their configured address bus widths. DAT_O O 8/16/32 2 Data to be sent to host processor DAT_I I 8/16/32 2 Data received from host processor WE_I I Level Write enable signal. Used to indicate whether the current local bus cycle is a Read or Write cycle: 0 = Read 1 = Write Custom Interface Signals (Example Items) Whole Internal Register (IR) IRName_I I Data input from connected logic IRName_O O Data output to connected logic Sliced Internal Register (IR) 2 slices shown IRName_Slice1Name_I I Range1 4 Slice 1 data input from connected logic. The Range1 bits of data will be loaded into the relevant bits of internal register IRName, as defined by register slice Slice1Name. IRName_Slice1Name_O O Range1 4 Slice 1 data output to connected logic. The Range1 bits of data in internal register IRName, as defined by register slice Slice1Name, will be sent to the connected logic. IRName_Slice2Name_I I Range2 4 Slice 2 data input from connected logic. The Range2 bits of data will be loaded into the relevant bits of internal register IRName, as defined by register slice Slice2Name. IRName_Slice2Name_O O Range2 4 Slice 2 data output to connected logic. The Range2 bits of data in internal register IRName, as defined by register slice Slice2Name, will be sent to the connected logic. Command Set (CS) Single command class configured with 2 commands and 2 operands 1 Automatically determined based on the items defined for the interface. 2 The width of the data bus for the Wishbone interface to the host processor is specified as part of the component's configuration. It must be greater than, or equal to, the largest data width specified for items in the interface. 3 The width of the data bus for an internal register is defined as part of its configuration. It must be less than, or equal to, the width specified for the Wishbone data bus of the WB_INTERFACE component. 4 Each slice must be a contiguous group of bits and no slices can overlap. For the single register IRName, the bit ranges defined for each of the constituent slices (e.g. Range1, Range2,...,RangeN) can not exceed the defined data width for the register. Version (v1.0) Apr 28,

7 CSName_CmdClassName _Cmd1Name_O CSName_CmdClassName _Cmd2Name_O CSName_CmdClassName _Op1Name_O CSName_CmdClassName _Op2Name_O O High Output pin for command Cmd1Name, which is part of the command class CmdClassName, within the defined command set CSName. O High Output pin for command Cmd2Name, which is part of the command class CmdClassName, within the defined command set CSName. O Range1 5 Output pin for command operand Op1Name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class. O Range2 5 Output pin for command operand Op2Name, which is part of the command class CmdClassName, within the defined command set CSName. This operand output will be used by all commands defined within the same parent command class. CSName_ACK_I I High Acknowledge signal. This pin will be present if, when defining the command set, the Immediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. External Address Range (EAR) EARName_ADR_O O Address bus. EARName_DAT_I I 1-32 Data input from connected logic. EARName_DAT_O O 1-32 Data output to connected logic. EARName_RD_O O High Read enable for the connected logic. EARName_WR_O O High Write enable for the connected logic. EARName_ACK_I I High Acknowledge signal. This pin will be present if, when defining the external address range, the Immediate Acknowledgement option is left disabled. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. 5 The bit ranges of operands in the same command class must comprise of contiguous bits and can not overlap. The usable operand bit ranges in a particular command class will be dependent on the data width specified for the command set and how many commands are defined in that set. 6 The width of the address bus for the external address range is defined as part of its configuration. If only one address is defined (0 bits) there will be no EARName_ADR_O pin. The maximum width of the address will depend on the number of items defined in the custom interface. Version (v1.0) Apr 28,

8 Interfacing How the WB_INTERFACE is placed and wired within an FPGA design depends on the method used to build that design. The main processor-based system can be contained as a separate OpenBus System, which is then referenced from the top-level schematic, or it can be defined purely on the schematic sheet. Figure 5 illustrates use of the component in both the OpenBus System and Schematic environments. Figure 5. Example use of a WB_INTERFACE component in both Schematic-based and OpenBus System-based FPGA designs. For more information on the concepts and workings of the OpenBus System, refer to the document AR0144 Streamlining Processor-based FPGA Design with the OpenBus System. Version (v1.0) Apr 28,

9 Configuring The WB_INTERFACE can be configured after placement on the OpenBus System document, or schematic sheet, using the associated Configure (Wishbone Interface) dialog (Figure 6). Access to this dialog depends on the document in which you are working: In the OpenBus System document access the dialog by right-clicking over the component and choosing the Configure command from the menu that appears. Alternatively, double-click on the component to access the dialog directly. In the Schematic document simply right-click over the component and choose the Configure command from the context menu that appears. Alternatively, click on the Configure button, available in the Component Properties dialog for the component. Figure 6. Configuring the Custom Wishbone Interface component. Use the dialog to configure the WB_INTERFACE component in accordance with design requirements. The following sections detail the configuration options available from this main dialog. For configuration of individual item types, see the section Configuring Item Types, later in this document. Items Use the Items region of the dialog to define the items within the custom interface internal registers, command sets, external address ranges. Use the controls available beneath the main list (or from the right-click menu) to add, edit or remove items as required. The Move Up and Move Down buttons (and corresponding commands on the right-click menu) can be used to change the order of the items within the interface, in terms of appearance on the schematic symbol. Each item in the list will appear in terms of the following information: Name the unique name for the item Data Width the width of the item's data bus, specified when defining the item. Item Type which of the three supported item types it is (internal register, command set, external address range). For internal register and external address range items, the data direction is also displayed (Read, Write or Read/Write). Item Address item addresses are determined automatically. Internal registers and command sets each occupy a single address. The address range occupied by an external address range item is determined by that item's address bus width, specified as part of its definition. Data Bus Width The Data Bus Width region of the dialog enables you to configure the width of the Wishbone data bus. Choose from 8-, 16-, or 32-bit data width. The width specified must be greater than, or equal to, the largest data width specified for items in the interface. Version (v1.0) Apr 28,

10 C Code Generation The Configure (Wishbone Interface) dialog also provides a Generate C Code button, which you can use to quickly generate C code to simplify interaction with the WB_INTERFACE component from an embedded software project. Ensure that your custom interface is configured as required prior to using this facility. When you click the button, the Choose a Base Filename dialog will appear. Use this dialog to determine where, and with what root name, the generated header (*.h) and source (*.c) files will be saved. These generated files can then be added to the relevant embedded software project. All functions within the generated files require the base address of the associated WB_INTERFACE component. This can be found in the generated hardware.h file for the design. Note: Remember to regenerate the C source files if the configuration of the WB_INTERFACE component changes. Figure 7. Examples of generated C header and source files for a configured WB_INTERFACE component. Version (v1.0) Apr 28,

11 Configuring Item Types The following sections take a closer look at configuration of each of the supported item types, with respect to the custom interface. Internal Register An internal register allows a value to be read from, and/or written to, connected logic. This item type is defined using the Internal Register Properties dialog (Figure 8). Figure 8. Configuration dialog for the internal register item. Use the dialog to define the following properties for the internal register: Name A unique name for the register. Each item in the custom interface must have a unique name so that there are no name 'clashes' in the schematic document, the generated VHDL code, or the generated C code. Note: If two items in different WB_INTERFACE components in the same design project have the same name, the functions generated in the C code will have the same name, resulting in a name 'clash'. Data Width The width of the data bus, in bits. This value can range from 1 to 32 bits, but must be less than or equal to, the value defined for the width of the Wishbone data bus. IO Type The direction of data access. You can specify Read, Write, or Read/Write. Graphical Attributes When the component is placed on a schematic sheet, this property allows you to specify the amount of blank space to be inserted after the item's bank of pins. Slices A register can, if required, be divided into smaller 'slices'. Each slice consists of a contiguous group of bits and the bit ranges of slices can not overlap. Version (v1.0) Apr 28,

12 Use the controls in this region of the dialog (buttons or commands from the right-click menu accessible from within the list area) to add, edit, remove, and reorder slice definitions. When adding or editing a slice, its properties are defined in the Register Slice Properties dialog. From here, you define a unique name for the slice, and its bit range in terms of Start (low order bit) and End (high order bit) indices. The start and end indices are inclusive. Figure 9 illustrates the slicing of an internal register (named BIG) into two equal slices name HI (bits 7..4) and LO (bits 3..0). While the names of slices within a single register must be unique, slices in different registers can have the same name. Figure 9. Example division of a register into slices. Note: If a register is not divided into slices, pins for the whole register will appear on the schematic symbol. If there is at least one slice, pins for the slices will appear on the schematic symbol, rather than pins for the whole register. The bits of a register that have not been assigned to a slice will be unused. Command Set A command set is a collection of commands, grouped into one or more command classes. Each command allows an operation to be enabled on connected logic. Similar to an instruction executed in a program, a command in the set consists of an opcode (command code) and one or more optional operands (data). MSB LSB Opcode: Operand1: AAAAAAAA Operand2: BBBBBBBB Operand3: CCCCCCCC Figure 10. Example command that uses three operands. Note: Opcodes are automatically assigned to commands and are aligned towards the higher order bits. The operands, which are manually defined, should be aligned to the low order bits, and with no gaps between them. The bit ranges of the operands should also not overlap. This item type is defined using the Command Set Properties dialog (Figure 11). Version (v1.0) Apr 28,

13 Figure 11. Configuration dialog for the command set item. Use the dialog to define the following properties for the command set: Name A unique name for the command set. Each item in the custom interface must have a unique name so that there are no name 'clashes' in the schematic document, the generated VHDL code, or the generated C code. Note: If two items in different WB_INTERFACE components in the same design project have the same name, the functions generated in the C code will have the same name, resulting in a name 'clash'. Data Width The width of the data bus, in bits. This value can range from 1 to 32 bits, but must be less than or equal to, the value defined for the width of the Wishbone data bus. Graphical Attributes When the component is placed on a schematic sheet, this property allows you to specify the amount of blank space to be inserted after the item's bank of pins. Immediate Acknowledgement Enable this option to have an acknowledgement sent immediately (and automatically) to the host processor through the ACK_O pin in the Wishbone interface, upon completion of a successful operation. Note: This option should only be enabled if you are sure that the connected logic can quickly read/write data (i.e. within one clock cycle). When this option is disabled, an ACK_I pin will be added to the custom interface for the command set item. The externallyconnected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. Commands and Classes This region of the dialog is used to display and manage the command set's constituent command classes, commands and operands. Use the available buttons (or commands from the right-click menu accessible from within the list area) to add, edit, remove, and reorder command classes and their constituent commands. Version (v1.0) Apr 28,

14 Defining a Command Class When adding or editing a command class, its properties are defined in the Command Class Properties dialog (Figure 12). Use the upper region of the dialog to define a unique name for the class. The lower region is used to display and manage any operands for the class. The command class itself is a collection of commands with the same type of operands. Therefore, any defined operands (and their corresponding outputs) will be shared by all commands in that class. Use the controls in this region of the dialog (buttons or commands from the right-click menu accessible from within the list area) to add, edit, remove, and reorder operand definitions. When adding or editing an operand, its properties are defined in the Operand Properties dialog. From here, you define a unique name for the operand, and its bit range in terms of Start (low order bit) and End (high order bit) indices. The start and end indices are inclusive Note: Within the same command class, all operands and commands must have unique names. Figure 13 illustrates the definition of an operand named BANK_NUM. It is 4 bits in size and is specified to be aligned to the lower 4 bits of a command that uses it. Figure 13 also illustrates the resulting entry for the operand in the Commands and Classes region of the main Command Set Properties dialog. Figure 12. Configuration dialog for a command class. Figure 13. Example operand definition. From Figure 13 we can see that the data width for the parent command set item has been set to 32 bits. The operand BANK_NUM, is 4 bits. In the command class REG to which this operand is associated, there is a single command BANK. As can be seen, this 32-bit command is comprised of a 1-bit opcode ("0"), 27 unused bits ("XXXXXXXXXXXXXXXXXXXXXXXXXXX") and the 4-bit operand ("AAAA"). The unused bits are neither part of the opcode, nor the operand and will simply be ignored. With 28 bits available for the opcode, this command class can support a maximum of 2 28 commands (all of which would use the 4-bit operand, BANK_NUM). To hit home the importance of correct operand definition and alignment, consider the following example of non-optimal operand definition: A command set with data width 32 bits A command class with two defined operands: - Operand1 8 bits located in the bit range Operand2 8 bits located in the bit range Figure 14 illustrates the make-up of a generic command added to this command class. MSB LSB Opcode Operand1: AAAAAAAA Operand2: BBBBBBBB Figure 14. Resulting command based on operand definition. Version (v1.0) Apr 28,

15 As mentioned previously, the opcode is automatically assigned to a command, and aligned to the higher order bits. From Figure 14 we can see that because of the way in which the two operands have been defined, only a 2-bit opcode can be generated. This allows for a maximum of 2 2 = 4 commands in this particular command class. If the bit ranges for the operands were edited, so that they are aligned to the right and with no spaces between them, there would be 16 bits available to opcode assignment. This would result in a maximum of 2 16 = commands definable for the command class. Defining a Command When adding or editing a command, its properties are defined in the Command Properties dialog (Figure 15). Simply give the command a unique name. The opcode for the command will automatically be assigned, taking into account any defined operands for the command class into which the command is added. Note: Within the same command class, all commands and operands must have unique names. Each command will have a corresponding output pin in the interface, which will be driven High when enabled. Troubleshooting Figure 15. Example command definition. Sometimes adding an operand or command will fail. This happens because Altium Designer is unable to assign an opcode to all commands. When this happens, try one or more of the following solutions: Increase the data width of the command set if it is currently less than 32 bits Check that all operands are aligned to the low order bits, with no gaps between them Decrease the width of some operands if their expected range of values is smaller than the allocated width Remove some commands if they are not really needed. If none of the above solutions offer a viable possibility, simply add another command set to the custom interface and define the required additional commands and operands there. External Address Range An external address range allows access to a block of addresses on connected logic. This item type is defined using the External Address Range Properties dialog (Figure 16). Figure 16. Configuration dialog for the external address range item. Use the dialog to define the following properties for the external address range: Version (v1.0) Apr 28,

16 Name A unique name for the address range. Each item in the custom interface must have a unique name so that there are no name 'clashes' in the schematic document, the generated VHDL code, or the generated C code. Note: If two items in different WB_INTERFACE components in the same design project have the same name, the functions generated in the C code will have the same name, resulting in a name 'clash'. Data Width The width of the data bus, in bits. This value can range from 1 to 32 bits, but must be less than or equal to, the value defined for the width of the Wishbone data bus. IO Type The direction of data access. You can specify Read, Write, or Read/Write. Immediate Acknowledgement Enable this option to have an acknowledgement sent immediately (and automatically) to the host processor through the ACK_O pin in the Wishbone interface, upon completion of a successful operation. Note: This option should only be enabled if you are sure that the connected logic can quickly read/write data (i.e. within one clock cycle). When this option is disabled, an ACK_I pin will be added to the custom interface for the external address range item. The connected logic must take this pin High to generate the acknowledge signal (High) on the WB_INTERFACE'S ACK_O line to the host processor. Address Width The width of the address bus (ADR_O) to the connected logic, in bits. This value can range from 0 bits (Range = 1) to 32 bits (Range = 4GB). The base address is automatically assigned to an external address range item. In the main Configure (Wishbone Interface) dialog, the Item Address will reflect the address range in hex and binary format. Consider a WB_INTERFACE component configured with a single external address range item with a 5-bit address width. The Item Address will appear as: 0x00 0x1F (XXXXX) As there is only one item in the interface, no bits are used to decode the item. Therefore all five bits (XXXXX) are forwarded to the connected logic in order to select an address in that component. To Read/Write address XXXXX on the component, put XXXXX on the Wishbone ADR_I bus. Now consider a second external address range item added to the interface, with an 8-bit address width. The Item Address entries for the two items will appear as: 5-bit width item: 0x100 0x11F (1000XXXXX) 8-bit width item: 0x000 0x0FF (0XXXXXXXX) Looking at our 5-bit width item, the 1000 prefix is used to decode the item, and the XXXXX bits are forwarded to the connected logic to select the required address. To Read/Write address XXXXX on the component, put 1000XXXXX on the Wishbone ADR_I bus. Note: The generated C code handles the different addressing modes. Graphical Attributes When the component is placed on a schematic sheet, this property allows you to specify the amount of blank space to be inserted after the item's bank of pins. Version (v1.0) Apr 28,

17 Operational Overview The following sections take a closer look at the operation of each of the supported item types, with respect to the custom interface. Information on the generated C code is also given. Internal Register Operation The internal register item is very similar in operation to a Port I/O component. When active (addressed by the host) it can latch output values to, and read input values from, the connected logic within one clock cycle. Therefore, immediate acknowledgements are automatically sent to the host after a successful operation. If the register is divided into slices, the data coming from the host on the Wishbone DAT_I bus will be divided into the configured slices and forwarded to the connected logic. Note: Write values are stored internally in the WB_INTERFACE component and therefore persist until they are changed. The following two sections detail what happens during read and write cycles respectively. Read cycle The host processor drives CYC_I and STB_I High and presents the address of the register on the ADR_I bus. WE_I is Low. Within 1 clock cycle: The address of the register is decoded The register data from the connected logic is put on the DAT_O bus ACK_O is driven High Seeing that the ACK_O signal is High, the processor terminates the read cycle, taking STB_I and CYC_I Low. Write cycle The host processor drives CYC_I and STB_I High and presents the address of the register on the ADR_I bus and the data to be sent to the connected logic on the DAT_I bus. WE_I is High. Within 1 clock cycle: The address of the register is decoded ACK_O is driven High At the next rising edge of CLK_I, the data on the DAT_I bus will be latched into the WB_INTERFACE's internal register(s) and forwarded to the connected logic. Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low. Generated C Functions The following example functions are generated for a sliced internal register item, named BIG. This item is configured for Read and Write, has an 8-bit data width and two register slices HI (BIG[7..4]) and LO (BIG[3..0]). // // Functions for the register: BIG // extern uint8_t wb_interface_get_big( uint32_t a_addr_base ); extern uint8_t wb_interface_get_big_lo( uint32_t a_addr_base ); extern uint8_t wb_interface_get_big_hi( uint32_t a_addr_base Version (v1.0) Apr 28,

18 ); extern void wb_interface_set_big( uint32_t a_addr_base, uint8_t a_value ); extern void wb_interface_set_big_slices( uint32_t a_addr_base, uint8_t lo, uint8_t hi ); For each function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project. For write functions, you will also need to supply the required data value. There are get and set methods to read/write the entire register wb_interface_get_big() and wb_interface_set_big(). Additionally, there is a set method which allows you to give separate values for the slices wb_interface_set_big_slices(). The function will combine the slice values into a single datum and write this to the register. There are also get methods for the individual slices in the register. Command Set Operation The opcode (plus any operands) is written to the command set's address. This is received from the host processor through the DAT_I bus of the Wishbone interface. The opcode is decoded and the selected command's output pin is driven High. The command's operands, if it has any, will be forwarded to the connected logic. An acknowledgement is sent to the host automatically on the ACK_O line of the Wishbone interface, if the Immediate Acknowledgement option for the command set is enabled. Otherwise, the connected logic needs to send the acknowledgement itself when it is done. The following section details what happens during a write cycle. Write cycle The host processor drives CYC_I and STB_I High and presents the address of the command set on the ADR_I bus, and the opcode + operand on the DAT_I bus. WE_I is High. Within 1 clock cycle: The address of the command set is decoded The opcode is decoded The selected command's output pin is driven High The command's operands (if it has any) are now valid ACK_O is driven High if the Immediate Acknowledgement option for the command set item is enabled. If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available CSName_ACK_I pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor. Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low. The output pin for the command is taken Low and any operands associated with it are no longer valid. Generated C Functions The following example function is generated for a command set item, named CHANGE. This item has a 32-bit data width and a single command class REG. Defined within this class is a single command, BANK, which has an associated 4-bit operand, BANK_NUM. Version (v1.0) Apr 28,

19 // // Functions for the command set: CHANGE // extern void wb_interface_set_change_reg_bank( uint32_t a_addr_base, uint8_t bank_num ); The above function activates the command BANK. For this function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project. You also need to supply the value for the BANK_NUM operand. The C code will handle the opcodes. External Address Range Operation When the address range item is selected, the RD or WR pin is driven High. The address is also forwarded to the connected logic, and the data is forwarded to or retrieved from that component. The data and address buses to the connected logic are only valid when one of RD or WR is High. An acknowledgement is sent to the host automatically on the ACK_O line of the Wishbone interface, if the Immediate Acknowledgement option is enabled for the item. Otherwise, the connected logic needs to send the acknowledgement itself when it is done. The following two sections detail what happens during read and write cycles respectively. Read cycle The host processor drives CYC_I and STB_I High and presents an address on the ADR_I bus. WE_I is Low. Within 1 clock cycle: The address code of the external address range is decoded The EARName_RD_O pin is driven High The address on the EARName_ADR_O bus now becomes valid The data from the connected logic on the EARName_DAT_I bus is put on the DAT_O bus ACK_O is driven High if the Immediate Acknowledgement option for the external address range item is enabled. If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available EARName_ACK_I pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor. Seeing that the ACK_O signal is High, the processor terminates the read cycle, taking STB_I and CYC_I Low. The EARName_RD_O pin is driven Low and the EARName_DAT_I and EARName_ADR_O lines are no longer valid. Write cycle The host processor drives CYC_I and STB_I High and presents an address on the ADR_I bus data to be sent to the connected logic on the DAT_I bus. WE_I is High. Within 1 clock cycle: The address code of the external address range is decoded The EARName_WR_O pin is driven High The address on the EARName_ADR_O bus now becomes valid The data on the EARName_DAT_O bus now becomes valid ACK_O is driven High if the Immediate Acknowledgement option for the external address range item is enabled. If the Immediate Acknowledgement option is disabled, the connected logic will need to send the acknowledgement through the available EARName_ACK_I pin of the interface when it is done. This will be forwarded through to the ACK_O line to the processor. Version (v1.0) Apr 28,

20 Seeing that the ACK_O signal is High, the processor terminates the write cycle, taking STB_I and CYC_I Low. The EARName_WR_O pin is driven Low and the EARName_DAT_O and EARName_ADR_O lines are no longer valid. Generated C Functions The following example functions are generated for an external address range item, named REG. This item is configured for Read and Write, has a 32-bit data width and a 5-bit address bus. // // Functions for the address range: REG // extern uint32_t wb_interface_get_reg( uint32_t a_addr_base, uint32_t a_offset ); extern void wb_interface_set_reg( uint32_t a_addr_base, uint32_t a_offset, uint32_t a_value ); For each function, you need to supply the base address of the WB_INTERFACE component. This can be found in the hardware.h file, generated from the design project. The offset is the address which should be forwarded to the connected logic. There is no need to worry about byte or word addressing, as the C code handles this. Version (v1.0) Apr 28,

21 Revision History Date Version No. Revision 28-Apr Initial release 29-Aug Updated template. Software, hardware, documentation and related materials: Copyright 2011 Altium Limited. All rights reserved. You are permitted to print this document provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the document is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, Altium Designer, Board Insight, DXP, Innovation Station, LiveDesign, NanoBoard, NanoTalk, OpenBus, P-CAD, SimCode, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed. Version (v1.0) Apr 28,