WB_SDHC - Wishbone SDHC Controller
|
|
- Dennis Bridges
- 5 years ago
- Views:
Transcription
1 WB_SDHC - Wishbone SDHC Controller Frozen Content Modified by Admin on Sep 13, 2017 Parent article: FPGA Peripheral Components - Wishbone WB_SDHC - Wishbone SDHC Controller. The Wishbone SDHC Controller component (WB_SDHC) provides an interface that enables a host processor to efficiently communicate with a Secure Digital (SD) or Secure Digital High-Capacity (SDHC) storage device resident outside of the physical FPGA device to which the design is targeted. Communication is over a 4-bit parallel data bus, with control implemented using a single-bit command bus. The WB_SDHC can be used with any of the 32-bit processors available in Altium Designer.
2 Features at-a-glance Transmit commands through a simple register-based interface Receive command responses through a FIFO-based interface Transmit data block-wise through a 32-bit DMA interface Receive data multiple-block-wise through the same DMA interface Maximum clock speed on SD is one quarter the system frequency Maximum raw transfer speed of 6.25MByte/s (based on a system clock of 50MHz) Maximum Read/Write speeds through file system (tested using a TSK3000A at 50MHz): Read: 7MByte/s (depends on SD/SDHC card used) Write: 5MByte/s (depends on SD/SDHC card used) CRC on both command and data interfaces Wishbone-compliant Availability From an OpenBus System document, the SDHC Controller component can be found in the Peripherals region of the OpenBus Palette panel. From a schematic document, the WB_SDHC component can be found in the FPGA Peripherals (Wishbone) integrated library (FPGA Peripherals (Wishbone).IntLib), located in the \Library\Fpga folder of the installation. Pin Description The following pin description is for the WB_SDHC component when used on the schematic. In an OpenBus System, although the same signals are present, the abstract nature of the system hides the pin-level Wishbone interfaces. The external interface signals will be made available as sheet entries, associated with the parent sheet symbol used to reference the underlying OpenBus System. Work In Progress Operational Overview The following sections outline the basic procedure in order to initiate communications with the target SD/SDHC Card. Card Detection and Removal Two bits in the Status register are available to check if a card is inserted and/or has been changed: Bit 0 reflects the state of the input pin SD_DETECT. It is '1' if there is a card inserted.
3 Bit 2 is set if the card is removed. It stays '1' until you write a '1' into the bit from software. Thus, if this bit is set, you must re-initialize the SD Card before further use. Transmitting Commands A commands always consists of 48 bits. It contains a start bit ('0'), a direction bit (host to card: '1'), 6 command bits, 32 argument bits, a 7-bit CRC and a stop bit ('1'). In order to transmit a command: Write the command to the CMD_TXCMD register Write the argument to the CMD_TXARG register Set the CMD_TXENABLE bit in the Control register Wait until the CMD_TXENABLE bit disappears from the Status register Wait until the CMD_TXBUSY bit disappears from the Status register Receiving Responses A response consists of 48 or 136 bits and can include a CRC. It always starts with a start bit ('0') a direction bit ('0' as well) and ends with a stop bit ('1'). In order to reliably receive a response, you should indicate you want to receive an answer at the same time you set up the transmission, as follows: Write the command to the CMD_TXCMD register Write the argument to the CMD_TXARG register Write the expected number of response bytes (excluding CRC) in the CMD_RXSIZE register Set the CMD_TXENABLE and CMD_RXENABLE bits in the Control register Wait until the CMD_TXENABLE bit disappears from the Status register Wait until the CMD_TXBUSY bit disappears from the Status register Setup a timeout for the receiver While timeout did not elapse, check FIFO and copy response into memory. Stop if you've got all bytes you want Check for timeout, busy, rxempty and CRC. Even though a message can contain up to 136 bits, the FIFO is large enough to store 16 bytes. The 17th byte in a long message always contains the CRC of the payload and is stripped by the WB_SDHC. Transmitting Data Data transmission can be done in single-block mode only. However, the SD Card protocol implements
4 a multi-block write command that can be used to transmit individual blocks in succession. It is not needed to send data using the single_block_write command. In order to transmit data, send the write_single_block command (SDMEM command 24) and wait for response as usual. Then: 6. Set block size to physical block size of SD Card (in bytes) Set DMA address to where data is stored in memory Set the DAT_TXENABLE bit in the Control register Wait for DAT_TXENABLE to disappear from the Status register Wait for DAT_TXBUSY to disappear from the Status register Check for overrun and CRC errors If you want to send multiple blocks, send a write_multiple_block command (SDMEM command 25), wait for response, than execute steps 1 and 2 only once and loop steps 3 6 until done. Then send a transmission_stop command (SDMEM command 12). Transmitting data may be followed by the card being busy. Check for DAT_READY before starting a new read- or write-cycle. Receiving Data If you are ready to receive data, you should: Write the buffer address (must be in external memory!) into the DAT_MEMADR register Write the SD card's physical block size in the DAT_BLKSIZE register Write the number of bytes you want to receive in the DAT_RXSIZE register Arm the data receiver by setting DAT_RXENABLE in the Control register Transmit and wait for the response to the data read command (SDMEM: cmd17 or cmd18) Setup the data timeout Wait while timeout did not elapse and DAT_RXBUSY in the Status register is not set If DAT_RXBUSY is set, wait for it to disappear (timeout error otherwise) If reading multiple blocks, sent a stop message 10. Check data CRC and DMA timeout status bits
5 DMA Interface The DMA interface consists of a 32-bit wishbone-compliant master bus. It currently has 20 address bits (19..0), from which the lower 2 bits are fixed to '0'. Reads and writes thus always are word-wide (MEM_SEL_O[.0] are fixed to '1') and they are 32-bit aligned. The core assumes memory access is big endian hosted, thus the first nibble in a card to host transmission is written on MEM_DAT_O[3.28], the second on MEM_DAT_O[27..24] and so on. In line with this, the host should write big endian style when preparing data for transmission to the card (MEM_DAT_I[3.28] should contain the first nibble to be transmitted). The WB_SDHC core needs access to the memory every 8 SD_CLK cycles. The maximum frequency of SD_CLK is CLK_I / Since most SD cards accept faster clock speeds than this, the WB_SDHC DMA unit typically will require access to memory every 32 system clock cycles during data transfer. You must make sure in your design that this requirement is met or you will at one time run into DMA errors! Register Interface Main article: WB_SDHC - Accessible Internal Registers Address Name Function 0000 (00h) CDIV 10-bit clock divider 0001 (01h) CTRL Control register 0010 (02h) STAT Status register 0011 (03h) CMD_TXCMD Command transmitter command code 0100 (04h) CMD_TXARG Command transmitter argument 0101 (05h) CMD_RXSIZE Command Receiver size 0110 (06h) CMD_RXFIFO Command Receiver FIFO 0111 (07h) DAT_BLKSIZE Data block size (in bytes) 1000 (08h) DAT_RXSIZE Data transfer size 1001 (09h) DAT_MEMADR DMA address for data Read/Write 1111 (0Fh) VERSION_INFO Version and configuration Software Platform Support The WB_SDHC is fully supported by the Software Platform. All registers of the peripheral are described in per_sdhc.h, a device driver is available in drv_sdhc.c and drv_sdhc.h. See online documentation for a full description of its interface. The driver connects to the posix Block Device I/O system if required, thus directly providing support for the posix filesystem.
6 Hardware wrapper and driver for the WB_SDHC, as part of a defined Software Platform. Associated Design Interface Component The following table summarizes the available design interface component that can be placed from the relevant port-plugin library for access to, and communications with, an SD/SDHC memory card inserted into: The SD Card reader accessible by the User FPGA on a 3000-series NanoBoard (port-plugin library: FPGA NB3000 Port-Plugin.IntLib). The SD Card reader resident on a Mass Storage peripheral board (PB02) attached to a NanoBoard NB2 (port-plugin library: FPGA PB02 Port-Plugin.IntLib). Component Symbol Component Name Description SDHC Place this component to interface to the Secure Digital (SD) card reader and write/read an SD or SDHC memory card inserted within. Resource Usage As a rough guide (subject to change!) on a Xilinx Spartan3, the core currently takes approx. 761 LUTs, 8 dual port 16x1D RAMs and 456 register bits.
7 Example Reference Design An example design, demonstrating the use of the SDHC Controller peripheral, is included as part of your Altium Designer installation: sdhc_memory_card.prjfpg located in the \Examples\Soft Designs\Storage\SDHC Memory Card folder. See Also WB_SDCARD - Wishbone SD Card Controller Source URL:
WB_MP3DEC - Wishbone MP3 Decoder
WB_MP3DEC - Wishbone MP3 Decoder Frozen Content Modified by on 13-Sep-2017 Parent article: FPGA Peripheral Components - Wishbone WB_MP3DEC - Wishbone MP3 Decoder. The Wishbone MP3 Decoder component (WB_MP3DEC)
More informationNanoBoard Configuring an FPGA Project Automatically. Identifying System Hardware. Modified by Admin on Sep 13, 2017
NanoBoard 3000 - Configuring an FPGA Project Automatically Frozen Content Modified by Admin on Sep 13, 2017 Parent article: Understanding the NanoBoard 3000 Constraint System Although an FPGA design project
More informationWB_INTERCON - Interfacing. Connecting Single Slave Devices. Modified by Admin on Sep 13, 2017
WB_INTERCON - Interfacing Frozen Content Modified by Admin on Sep 13, 2017 The WB_INTERCON component can be used to connect to one or more slave memory or peripheral I/O devices. The following sections
More informationWB_INTERFACE Custom Wishbone Interface
WB_INTERFACE Custom Wishbone Interface Summary This document provides detailed reference information with respect to the WB_INTERFACE peripheral component. This component enables you to build custom Wishbone
More informationWB_UART8 Serial Communications Port
Summary This document provides detailed reference information with respect to the UART peripheral device. Core Reference CR0157 (v3.1) August 01, 2008 Serial ports on embedded systems often provide a 2-wire
More informationEMAC8, EMAC8_MD Ethernet Media Access Controller
EMAC8, EMAC8_MD Ethernet Media Access Controller Summary This document provides detailed reference information with respect to the non-wishbone EMAC peripheral components, EMAC8 and EMAC8_MD. The 8-bit
More informationSDRAM Interface Clocking for the NanoBoard 2
SDRAM Interface Clocking for the NanoBoard 2 NB2 + DB30 Xilinx Spartan 3 DaughterBoard 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port Plugin wiring. NB2 + DB31 Altera Cyclone II DaughterBoard
More informationThe following sections detail the internal registers for the WB_OWM that can be accessed from the host processor.
WB_OWM - Accessible Internal Registers Frozen Content Modified by Admin on Sep 13, 2017 The following sections detail the internal registers for the WB_OWM that can be accessed from the host processor.
More informationSoftware development from a bird's eye view Ulrich Kloidt, Senior Application Engineer, Altium Europe GmbH
Software development from a bird's eye view Ulrich Kloidt, Senior Application Engineer, Altium Europe GmbH A modular software application can help designers focus on the essential part of their task -
More informationSDRAM Interface Clocking for the NB3000
SDRAM Interface Clocking for the NB3000 Frozen Content Modified by on 6-Nov-2013 NB3000XN 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port PlugIn wiring. NB3000AL 1. Altera PLL wiring. 2.
More informationPB30 Prototyping Peripheral Board
PB30 Prototyping Peripheral Board Frozen Content Mod ifi ed by Adm in on Feb 10, 201 4 Additional Resources Datasheet Board Schematics Parent article: Peripheral Boards Altium's Prototyping peripheral
More informationSRL0 Serial Port Unit
Summary The serial communications port peripheral devices can be configured for communications between a microprocessor and peripheral devices, or for multiprocessor communications. This document provides
More informationWB_INTERFACE - Pin Description
WB_NTERFACE - Pin Description Frozen Content Modified by Admin on Sep 13, 2017 The following pin description is for the WB_NTERFACE component when used on the schematic. n an penbus System, although the
More informationNanoBoard MIDI Interface
NanoBoard 3000 - MIDI Interface Frozen Content Mod ifi ed by Adm in on Nov 6, 201 3 The NanoBoard 3000 caters for transmission and reception of signals in accordance with the MIDI (Musical Instrument Digital
More informationTutorial - Getting Started with the Innovation Station
Tutorial - Getting Started with the Innovation Station Old Content - visit altium.com/documentation Modified by on 13-Sep-2017 This documentation is now considered legacy - Altium no longer manufactures,
More informationSD Card Controller IP Specification
SD Card Controller IP Specification Marek Czerski Friday 30 th August, 2013 1 List of Figures 1 SoC with SD Card IP core................................ 4 2 Wishbone SD Card Controller IP Core interface....................
More informationConfigurable Generic Library
Configurable Generic Library Frozen Content Modified by on 13-Sep-2017 Altium Designer Winter 09 heralds the arrival of a new integrated library of configurable generic FPGA logic components FPGA Configurable
More informationAltiumLive - Content Store
AltiumLive - Content Store Frozen Content Modified by on 13-Sep-2017 Introducing the AltiumLive Content Store. The Content Store is an area in AltiumLive dedicated to content - content that is invaluable
More informationSummary. Seeing is Believing - Read More and Watch Demos of Altium Designer
Whats New in Altium Designer 6.9 Summary Altium Designer 6.9 brings significant refinements to 3D PCB Visualization combined with a number of smaller enhancements and improved system-wide support for existing
More informationHello, and welcome to this presentation of the STM32 I²C interface. It covers the main features of this communication interface, which is widely used
Hello, and welcome to this presentation of the STM32 I²C interface. It covers the main features of this communication interface, which is widely used to connect devices such as microcontrollers, sensors,
More informationThe Software Platform consists of device stacks and software services. This section describes both parts and how they are related to each other.
Organization of the Software Platform Frozen Content Modified by Admin on Sep 13, 2017 Introduction to the Software Platform Organization of the Software Platform Using the Software Platform Builder Glossary
More informationTech Spec for SDXC Host Controller
Tech Spec for SDXC Host Controller iwave Systems Technologies Pvt. Ltd. Page 1 of 16 Table of Contents 1 Introduction 4 1.1 Overview 4 1.2 Features 4 1.3 Acronyms and Abbreviations 5 2 Host Controller
More informationPowerPC on NetFPGA CSE 237B. Erik Rubow
PowerPC on NetFPGA CSE 237B Erik Rubow NetFPGA PCI card + FPGA + 4 GbE ports FPGA (Virtex II Pro) has 2 PowerPC hard cores Untapped resource within NetFPGA community Goals Evaluate performance of on chip
More informationAltium Designer Functional Areas
Altium Designer Functional Areas Why Data Management The Idea behind Altium Designer Copyright 2013 Altium Limited Functional units of AD JK, v 2.3 2 ONE Tool for each Electronic Design Engineer What exactly
More informationSecure Digital Input/Output (SDIO) Host Controller Data Sheet
Secure Digital Input/Output (SDIO) Host Controller Sheet Device Highlights Proven System Block (PSB) for QuickLogic Customer Specific Standard Products (CSSPs) QuickLogic CSSPs are architected from a unique
More information32-bit VGA Controllers - Host to Controller Communications
32-bit VGA Controllers - Host to Controller Communications Frozen Content Modified by Admin on Nov 6, 2013 Communications between a 32-bit host processor and a 32-bit VGA Controller are carried out over
More informationPMC-HPDI32A-ASYNC High-speed Serial I/O PCI Board
PMC-HPDI32A-ASYNC High-speed Serial I/O PCI Board Features Include: Data rate of 5.0 megabits per second 8 Bits transmitter. LSB First. Software Selectable Even / Odd Parity. Software Selectable No Parity
More informationAdvanced FPGA Design Methodologies with Xilinx Vivado
Advanced FPGA Design Methodologies with Xilinx Vivado Lecturer: Alexander Jäger Course of studies: Technische Informatik Student number: 3158849 Date: 30.01.2015 30/01/15 Advanced FPGA Design Methodologies
More informationFor reference only Refer to the latest documents for details
STM32F3 Technical Training For reference only Refer to the latest documents for details Serial peripheral interface SPI 3 SPI Features (1/2) 3 Full duplex synchronous transfers (3 lines) Half duplex/simplex
More informationAN5200. Getting started with STM32H7 Series SDMMC host controller. Application note. Introduction
Application note Getting started with STM32H7 Series SDMMC host controller Introduction The SDMMC (secure digital multimedia card) host interface in the STM32H7 Series provides an interface between the
More informationcpci-dart Base-Board & Daughter-Board
DYNAMIC ENGINEERING 150 DuBois, Suite C Santa Cruz, CA 95060 (831) 457-8891 Fax (831) 457-4793 http://www.dyneng.com sales@dyneng.com Est. 1988 User Manual cpci-dart Base-Board & Daughter-Board Eight-Channel
More informationOctober 9, 2018 Product Specification Rev1.1. Core Facts. Documentation. Design File Formats. Additional Items
October 9, 2018 Product Specification Rev1.1 Design Gateway Co.,Ltd 54 BB Building 14 th Fl., Room No.1402 Sukhumvit 21 Rd. (Asoke), Klongtoey-Nua, Wattana, Bangkok 10110 Phone: 66(0)2-261-2277 Fax: 66(0)2-261-2290
More informationLogiCORE IP AXI Video Direct Memory Access (axi_vdma) (v3.01.a)
DS799 June 22, 2011 LogiCORE IP AXI Video Direct Memory Access (axi_vdma) (v3.01.a) Introduction The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded
More informationPretty Good Protocol - Design Specification
Document # Date effective October 23, 2006 Author(s) Ryan Herbst Supersedes Draft Revision 0.02 January 12, 2007 Document Title Pretty Good Protocol - Design Specification CHANGE HISTORY LOG Revision Effective
More informationPage 1 SPACEWIRE SEMINAR 4/5 NOVEMBER 2003 JF COLDEFY / C HONVAULT
Page 1 SPACEWIRE SEMINAR 4/5 NOVEMBER 2003 JF COLDEFY / C HONVAULT INTRODUCTION The SW IP was developped in the frame of the ESA 13345/#3 contract "Building block for System on a Chip" This presentation
More information11. SD/MMC Controller
11. SD/MMC Controller November 2012 cv_54011-1.1 cv_54011-1.1 The hard processor system (HPS) provides a Secure Digital/MultiMediaCard (SD/MMC) controller for interfacing to external SD and MMC flash cards,
More informationDesign Portability, Configurations and Constraints
Design Portability, Configurations and Constraints Summary This article describes what is required for design portability, and the role of configurations and constraints in achieving this portability.
More informationA (Very Hand-Wavy) Introduction to. PCI-Express. Jonathan Heathcote
A (Very Hand-Wavy) Introduction to PCI-Express Jonathan Heathcote Motivation Six Week Project Before PhD Starts: SpiNNaker Ethernet I/O is Sloooooow How Do You Get Things In/Out of SpiNNaker, Fast? Build
More informationIntegrated Device Technology, Inc Stender Way, Santa Clara, CA Phone #: (408) Fax #: (408) Errata Notification
Integrated Device Technology, Inc. 2975 Stender Way, Santa Clara, CA - 95054 Phone #: (408) 727-6116 Fax #: (408) 727-2328 Errata Notification EN #: IEN01-02 Errata Revision #: 11/5/01 Issue Date: December
More informationCPCI-HPDI32ALT High-speed 64 Bit Parallel Digital I/O PCI Board 100 to 400 Mbytes/s Cable I/O with PCI-DMA engine
CPCI-HPDI32ALT High-speed 64 Bit Parallel Digital I/O PCI Board 100 to 400 Mbytes/s Cable I/O with PCI-DMA engine Features Include: 200 Mbytes per second (max) input transfer rate via the front panel connector
More informationWB_INTERFACE - Configuring Item Types
WB_INTERFACE - Configuring Item Types The following sections take a closer look at configuration of each of the supported item types Internal Register, Co mmand Set, External Address Range with respect
More informationNB2DSK01 - TFT LCD Panel (with Touch Screen)
NB2DSK01 - TFT LCD Panel (with Touch Screen) Frozen Content Modified by on 6-Nov-2013 The NB2DSK01 provides high quality color display through a Hitachi TX09D50VM1CAA TFT (Thin Film Transistor) LCD panel.
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP TFT Controller General Description The Digital Blocks TFT Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 to a TFT panel. In an FPGA,
More informationExternal Parallel Port to Internal Wishbone Interface
Page 1 of 5 Revision History Revision Date Author Description 0.1 2008-06-22 Thomas Thanner Initial Version Author TTHA Date 2008-06-22 File wbc_parallel_master-spec_doc-r01.odt Page 2 of 5 1 Introduction
More informationUSB3DevIP Data Recorder by FAT32 Design Rev Mar-15
1 Introduction USB3DevIP Data Recorder by FAT32 Design Rev1.1 13-Mar-15 Figure 1 FAT32 Data Recorder Hardware on CycloneVE board The demo system implements USB3 Device IP to be USB3 Mass storage device
More informationPower Monitoring on the Desktop NanoBoard NB2DSK01
Power Monitoring on the Desktop NanoBoard NB2DSK01 Summary This application note provides information on the Power Monitoring functionality provided for the Desktop NanoBoard NB2DSK01. It covers how this
More informationATAES132A Firmware Development Library. Introduction. Features. Atmel CryptoAuthentication USER GUIDE
Atmel CryptoAuthentication ATAES132A Firmware Development Library USER GUIDE Introduction This user guide describes how to use the Atmel CryptoAuthentication ATAES132A Firmware Development Library with
More informationIntellectual Property Macrocell for. SpaceWire Interface. Compliant with AMBA-APB Bus
Intellectual Property Macrocell for SpaceWire Interface Compliant with AMBA-APB Bus L. Fanucci, A. Renieri, P. Terreni Tel. +39 050 2217 668, Fax. +39 050 2217522 Email: luca.fanucci@iet.unipi.it - 1 -
More informationXAPP170 May 19, 1999 (Version 1.0) Application Note
XAPP170 May 19, 1999 (Version 1.0) Application Note Summary This application note illustrates the use of Spartan devices in an ISDN modem. The design example shows how cost effective a Spartan device can
More informationUser Guide Gennum GN4124 to Wishbone bridge
ORGANISATION EUROPÉENNE POUR LA RECHERCHE NUCLÉAIRE EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH CERN BE-CO-HT User Guide Gennum GN4124 to Wishbone bridge May 2010 Edited by: Simon Deprez Checked by: Erik
More informationHello, and welcome to this presentation of the STM32 Low Power Universal Asynchronous Receiver/Transmitter interface. It covers the main features of
Hello, and welcome to this presentation of the STM32 Low Power Universal Asynchronous Receiver/Transmitter interface. It covers the main features of this interface, which is widely used for serial communications.
More informationEach I2C master has 8-deep transmit and receive FIFOs for efficient data handling. SPI to Dual I2C Masters. Registers
February 205 Introduction Reference Design RD73 I2C and SPI are the two widely used bus protocols in today s embedded systems. The I2C bus has a minimum pin count requirement and therefore a smaller footprint
More informationSDC/MMC Controller. Author: [Adam Edvardsson]
SDC/MMC Controller Author: [Adam Edvardsson] [adam@orsoc.se] Rev. [0.1] May 23, 2009 OpenCores SD/MMC controller specification 5/23/2009 This page has been intentionally left blank. www.opencores.org Rev
More informationSundance Multiprocessor Technology Limited. Capture Demo For Intech Unit / Module Number: C Hong. EVP6472 Intech Demo. Abstract
Sundance Multiprocessor Technology Limited EVP6472 Intech Demo Unit / Module Description: Capture Demo For Intech Unit / Module Number: EVP6472-SMT391 Document Issue Number 1.1 Issue Data: 19th July 2012
More informationLogiCORE IP AXI DMA (v4.00.a)
DS781 June 22, 2011 Introduction The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth
More informationAchieving UFS Host Throughput For System Performance
Achieving UFS Host Throughput For System Performance Yifei-Liu CAE Manager, Synopsys Mobile Forum 2013 Copyright 2013 Synopsys Agenda UFS Throughput Considerations to Meet Performance Objectives UFS Host
More informationAdding a Simulation Model to a Component Definition
Adding a Simulation Model to a Component Definition Old Content - see latest equivalent Modified by on 13-Sep-2017 Parent article: Releasing a Component Definition to a Vault On the design side, each design
More informationPCI to SH-3 AN Hitachi SH3 to PCI bus
PCI to SH-3 AN Hitachi SH3 to PCI bus Version 1.0 Application Note FEATURES GENERAL DESCRIPTION Complete Application Note for designing a PCI adapter or embedded system based on the Hitachi SH-3 including:
More informationProduct Technical Brief S3C2412 Rev 2.2, Apr. 2006
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006 Overview SAMSUNG's S3C2412 is a Derivative product of S3C2410A. S3C2412 is designed to provide hand-held devices and general applications with cost-effective,
More informationMISO MOSI Clock. The master and the slave use a protocol based on the following frame structure. Preamble Body Postamble
4.7 Slow Control slow control is used to configure (Write) and check (Read) the functionalities and status of the card, i.e. the functionalities and status of all programmable components, except AGET which
More informationLogiCORE IP AXI DMA (v3.00a)
DS781 March 1, 2011 Introduction The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI DMA engine provides high-bandwidth
More informationExcalibur Solutions Using the Expansion Bus Interface. Introduction. EBI Characteristics
Excalibur Solutions Using the Expansion Bus Interface October 2002, ver. 1.0 Application Note 143 Introduction In the Excalibur family of devices, an ARM922T processor, memory and peripherals are embedded
More informationDesign of an Efficient FSM for an Implementation of AMBA AHB in SD Host Controller
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 11, November 2015,
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP General Description The Digital Blocks LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and
More informationThe following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.
JTAG Viewer Old Content - visit altium.com/documentation Modified by Admin on Nov 6, 2013 The following content has been imported from Legacy Help systems and is in the process of being checked for accuracy.
More informationLogiCORE IP AXI Video Direct Memory Access v4.00.a
LogiCORE IP AXI Video Direct Memory Access v4.00.a Product Guide Table of Contents Chapter 1: Overview Feature Summary............................................................ 9 Applications................................................................
More informationEthernet IP Datalink. Introduction
Object Dictionary 1 Ethernet IP Datalink Introduction The Ethernet Internet Protocol (IP) Datalink object manages the Ethernet communications bus and the messages transmitted on it. This object allows
More informationOUTLINE. SPI Theory SPI Implementation STM32F0 SPI Resources System Overview Registers SPI Application Initialization Interface Examples
SERIAL PERIPHERAL INTERFACE (SPI) George E Hadley, Timothy Rogers, and David G Meyer 2018, Images Property of their Respective Owners OUTLINE SPI Theory SPI Implementation STM32F0 SPI Resources System
More informationUART Register Set. UART Master Controller. Tx FSM. Rx FSM XMIT FIFO RCVR. i_rx_clk o_intr. o_out1 o_txrdy_n. o_out2 o_rxdy_n i_cs0 i_cs1 i_ads_n
October 2012 Reference Design RD1138 Introduction The Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel conversion on data characters received from a peripheral device or a
More informationGraphical Display of Power Monitoring Data
Graphical Display of Power Monitoring Data Frozen Content Modified by on 6-Nov-2013 Display of power monitoring information in tabular format is good, but a visual representation of the values over time
More informationThe Nios II Family of Configurable Soft-core Processors
The Nios II Family of Configurable Soft-core Processors James Ball August 16, 2005 2005 Altera Corporation Agenda Nios II Introduction Configuring your CPU FPGA vs. ASIC CPU Design Instruction Set Architecture
More informationUSB Framework, IP Core and related software Tropea S.E., Melo R.A.
USB Framework, IP Core and related software Tropea S.E., Melo R.A. Why? We develop embedded systems that usually connect to a PC. Parallel and serial ports obsolete in favor of USB. Faster Plug & play
More informationLogiCORE IP AXI Video Direct Memory Access (axi_vdma) (v3.00.a)
DS799 March 1, 2011 LogiCORE IP AXI Video Direct Memory Access (axi_vdma) (v3.00.a) Introduction The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded
More informationEl Camino Training - Engineering - Consultancy
El Camino Training - Engineering - Consultancy SD BUS Core with Avalon Interface General Description The SD BUS Core with Avalon Interface allows the easy access of SOPC Builder systems to standard Secure
More informationThe Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1].
Lekha IP 3GPP LTE FEC Encoder IP Core V1.0 The Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS 36.212 V 10.5.0 Release 10[1]. 1.0 Introduction The Lekha IP 3GPP LTE FEC Encoder IP Core
More information32 Channel HDLC Core V1.2. Applications. LogiCORE Facts. Features. General Description. X.25 Frame Relay B-channel and D-channel
May 3, 2000 Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com Features
More informationFPGA-BASED DATA ACQUISITION SYSTEM WITH RS 232 INTERFACE
FPGA-BASED DATA ACQUISITION SYSTEM WITH RS 232 INTERFACE 1 Thirunavukkarasu.T, 2 Kirthika.N 1 PG Student: Department of ECE (PG), Sri Ramakrishna Engineering College, Coimbatore, India 2 Assistant Professor,
More informationInput/Output Systems
Input/Output Systems CSCI 315 Operating Systems Design Department of Computer Science Notice: The slides for this lecture have been largely based on those from an earlier edition of the course text Operating
More informationGAISLER. SpaceWire CODEC with RMAP GRSPW / GRSPW-FT CompanionCore Data Sheet
SpaceWire CODEC with RMAP GRSPW / GRSPW-FT CompanionCore Data Sheet Features Full implementation of SpaceWire standard ECSS-E-ST-50-12C Protocol ID extension ECSS-E-ST-50-11C RMAP protocol ECSS-E-ST-50-11C
More informationSMT743 APPLICATION NOTE 1 APPLICATION NOTE 1. Application Note - SMT743 System.doc SMT743 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD.
APPLICATION NOTE 1 Application Note - SMT743 System. SMT743 SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD. Date 23/05/2011 Revision 1 Page 1 of 8 Date Comments / Changes Author Revision 23/05/11 Original Document
More informationLatticeMico32 SPI Flash Controller
LatticeMico32 SPI Flash Controller The LatticeMico32 Serial Peripheral Interface (SPI) flash controller is a WISHBONE slave device that provides an industry-standard interface between a LatticeMico32 processor
More informationBlock Diagram. mast_sel. mast_inst. mast_data. mast_val mast_rdy. clk. slv_sel. slv_inst. slv_data. slv_val slv_rdy. rfifo_depth_log2.
Key Design Features Block Diagram Synthesizable, technology independent IP Core for FPGA, ASIC and SoC reset Supplied as human readable VHDL (or Verilog) source code mast_sel SPI serial-bus compliant Supports
More informationSerial Peripheral Interface Bus SPI
Serial Peripheral Interface Bus SPI SPI Bus Developed by Motorola in the mid 1980 s Full-duplex, master-slave serial bus suited to data streaming applications for embedded systems Existing peripheral busses
More information11 ASYNCHRONOUS SERIAL PORTS
11 ASYNCHRONOUS SERIAL PORTS 11.1 General The ETRAX 100LX contains four complete asynchronous serial receivers/ transmitters with full buffering and parity control. Each asynchronous serial port has one
More informationFreescale Semiconductor, I. Product Brief Integrated Multiprotocol Processor with Ethernet
Order this document by MC68EN302/D MC68EN302 Product Brief Integrated Multiprotocol Processor with Ethernet Freescale introduces a version of the well-known MC68302 Integrated Multiprotocol Processor (IMP)
More informationAMC data sheet. PMC Module with four CAN bus Nodes ARINC825 compliant for Testing & Simulation of Avionic CAN bus Systems
AIM-USA PMC Module with four bus Nodes ARINC825 compliant for Testing & Simulation of Avionic bus Systems www.aim-online.com Avionics Databus Solutions data sheet product guide www.aim-online.com and IRIG-B
More informationRL78 Serial interfaces
RL78 Serial interfaces Renesas Electronics 00000-A Introduction Purpose This course provides an introduction to the RL78 serial interface architecture. In detail the different serial interfaces and their
More informationSATA PHY Design Manual
SATA PHY Design Manual BeanDigital (v1.0) 1 July 2012 Revision History Date Version Revision 11/07/12 1.0 Initial release Page 2 1 Contents 2 Introduction... 4 3 Block Diagram... 4 4 Interface... 5 5 Parameters...
More informationAMC data sheet. PMC Module with four CAN bus Nodes ARINC825 compliant for Testing & Simulation of Avionic CAN bus Systems
data sheet PMC Module with four bus Nodes ARINC825 compliant for Testing & Simulation of Avionic bus Systems Avionics Databus Solutions product guide General Features The PCI Mezzanine Card (PMC) can work
More informationSD Mode SD Memory Card Driver Firmware Integration Technology
APPLICATION NOTE RX Family R01AN4233EJ0202 Rev.2.02 Introduction This application note describes the SD Mode SD Memory Card driver which uses Firmware Integration Technology (FIT). This driver controls
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP -UHD General Description The Digital Blocks -UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect
More informationAutomatic Firmware Update Wizard
Automatic Firmware Update Wizard Frozen Content Modified by on 13-Sep-2017 Main article: NanoBoard 3000 - Firmware Updates The Automatic Firmware Update wizard. The Automatic Firmware Update wizard is used
More informationEmbedded Design without an OS. By Peter de Ruiter D&E September 21 st, Transfer BV
Embedded Design without an OS By Peter de Ruiter D&E September 21 st, 2010 Transfer BV Since 1988, Transfer is well known in the BeNeLux for Electronic Design Automation (EDA) training, electronic design
More informationSingle Channel HDLC Core V1.3. LogiCORE Facts. Features. General Description. Applications
Sept 8, 2000 Product Specification R Powered by Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: logicore@xilinx.com URL: www.xilinx.com/ipcenter Support:
More informationClock Synchronous Control Module for Serial Flash Memory Access Firmware Integration Technology
APPLICATION NOTE RX Family R01AN2662EJ0234 Rev.2.34 Introduction This application note explains how to control and use serial flash memory with microcontrollers manufactured by Renesas Electronics. Refer
More informationVideo over SPI. (VoSPI) Implementaion Specification. Document Number: 102-PS Date: 22 Jan Weilming Sieh, FLIR. Paul Fagerburg, Syncroness
Video over SPI (VoSPI) Implementaion Specification Document Number: 102-PS245-43 Date: 22 Jan 2013 Weilming Sieh, FLIR Paul Fagerburg, Syncroness Reviewed by: FLIR SYSTEMS PROPRIETARY COMPANY ONLY This
More informationProduct Technical Brief S3C2413 Rev 2.2, Apr. 2006
Product Technical Brief Rev 2.2, Apr. 2006 Overview SAMSUNG's is a Derivative product of S3C2410A. is designed to provide hand-held devices and general applications with cost-effective, low-power, and
More informationSimplify System Complexity
1 2 Simplify System Complexity With the new high-performance CompactRIO controller Arun Veeramani Senior Program Manager National Instruments NI CompactRIO The Worlds Only Software Designed Controller
More informationWhat's "vspi"? What's included?
What's "vspi"? vspi is a Verilog implementation of an SPI slave. Think of it as a very fast serial port. It can reliably transfer data at 27.9 mbps on an Atlys FPGA devkit (a Spartan-6 with a 100 MHz system
More informationMMC and SD Media Driver for Atmel SAM User Guide
MMC and SD Media Driver for Atmel SAM User Guide Version 1.60 For use with MMC and SD Media Driver for Atmel SAM versions 2.03 and above Date: 18-Aug-2017 15:15 All rights reserved. This document and the
More information