EE414 Embedded Systems Ch 2. Custom Single- Purpose Processors: Hardware

Transcription

1 EE44 Embedded Systems Ch 2. Custom Single- Purpose Processors: Hardware Byung Kook Kim School of Electrical Engineering Korea Advanced Institute of Science and Technology

2 Outline 2. Introduction Review Digital Logic 2.2 Combinational logic 2.3 Sequential logic Custom Single-Purpose Processor 2.4 Custom single-purpose processor design 2.5 RT-level custom single-purpose processor design 2.6 Optimizing custom single-purpose processors Embedded Systems, KAIST 2

3 2. Introduction Processor Digital circuit that performs computation tasks Controller and datapath General-purpose: variety of computation tasks Single-purpose: one particular computation task Custom single-purpose processor: non-standard task Custom single-purpose processor Faster, smaller, low power But, high NRE cost, longer time-tomarket, less fleible. CCD preprocessor Microcontroller Piel coprocessor Embedded Systems, KAIST 3 lens CCD Digital camera chip A2D JPEG codec DMA controller Display ctrl D2A Multiplier/Accum Memory controller ISA bus interface UART LCD ctrl

4 2.2 Combinational Logic Transistors and Logic Gates Transistor The basic electrical component in digital systems. Acts as an on/off switch (not as an amplifier). Voltage at gate controls whether current flows from source to drain Don t confuse this gate with a logic gate gate source drain Conducts if gate= IC package IC source gate oide channel drain Silicon substrate Embedded Systems, KAIST 4

5 CMOS transistor Logic gate implementations CMOS: Complementary Metal Oide Semiconductor Most widely used. Transistor < Logic gates < Digital systems. We refer to logic levels Typically is V, is 5V Two basic CMOS TR types nmos conducts if gate= pmos conducts if gate= Hence complementary Basic logic gates Inverter, NAND, NOR gate source Conducts gate source Conducts if gate= if gate= drain drain nmos pmos y F = ' F = (y)' y F = (+y)' y y inverter NAND gate NOR gate Embedded Systems, KAIST 5

6 Basic Logic Gates F = Driver F F y F = y AND F y F y F = + y OR F y F y F = y XOR F y F F = Inverter F F y F = ( y) NAND F y F y F = (+y) NOR F y F y F = y XNOR F y F Digital system designers usually work at the abstraction level of logic gates rather than transistors. Transistor < Logic gates < Digital systems. Embedded Systems, KAIST 6

7 Basic Combinational Logic Design Combinational circuit: Output purely function of present input (No memory) A) Problem description y is if a is to, or b and c are. z is if b or c is to, but not both, or if all are. D) Minimized output equations y bc a z bc a y = a + bc z = ab + b c + bc B) Truth table Inputs Outputs a b c y z Karnaugh maps: Maimize squares enclosing s. C) Output equations y = a'bc + ab'c' + ab'c + abc' + abc z = a'b'c + a'bc' + ab'c + abc' + abc E) Logic Gates Embedded Systems, KAIST 7 a b c y z

8 RT-level combinational components Multipleer, Decoder, Adder, Comparator, and ALU I(m-) I I n S n-bit, m Multipleor S(log m) n I I(log n -) log n n Decoder A B n n-bit Adder n n A n B n-bit Comparator n A n B n bit, m function S ALU n S(log m) O O(n-) O O carry sum less equal greater O O = I if S=.. I if S=.. I(m-) if S=.. O = if I=.. O = if I=.. O(n-) = if I=.. sum = A+B (first n bits) carry = (n+) th bit of A+B less = if A<B equal = if A=B greater= if A>B O = A op B op determined by S. With enable input e all O s are if e= With carry-in input Ci sum = A + B + Ci May have status outputs carry, zero, etc. Embedded Systems, KAIST 8

9 2.3 Sequential Logic Sequential circuit Flip-Flops A digital circuit whose outputs are function of the present as well as previous input values Sequential logic possesses memory: Combinational logic and memory. E. Coffee vending machine Flip-flop Basic memory in sequential circuit D flip-flop SR flip-flop JK flip-flop Level triggered Edge triggered Embedded Systems, KAIST 9

10 RT-level sequential components Register, shift register, and counter I load clear n n-bit Register n shift I n-bit Shift register Q n-bit Counter n Q Q Q = if clear=, I if load= and clock=, Q(previous) otherwise. Q = lsb - Content shifted - I stored in msb Q = if clear=, Q(prev)+ if count= and clock=. Synchronous: Input value has an affect during clock edge. Asynchronous: Input value affects the circuit independent of clock. Embedded Systems, KAIST

11 Sequential Logic Design A) Problem Description You want to construct a clock divider. Slow down your preeisting clock so that you output a for every four clock cycles B) State Diagram C) Implementation Model a Combinational logic I I Q Q State register I I D) State Table (Mooretype) Inputs Outputs Q Q a I I a= = = a= 3 a= a= a= State diagram a= a= 2 = = a= Finite State Machine (FSM) Given this implementation model Sequential logic design quickly reduces to combinational logic design. Embedded Systems, KAIST

12 Sequential logic design (cont.) I QQ a E) Minimized Output Equations F) Combinational Logic I = Q Qa + Qa + QQ a I QQ a I = Qa + Q a I a QQ = QQ I Q Q Embedded Systems, KAIST 2

13 2.4 Custom Single-Purpose Processor Design A basic processor model Controller: Control datapath. Datapath: Manipulate and store. Inside view eternal control inputs controller datapath control inputs eternal data inputs datapath controller net-state and control logic datapath registers eternal control outputs datapath control outputs eternal data outputs state register functional units Controller and datapath A view inside the controller and datapath Embedded Systems, KAIST 3

14 Design eample: Greatest Common Divisor. First create algorithm (a) black-bo view :!!(!go_i) (c) state diagram Subtraction (b) go_i _i y_i 2:!go_i 2. Convert algorithm to comple state machine (c) Known as FSMD: finite-state machine with data Can use templates to perform such conversion GCD d_o (b) desired functionality : int, y; : while () { 2: while (!go_i); 3: = _i; 4: y = y_i; 5: while (!= y) { 6: if ( < y) 7: y = y - ; else 8: = - y; } 9: d_o = ; } 7: 2-J: 3: = _i 4: y = y_i 5:!(!=y)!=y 6: <y!(<y) y = y - 8: = - y 6-J: 5-J: 9: d_o = -J: Embedded Systems, KAIST 4

15 2. State diagram templates Assignment statement a = b net statement Templates (a) Assignment (b) Loop (c) Branch Loop statement while (cond) { loop-bodystatements } net statement Branch statement if (c) c stmts else if c2 c2 stmts else other stmts net statement a = b C: cond!cond C: c!c*c2!c*!c2 net statement loop-bodystatements c stmts c2 stmts others J: J: net statement net statement Embedded Systems, KAIST 5

16 3. Creating the datapath. Create a register & ports for any declared variable 2. Create a functional unit for each arithmetic operation 3. Connect the ports, registers and functional units Based on reads and writes Use multipleers for multiple sources 4. Create unique identifier for each datapath component control input and output _i y_i _sel n-bit 2 n-bit 2 y_sel _ld : : y y_ld!= < subtractor 5:!=y 6: <y 8: -y _neq_y _lt_y d_ld Datapath subtractor 7: y- 9: d d_o Embedded Systems, KAIST 6

17 4. Creating the controller s FSM Controller implementation model Q3 I3 Combinational logic Q2 Q State register I2 go_i Q I I _sel y_sel _ld y_ld _neq_y _lt_y d_ld Controller : 2: 2-J: 5: 6: _neq_y!_neq_y _lt_y!_lt_y 7: y_sel = 8: _sel = y_ld = _ld = 5-J: 9: 3: 4: -J:!go_i _sel = _ld = y_sel = y_ld = d_ld =!!(!go_i) 6-J: go_i Same structure as FSMD Replace comple actions/conditions with datapath identifiers _sel y_sel _ld y_ld _i n-bit 2 5:!=y 6: <y _neq_y _lt_y d_ld!= y_i n-bit 2 : : y < subtractor 8: -y Datapath subtractor 7: y- 9: d d_o Embedded Systems, KAIST 7

18 5. Controller state table for the GCD eample Inputs Q3 Q2 Q Q _neq _y Outputs _lt_y go_i I3 I2 I I _sel y_sel _ld y_ld d_ld * * * X X * * X X * * X X * * * X X * * * X * * * X * * X X * * X X * * X X * * X X * * * X * * * X * * * X X * * * X X * * * X X * * * X X * * * X X * * * X X * * * X X Embedded Systems, KAIST 8

19 6. Completing the GCD custom single-purpose processor design We finished the datapath We have a state table for the net state and control logic All that s left is combinational logic design controller net-state and control logic datapath registers This is not an optimized design, but we see the basic steps state register functional units a view inside the controller and datapath Embedded Systems, KAIST 9

20 2.5 RT-level Custom Single- Purpose Processor Design We often start with a state machine, rather than program. Especially when eplicit cycle timing is important. Eample Bus bridge that converts 4-bit bus to 8-bit bus Start with FSMD Known as register-transfer (RT) level Eercise: complete the design Problem Specification Sende r FSMD rdy_in clock data_in(4) rdy_in= WaitFirst4 rdy_in= WaitSecond4 Send8Start data_out=data_hi & data_lo rdy_out= Bridge A single-purpose processor that converts two 4-bit inputs, arriving one at a time over data_in along with a rdy_in pulse, into one 8-bit output on data_out along with a rdy_out pulse. rdy_in= Bridge RecFirst4Start data_lo=data_in rdy_in= rdy_in= RecSecond4Start data_hi=data_in rdy_in= Send8End rdy_out= rdy_out data_out(8) rdy_in= RecFirst4End rdy_in= RecSecond4End Rece iver Inputs rdy_in: bit; data_in: bit[4]; Outputs rdy_out: bit; data_out:bit[8] Variables data_lo, data_hi: bit[4]; Embedded Systems, KAIST 2

21 RT-level custom single-purpose processor design (cont ) (a) Controller rdy_in= WaitFirst4 rdy_in= WaitSecond4 rdy_in= Bridge RecFirst4Start data_lo_ld= rdy_in= rdy_in= RecSecond4Start data_hi_ld= rdy_in= RecFirst4End rdy_in= RecSecond4End Send8Start data_out_ld= rdy_out= Send8End rdy_out= rdy_in clk data_in(4) rdy_out data_out to all registers (b) Datapath data_out_ld data_hi_ld data_hi data_out data_lo data_lo_ld Embedded Systems, KAIST 2

22 2.6 Optimizing Custom Single- Purpose Processors Optimization is the task of making design metric values the best possible. Optimization opportunities A. Original program / algorithm B. FSMD C. Datapath D. FSM Embedded Systems, KAIST 22

23 A. Optimizing the original program Analyze program attributes and look for areas of possible improvement Time and space compleity Number of computations Size of variable Operations used Multiplication and division are very epensive. Embedded Systems, KAIST 23

24 Optimizing the original program: Using Modulo operation Original program : int, y; : while () { 2: while (!go_i); 3: = _i; 4: y = y_i; 5: while (!= y) { 6: if ( < y) 7: y = y - ; else 8: = - y; } 9: d_o = ; } replace the subtraction operation(s) with modulo operation in order to speed up program GCD(42, 8) - 9 iterations to complete the loop and y values evaluated as follows : (42, 8), (43, 8), (26,8), (8,8), (, 8), (2,8), (2,6), (2,4), (2,2). Optimized program : int, y, r; : while () { 2: while (!go_i); // must be the larger number 3: if (_i >= y_i) { 4: =_i; 5: y=y_i; } 6: else { 7: =y_i; 8: y=_i; } 9: while (y!= ) { : r = % y; : = y; 2: y = r; } 3: d_o = ; } GCD(42,8) - 3 iterations to complete the loop and y values evaluated as follows: (42, 8), (8,2), (2,) Embedded Systems, KAIST 24

25 B. Optimizing the FSMD Areas of possible improvements Scheduling Task of assigning operations from the original program to states in an FSMD. Merge states States with constants on transitions can be eliminated: Transition taken is already known States with independent operations can be merged Separate states States which require comple operations (a*b*c*d) can be broken into smaller states to reduce hardware size Embedded Systems, KAIST 25

26 Optimizing the FSMD (cont.) : 2: 2-J: 3: int, y;!!(!go_i)!go_i = _i Original FSMD eliminate state transitions have constant values merge state 2 and state 2J no loop operation in between them Optimized FSMD 2: 3: 5: int, y; go_i = _i y = y_i!go_i 4: 5: y = y_i!(!=y) merge state 3 and state 4 assignment operations are independent of one another <y >y 7: y = y - 8: = - y 7: 6: y = y - 6-J: 5-J:!=y <y!(<y) 8: = - y merge state 5 and state 6 transitions from state 6 can be done in state 5 eliminate state 5J and 6J transitions from each state can be done from state 7 and state 8, respectively 9: d_o = -J: 9: d_o = eliminate state -J transition from state -J can be done directly from state 9 Embedded Systems, KAIST 26

27 C. Optimizing the datapath Sharing of functional units One-to-one mapping, as done previously, is not necessary If same operation occurs in different states, they can share a single functional unit Multi-functional units ALUs support a variety of operations, it can be shared among operations occurring in different states Allocation: Choose RT components to use Bind: Map operations from FSMD to components. Embedded Systems, KAIST 27

28 D. Optimizing the FSM State encoding Task of assigning a unique bit pattern to each state in an FSM Size of state register and combinational logic vary Can be treated as an ordering problem State minimization Task of merging equivalent states into a single state State equivalent if for all possible input combinations the two states generate the same outputs and transitions to the net same state Embedded Systems, KAIST 28

29 Summary Custom single-purpose processors For non-standard tasks Optimized Design Straightforward design techniques Can be built to eecute algorithms Typically start with FSMD CAD tools can be of great assistance. Embedded Systems, KAIST 29

30 References [] Frank Vahid, Embedded system design: A unified hardware/software introduction, John Wiley & Sons, 22. Embedded Systems, KAIST 3