Spring 2013 EE201L Instructor: Gandhi Puvvada. Time: 7:30-10:20AM SGM124 Total points: Perfect score: Open-Book Open-Notes Exam

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1 Spring 2013 EE201L Instructor: Gandhi Puvvada Final Exam 2 (25%) Date: May 9, 2013, Thursday Name: Open-Book Open-Notes Exam Time: 7:30-10:20AM SGM124 Total points: Perfect score: 1 ( points) min. Memory width and depth expansion: Build an 8Kx8 ROM memory (with an overall CS chip-select) using the 7 smaller ROM chips as shown in the map on the side. The 8Kx8 ROM has address pins and data pins. Complete the design below. Add missing labels, wires, and gates. 2 to 4 decoder A0 A1 G Y0 Y1 Y2 Y3 1Kx8 ROM A9-A0 #7 CE 1Kx8 ROM A9-A0 CE #6 1Kx8 ROM A9-A0 #5 CE 1Kx8 ROM A9-A0 #4 CE O7-O0 O7-O0 O7-O0 O7-O0 #7 #6 #5 #4 4Kx4 1Kx8 1Kx8 1Kx8 1Kx8 #2 4Kx2 4Kx2 #1 #0 4Kx4 ROM A11-A0 4Kx2 ROM 4Kx2 ROM A11-A0 #2 #1 #0 CS O3-O0 CS O1-O0 1.1 A ROM can not be used as a RAM (=RWM) because you can t (read from / write to) it. (However / Also) a RAM (=RWM) (Can t / can) be used as a ROM because May 9, :06 am EE201L Final - Spring / 7

2 2 ( points) min. State Machine design: Given an array of 25 8-bit unsigned numbers (M[0] to M[24]) find how many non-zero numbers are divisible by 40. Since 40 can be factorized as 8 * 5 and since divisibility by 8 can easily be checked by looking at the three least significant bits, only numbers divisible by 8 are further inspected for divisibility by 5 using the "division by repetitive subtraction" method. "I" is an index into M[I] and "J" is the number of divisible-by-40 numbers. Both "I" and "J" are initialized to zero in the INI state. In the LOAD state the upper 5 bits M[I][7:3] are loaded into A and the lower 3 bits M[I][2:0] are inspected. Like in other problems, here also we have DONE_F (for done found) and DONE_NF (for done not found meaning no number is divisible by 40). Reset Start INI I <= 0; J <= 0 Start LOAD A <= {3 b000, M[I][7:3]; if (M[I][2:0]!= 3 b000) DIV DONE_F DONE_NF Considering only the clocks spent in LOAD and DIV states what is the least number of clocks taken for what kind of array which ends up drawing DONE_F inference? May 9, :06 am EE201L Final - Spring / 7

3 3 ( points) min. Merge sort lab: RESET_N START INITIAL 0 START Clear Counters I, J, K 1 CMP P < Q? P_LT_Q 2 SP R(K) P(I) I I + 1 P_LT_Q 5 SQ R(K) Q(J) J J RQ R(K) Q(J) J J RP R(K) P(I) I I + 1 DUMMY DONE Done = (unconditional) In the above design, P and Q are 4-element arrays and R is an 8-element array. Assuming that the I, J, and K counters are adequately big, does your design assume or require that the P and Q be of equal size? Yes / No 3.2 You have designed and implement the above lab as positive-edge-triggered system. If you need to change it negative-edge-triggered system, what is the minimal changes you need to make. You were told not to meddle with the clock, so do not put inverters in the clock path. You need to change components if required from the positive-edge trigger red to negative edge triggered. 3.3 The condition select mux in your schematic is shown on the side. Your VLSI engineer can make custom components, for example a 7-to-1 mux instead of the standard 8-to-1 mux. What is your bare necessity and how? START_N P_LT_Q_N _N _N VDD _N GND GND I2 I3 Y I4 I5 I6 I7 S0 S1 S2 CS0 CS1 CS2 3.4 Your VLSI engineer asks you if he can change the order of connections to I[7:0] and also to CS[2:0]. This gives him some layout convenience. Will you be able to accommodate him and fix it in programming of the microprogram memory? 3.5 Your VLSI engineer by mistake designed an inverting mux. Can you fix it n programming of the microprogram memory? Yes / No May 9, :06 am EE201L Final - Spring / 7

4 3.6 Your boss (who boasts himself as forward-thinking), without telling you, increased the microprogram counter to a 4-bit counter from a 3-bit counter and also doubled the depth and width of the microprogram memory. He says this is good for future changes. The 4-bit output of the microprogram counter is connected as the 4-bit address input of the microprogram memory. Any problem? Major (requiring the VLSI engineer s work to redone) or minor (that you can fix) 3.7 In your current design, you have a 4-bit comparison unit as shown on the P A side. Mr. Bruin saved an inverter by labeling upper output pin as P_LT_Q_N A>B Q B and he says his design worked! Please comment. A<B PL_Q P_LT_QN 3.8 In merge-sort you merge two sorted array into a larger sorted array. Either all three array are in ascending order or in descending order. In our lab, the three arrays P, Q, and R are all in ascending order. How can you tell from the state diagram below. 3.9 After you finished the above design, suppose we tell you that all three arrays are in descending order. Change the above state diagram and narrate below consequential changes. Any change to the size of the components in your design? Microprogram Counter: Yes / No Microprogram memory: Yes / No Condition select multiplexor: Yes / No Any changes to the input connections to the inputs of the above three? Yes / No Any changes to the content of the Microprogram memory? Yes / No Explain all your "Yes"s 3.10 Redesign the above state machine as a mealy machine for one-hot implementation. The clock is wide enough so that you can compare and make a conditional load into R array. START RESET_N INITIAL Clear Counters I, J, K START If (P < Q) begin end else begin end CMP_N_STORE RQ R(K) Q(J) J J + 1 RP R(K) P(I) I I + 1 DONE Done = 1 May 9, :06 am EE201L Final - Spring / 7

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7 4 ( points) min. Epp: On the Nexys-3 board, who is the Epp Master and who is the Epp Slave? Who activates the data strobe DSTB? (Master / Slave). And who responds with WAIT? (Master / Slave). Response means activating or inactivating WAIT? (activating / inactivating). If DSTB? is 0 for a long time with WAIT? showing a value of 1, do you suspect that the master is faulty or the slave? Why? (Mr. Bruin / Mr. Trojan) looks at WRITE alone and if it is a 0, he concludes that a write transaction is in progress and if it is a 1 a read transaction is in progress. Please comment. EppAstb Nexys-3 Board Cypress USB interface chip Spartan 6 FPGA Epp Master 8 EppDstb EppWr EppDB EppWait Epp Slave = GOT Synchronization of asynchronous inputs: If System 1 provides 32-bit DATA1 and says take with T1 (T1 = 1) and System 2 provides another 32-bit DATA2 and says take with T2 (T2 = 1). Then System 3 adds both of them and returns 32-bit SUM and says done (DONE =1). The three systems are working at different frequencies. Our (cheap) company uses only single synchronization. You add synchronization Flip-Flops to make the system work. Mark D and Q and show clock connections also. Do you provide synchronization flip-flops on 32-bit DATA lines or 1-bit control lines or both? Explain your design: System #1 System #2 Take Data Got Sum CLK1 Take Data Got Sum CLK2 T1 DATA1 T2 DATA2 T DATA1 DATA2 Take Data1 Data2 Done Sum CLK3 Adder Reg A B AB System #3 May 9, :06 am EE201L Final - Spring / 7

8 5 ( points) min. FIFOs 5.1 A change in (depth / width) of the FIFO will not cause a change in the pinout of the FIFO because 5.2 If WP = 4 and RP =2, the depth is if the FIFO is a 16-location FIFO, and is if the FIFO is a 64-location FIFO. If WP = 2 and RP =4, the depth is if the FIFO is a 16-location FIFO, and is if the FIFO is a 64-location FIFO. 5.3 Consider an 8-location 2-clock FIFO using 4-bit counters (in place of 3-bit counters) for the WP and RP pointers. If the producer is much faster, then the FIFO will be running FULL most of the time. So WP may be 1000 (=8) and RP may be 0000 (=0) for quite some time and then finally the consumer consumes one item and in no time, the producer replenishes (fills the fifo). Then the WP will be 1001 (=9) and RP will be 0001 (=1) for some time. However sometimes the producer may be busy and it is possible that WP is 1110 (=14) and RP is 1101 (=13). It is (possible / not possible) to have WP = 0001 (=1) and RP = 1111 (=15). It is (possible / not possible) to have WP = 1111 (=15) and RP = 0001 (=1). For each of the above 2, if you said "possible", state the depth and if you said "not possible" state your reason. Also state whether you do MOD_8 or MOD_16 subtraction here. 5.4 Never ever synchronize by sampling and holding (circle all applicable): (a) a multi-bit data item where multiple bits could be changing simultaneously (b) a single-bit data item (c) a multi-bit data item where multiple bits wouldn t be changing simultaneously (d) none of the above 5.5 It is (necessary/not necessary) that the WP and RP are initialized to zero-zero only and nothing else. It (is / isn t) fine if they are both initialized to say one-one. 5.6 Deadlock can be created if the FIFOs are (shallow / deep) and if the frequencies of the producer and consumer are (nearly the same / orders of magnitude different) and used [n-bit pointers for 2 n -location FIFO / (n+1)-bit pointers for 2 n -location FIFO]. Deadlock will never occur irrespective of how deep is the FIFO, how different are the frequencies if we use [n-bit / (n+1)-bit] pointers for a 2 n -location FIFO. 5.7 Gray code counters are wasteful but not harmful in (singleclock / two-clock / both / neither) FIFO. The 16-bit Gray code 1010_1010_0000_1111 represents an (odd / even) decimal number. The 16-bit Binary code 1010_1010_0000_1111 represents an (odd / even) decimal number. May 9, :06 am EE201L Final - Spring / 7

9 6 ( points) min. Timing design and the Shannon s Expansion Theorem: Essential parts of the solution to Q#1 of Spring 2012 is reproduced below. Suggest a set of delays for the U/D and EN (let us call it Set E) such that the Circuit #3 is the only viable option. Arrive at setup time and hold time margins. Item incrementer/decrementer incrementer decrementer 2-to-1 mux register without date-enable Cost (area) Max Delay (ns) min Delay (ns) register set-up time tsu (min) = 0.8ns register hold time th (min) = 0.3ns Cheapest Circuit U/D EN for 10ns clock Arrival delay times Set A Arrival delay times Set B Arrival delay times Set C Arrival delay times Set D 0 ns 7 ns 0 ns Circuit # 2 Circuit # 1 Circuit # 2 Circuit # 2 Arrival delay times Set E Circuit # 3 Circuit #1 Circuit #2 Circuit #3 AREA For the Cheapest Circuit Set-up time margin margin Hold time 1.7 ns 0.2 ns 0.7 ns 0.2 ns 1.7 ns 0.2 ns 0.2 ns 0.2 ns Set E Circuit # 3 Set E Circuit # 3 Set-up time margin calculations Hold time margin calculations Incrementer/ Decrementor I_next Register I Incrementer Decrementer I+1 I-1 U/D EN CLK U/D ENCLK U/D EN Circuit #1 Circuit #2 Circuit #3 Register I Incrementer Decrementer I+1 I-1 EN CLK Register I 7 ( points) min. Barrel shifter In class, we discussed the following: A 4-input 4-output barrel shifter (which can be built from 4 of 4-to-1 muxes) does not need 4 * 3 = 12 2-to-1 muxes but can be built using 8 2-to-1 muxes (4 in each of the two columns governed by S1 and S0). Make a similar statement by completing the sentence below. A 16-input 16-output barrel shifter (which can be built from of -to-1 muxes) does not need 2-to-1 muxes but can be built using 2-to-1 muxes ( in each of the columns governed by ). The TAs, the graders and I have enjoyed teaching this course and we hope you too liked this course. Hope to see all of you in EE457 and some of you in EE454L in an year :) May 9, :06 am EE201L Final - Spring / 7