MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS

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1 MASSEY UNIVERSITY PALMERSTON NORTH CAMPUS EXAMINATION FOR COMPUTER SYSTEMS Semester I Time allowed: THREE (3) hours THIS IS A CLOSED BOOK EXAMINATION ANSWER ALL QUESTIONS SECTION A 28 Multi-choice Questions each worth 1 mark 28 marks Record your answers to the questions in Section A on the Mark Sense Card provided. SECTION B Three Questions each worth 24 marks 72 marks Write your answers to the questions in Section B in the blue answer booklet provided Total: 100 marks Marks for each question are shown in brackets after the question, like this [8 marks] Note that in some of the questions in this exam, the abbreviations hi and lo may have been used to signify logic high (5V for TTL, 12V for CMOS) and logic low (0V for TTL and CMOS) signals respectively. Page 1 of 19

2 SECTION A 1 If a weather system has sensors that report whether or not it s cloudy, whether or not it s too cold for outdoor sport, and whether the wind speed exceeds 20 kilometres per hour or not, then how many rows would there be in a Truth table that listed all types of weather that the system can distinguish? (A) 3 (B) 8 (= 2 x 2 x 2) (C) 80 (= 2 x 2 x 20) (D) Don t be silly. You can t possibly list all weather types in a single table of finite size. 2 The diagram below shows the start of a circuit diagram. In the diagrammatic conventions we ve used in this paper, what type of diagram would this image belong to, and what are the benefits of starting the diagram this way? A B C (A) It s the first stage of a random access memory device. The labels A, B, and C represent the control signals for Accessing, Bounce-suppression and Chip-select. The benefits are that Bounce-suppression does not have to be handled as a separate entity, and the Accessing signal amalgamates Read-enable and Write enable as a single signal that enables reading when the signal is TRUE and writing when it is FALSE. (B) It s the first stage of a combinatorial circuit. The benefits are that AND gates in the rest of the diagram can access any input (or its inverse), and because of the regular layout of the input signals, it s very easy to read the Boolean expression that the diagram corresponds to. (C) It s the first stage of a combinatorial circuit. The benefits are that the highly regular nature of the set of signals (i.e., fact that the signals A, B, and C are in ascending sequence) makes it easy to relate the semantic content of the diagram to the significance of the signals in the outside world. (D) It s the first stage of a counter. The benefits are that these signals which are control signals - are separate from the data signals that the counter will process. Furthermore, the amplifiers (the triangles on the right hand wires) increase the voltage so that the inputs to be sent to a large number of stages, and thus the counter can have many bits. Page 2 of 19

3 3 Does a demultiplexor invert its output? (A) Yes, always. (B) Yes, but only under exceptional circumstances. (C) Yes, often. (D) No, never. 4 In analysing the behaviour of an RS flip flop, we normally make an assumption. What is that assumption, and why do we make it? (A) We need to assume that the device is currently in memory mode, because otherwise its initial output can t be guaranteed. (B) We need to assume the value of one of the outputs, because the circuit involves feedback, and thus one of its inputs can t be externally set. (C) We need to assume that R and S are different from each other (one high and the other low). This prevents the device from malfunctioning (blowing up). (D) We need to assume that the clock speed is higher than the data-set time (the time for the output to settle to a stable value after the input has changed) for the circuit. This gives the external circuitry time to react when a new value is loaded into the flip-flop 5 In a random access memory (A) the size of the words must be smaller than the size of the addresses. (B) tri-state circuitry must not be used to connect the output to the data line, because the data line has only two values, in and out. (C) the word random means that words can be accessed in any order. (D) the incoming data value is fed into a decoder, and the output from the decoder is used to select a particular word in memory. 6 A ripple counter (A) is frequently used in wave mechanics calculations. (B) involves much simpler flipflops (i.e. D flipflops) than a synchronous counter (which uses JK flipflops). (C) can cause problems when it is important that spurious (false) intermediate values are not generated in the transition between two valid numbers. (D) should be clocked in several stages, so that the ripple effect can catch up between the flipflops. 7 In an ASM (A) diamonds (or hexagons) contain unconditional outputs. (B) diamonds (or hexagons) represent conditional outputs. (C) diamonds (or hexagons) denote clock transitions. (D) diamonds (or hexagons) contain conditional tests. Page 3 of 19

4 8 In an ASM (A) the first state should always be 0. (B) a state should never cycle immediately back to itself; there should always be an intervening state, even if the outputs are the same. (C) a reset-on-powerup circuit can be used to ensure that the ASM starts in state 0. (D) the first state should always be a wait state, where the circuit is waiting for some condition to be fulfilled before embarking on the rest of the cycle of states. 9 A decoder (A) transfers an input value on one of 2 n inputs to a single output line. The input is chosen on the basis of the value on an n-bit control input. (B) is an essential part of a shift register, as it determines which of the flipflops will receive the incoming data. (C) should only produce one TRUE output at a time. (D) can be replaced by a multiplexor, if the control and data inputs are reversed. 10 Multiplexors are used in ASMs (A) because their internal design is generally simpler than the combinatorial circuitry that they replace. (B) because they re cheaper than nearly all other types of digital circuit. (c) because they turn output generation from a calculation to a lookup, which is easy to understand and easy to modify. (d) only when all other alternatives have been exhausted. 11 Shift registers (A) have to alternate between shift left operations and shift right operations. (B) should only be constructed with falling-edge triggered flip flops. (C) are gradually being phased out in sensitive applications (such as encryption hardware). (D) shift information in one direction at a time. 12 A single data input connected to a set of independently loadable flipflops would be called (A) a tri-state input. (B) a conductor. (C) a control input. (D) a bus. Page 4 of 19

5 13 A computer processor (A) cannot be programmed to overwrite its own program. (B) is used in recycling stations to separate the parts of old PCs into different groups, according to how they can be reused. (C) uses the same representation for program and for data that a program uses and generates. (D) is the device that implements the instruction set for a computer, and sends commands to the architecture to perform the tasks associated with each instruction. 14 A computer instruction (A) is represented within the computer by an English word that is interpreted during a series of clock cycles. (B) is represented within the computer by a series of English-like words that form a sentence. (C) is the same thing as an address. (D) is represented within the computer by a binary code that is interpreted during a series of clock cycles. 15 After the following sequence of 8051 instructions has executed data equ $50 start mov $50,#1 mov $51,#'A' mov $52,#2 mov $53,#'B' mov r1,#data inc r1 mov r0,data mov a,r1 add a,r0 inc a mov r0,a mov a,@r0 ; Set up Data Memory ; Test Code which value will be left in the accumulator? (A) 1 (B) 'A' (C) 2 (D) 'B' Page 5 of 19

6 16 Interrupts are used to (A) simplify programming and allow multiple activities to (apparently) run concurrently. (B) replace subroutines when the Global Interrupt Enable (EA) bit is a 0. (C) handle arithmetic on multibyte values. (D) simplify programming by delegating all complex tasks to the ALU. 17 Which of the following is NOT correct? The stack in the 8051 microcontroller is important because (A) it provides a way to reuse the same memory to hold temporary data. (B) it provides a place to save subroutine return addresses. (C) using the stack, recursive subroutines can call themselves at least 128 times. (D) it provides a method of passing parameters to subroutines. 18 An embedded microcontroller system is (A) a small computer system that doesn't use a program counter, just registers. (B) a system pre-programmed to perform a fixed task. (C) one that does not need any I/O (input/output) (D) one that must run only from batteries. 19 The following 8051 subroutine has one parameter, passed in the accumulator xxx: push again: jnz sjmp doit: clr subb sjmp done: pop ret acc doit done c a,#1 again acc If subroutine xxx is called in the following way mov a,#119 lcall xxx (A) it finds the total of all numbers from 1 to 119. (B) it continuously increments the stack pointer. (C) it subtracts one from the initial parameter, being sure to clear the carry bit first. (D) it provides a variable delay, the length of which is controlled by the parameter. Page 6 of 19

7 20 In the 8051, the carry bit is often cleared before subtraction but not addition. This is because (A) the addition operation only generates a carry-out but does not use a carry-in. (B) the subtraction operation depends on the decrement operation and the carry is used as a flag (like the F bit) to ensure the operation puts the result in the accumulator (as expected). (C) subtraction is a less frequent operation than addition, so to optimise the usage of bits available to encode instructions, the designers chose to make the processor have only one subtract instruction (which always includes the carry bit). For the lowest byte of a multi-byte instruction, the carry bit must be zero to give a correct result. (D) the carry bit is not relevant to subtraction; it is only used by the Add-withcarry (ADDC) instruction. 21 Start and stop bits (A) are used to synchronise a receiver to the start and end of an arriving chunk of data, usually a byte. (B) are the same. (C) can have data values piggybacked onto them. (D) invert from one byte to the next. 22 Frequency modulation (A) uses an analogue wave with two different frequencies to transmit unidirectional binary data and four different frequencies to transmit simultaneous bidirectional binary data. (B) becomes more effective at data rates in excess of 1MB s -1. (C) is only used for FM radio transmissions. (D) is less effective at data rates in excess of 1MB s Hamming codes (A) can be used to correct single bit errors. (B) should be used in situations where it is likely that errors are smeared over a large number of successive bytes. (C) can be used to detect single bit errors and detect 2-bit errors simultaneously (D) should not be used in situations where it is likely that errors are smeared over a large number of successive bytes. 24 The IP protocol (A) is designed to throw away data under certain conditions. (B) has error correction facilities that guarantee that it will deliver correct data. (C) is designed to work over fibre optic links. (D) is designed to run over satellite links. Page 7 of 19

8 25 Class B IP addresses have (A) 128 networks with 16 million hosts. (B) 16K networks with 64K hosts. (C) 2 million networks with 254 hosts. (D) an arbitrary number of hosts, as they are used for multicasting applications. 26 Flooding is not used as a data delivery mechanism in networks because (A) it s a very inefficient use of network bandwidth. (B) it came along too late; it would have been ideal, but other delivery mechanisms were entrenched by the time the benefits were realised. (C) it is not robust in military applications, as the flood can easily be blocked. (D) it simply cannot be used to carry data; only route calculations can be performed this way. 27 In Dijkstra s algorithm (A) there is no way of taking the varying costs of different links into account. (B) the route to a node is calculated by adding the best current candidate to a tree of existing start points. (C) the route to a node is stored in a central database that is updated by uploading the routes along a tree with its root at the node containing the central database. (D) the route between every pair of nodes in a network involves an independent calculation. 28 In a data communications network constructed according to the ISO model (A) intermediate nodes are passive with respect to the binary content of the data packets. Thus they only need to implement the physical layer of the model. (B) intermediate nodes do not have to implement the complete ISO stack. (C) intermediate nodes are unnecessary. (D) intermediate nodes always contain 5 levels of the stack. Page 8 of 19

9 SECTION B (long answers) Answer questions 29 to 31 in the blue answer booklet provided Write the numbers of the questions you have answered from this Section on the front cover of your blue answer booklet DO NOT DO tie the Scantron Mark Sense Card into your blue answer booklet tie the ancillary sheet into your blue answer booklet Page 9 of 19

10 29 (A) Draw a circuit for a four-bit synchronous counter. [6 marks] (B) Design a circuit that inputs a 2-bit number and outputs it successor (if the input is 2, the output is 3, if the input is 3 the output is 0 and so on). [6 marks] (C) A number of devices need to be controlled. Each one has a start input, and should start operating when that input becomes true. The devices start in sequence (i.e. one after the other, on successive clock cycles). Design a control circuit that uses a counter and a decoder can be used to produce the start signals, and stops producing start signals as soon as another signal, stop becomes TRUE. This circuit does not need to be an ASM [6 marks] (D) A separate sheet has been distributed with this exam, showing the ASM diagram for the PicoComputer. Some labels have been omitted from the exit paths of some conditional tests. CLEARLY indicate what the labels should be and the exit paths that they should be attached to. Write your name and ID number on the sheet and tie it into your exam script. [6 marks] 30 (A) Show how the following statements could be translated into 8051 assembler. Literal translations are not required, just code that implements the same functionality. (i) X:= X + Y 17; Note: the variables X and Y are one byte variables. [2 marks] (ii) ch:= getch; i := 0; while ( (ch <> '?') AND (ch <> '.') ) do begin mystring[i] := ch; (* Assume mystring starts at Data Memory location $50 *) i:= i+1; ch:= getch; end; The preceding code fragment builds a string. You may assume that: a subroutine called getch already exists. It loads the accumulator with the next character that the user inputs. mystring is a block of memory starting at location $50 in data memory [4 marks] Page 10 of 19

11 (iii) for i:= 0 to 19 do M[i]:= 0; You may assume that the array M is stored in a block of memory that starts at Internal Data Memory location $50. [2 marks] (B) The 8051 instructions CLR C and SET C affect the carry bit. Illustrate how this bit is used by writing a subroutine to add multi-byte numbers. On entry to the subroutine: - r0 contains the address of the first (the least significant) byte of N1, the first number - r1 contains the address of the first byte of N2, the second number - r7 contains the number of bytes in each number (they're the same) The numbers are stored so that the least significant byte is stored at the specified memory address and any additional bytes are stored in consecutive memory locations in ascending address order. The result of the addition is stored in the same memory as N2 (the subroutine overwrites N2 it implements N2:= N1 + N2). [8 marks] (C) Describe what interrupts are and why they are used. [4 marks] (D) The 8051 status register contains the following bits. CY AC - F0 - RS1 - RS0 OV - F1 - P Describe the purpose of each bit. [4 marks] 31 (A) A sender and receiver are using the Lempel-Ziv compression algorithm. Write down their code tables after (i) one character (ii) two characters (iii) three characters of the message hello had been transmitted, if the initial agreed code was 1 h 2 e 3 l 4 o [6 marks] Page 11 of 19

12 (B) In an IP network, segment A is capable of carrying packets containing 65K bytes, and segment B is capable of carrying packets containing 5Kbytes. Data must traverse segments A and B (in that order) to go from source to destination. How does the IP protocol allow for this? In your answer, remember that the IP protocol does not guarantee to deliver packets in the correct order. [6 marks] (C) In the OSI model, there are various acronyms and jargon terms. Define the terms PDU, SAP, and peer-to-peer communication. The definitions of the terms should include, but not be restricted to, an expansion of the acronyms. Note that it could make sense to combine two of the definitions. [6 marks] (D) Draw a diagram showing how sections, lines and paths relate to the topology of a SONET network, and show, with a sketch, how the line overhead, section overhead and data are organised in a SONET frame. There s something odd about this arrangement. What is it, and what problem does it address? [6 marks] Page 12 of 19

13 8051 Architecture Reference Program Memory (Code) Address 07FFFH (8051) Internal Memory (Data) Special Function Registers* 07FFH (89C2051) 7FH I/O registers accessed via memory locations Serial Port Timer 1 Ext Interrupt 1 Timer 0 Ext Interrupt 0 Reset 0023H 001BH 0013H 000BH 0003H 0000H Interrupt Vectors (location jumped to on Interrupt) Bank Select Bits in PSW 11 { 10 { 01 { 00 { Directly Addressable Bits 0-7F RB3* RB2* RB1* RB0* * Four banks of Registers addressable as R0-R7 2FH 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Reset value of Stack Pointer Program Counter: 16 bit register restricted to 0000H -> 07FFFH Special Function Registers (SFR) Space: Byte address Name Description Bits ("-" NOT bit addressable) 80H P0 Port 0 bit addressable: P0.7 -> P0.0 81H SP Stack Pointer - 82H DPL Low byte of DPTR - 83H DPH High byte of DPTR - 87H PCON Power control - 88H TCON Timer control TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0 89H TMOD Timer mode control - 8AH TL0 Timer 0 low byte - 8BH TL1 Timer 1 low byte - 8CH TH0 Timer 0 high byte - 8DH TH1 Timer 1 high byte - 90H P1 Parallel port 1 Bit Addressable P1.7 -> P1.0 98H SCON Serial control SM0-SM1-SM2-REN-TB8-RB8-TI -RI 99H SBUF Serial buffer - A0H P2 Port 2 Bit addressable: P2.7-P2.0 A8H IE Interrupt Enable EA - - -ES -ET1-EX1-ET0-EX0 B0H P3 Parallel port 3 Bit addressable: P3.7 -> P3.0 B8H IP Interrupt priority - - -PS -PT1-PX1-PT0-PX0 D0H PSW Program Status Word CY -AC -F0 -RS1-RS0-OV -F1 -P E0H ACC Accumulator ACC.7 -> ACC.0 F0H B B register B.7 -> B.0 Page 13 of 19

14 Interrupt control register IE: EA Global bit to enable interrupts ES,ETx Serial interrupt (either RI or TI), Clock interrupt on overflow Timer control and mode registers - 2 timers 0 and 1 TCON: TF0/TF1 Timer overflow flag timers 0/1 TR0/TR1 Timer run control bit. Set by software to switch timer ON TMOD: mode0-mode1 2 4-bit nibbles. Timer 1 high order nibble, Timer 0 low order. mode = 0 13 bit timer mode = 1 16 bit timer mode = 2 8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial I/O as bit rate (*32). 0FDH in Thx gives 9600bps for Mhz clock Serial control register SCON: SM0-SM1-SM2-REN should be set to 0111 for normal operation TI set when the character has been transmitted RI set when a character is received Power control register PCON: set to 2 will stop the processor Addressing Modes: Rn Register R0 - R7 of the currently selected register bank. direct 8-bit internal data location's address. This could be an internal Data RAM location (0-127) or a 8-bit internal Data RAM location addressed indirectly via register R0 or R1 #data 8-bit constant included in instruction. #data1616-bit constant included in instruction. addr11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of Program Memory as the first byte of the following instruction. addr16 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 2K byte Program Memory address space. rel Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the next instruction. bit Direct addressed bit in internal Data RAM or SFR. Page 14 of 19

15 Arithmetic operations: Byte Cycle C OV AC ADD A,Rn Add register to Accumulator 1 1 X X X ADD A,direct Add direct byte to Accumulator 2 1 X X X ADD A,@Ri Add indirect RAM to Accumulator 1 1 X X X ADD A,#data Add immediate data to Accumulator 2 1 X X X ADDC A,Rn Add register to Acc. with Carry 1 1 X X X ADDC A,direct Add direct byte to Acc. with Carry 2 1 X X X ADDC A,@Ri Add indirect RAM to Acc. with Carry 1 1 X X X ADDC A,#data Add immediate data to Acc. / Carry 2 1 X X X SUBB A,Rn Subtract reg. from Acc. with borrow 1 1 X X X SUBB A,direct Sub. direct byte from Acc. / borrow 2 1 X X X SUBB A,@Ri Sub. indirect RAM from Acc./ borrow 1 1 X X X SUBB A,#data Sub. imm. data from Acc. / borrow 2 1 X X X INC A Increment Accumulator 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 1 Increment indirect RAM 1 1 DEC A Decrement Accumulator 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 1 Decrement indirect RAM 1 1 INC DPTR Increment Data Pointer 1 2 MUL AB Multiply A and B X DIV AB Divide A by B X DA A Decimal adjust Accumulator 1 1 X Page 15 of 19

16 Logical operations: ANL A,Rn AND register to Accumulator 1 1 ANL A,direct AND direct byte to Accumulator 2 1 ANL A,@Ri AND indirect RAM to Accumulator 1 1 ANL A,#data AND immediate data to Accumulator 2 1 ANL direct,a AND Accumulator to direct byte 2 1 ANL direct,#data AND immediate data to direct byte 3 2 ORL A,Rn OR register to Accumulator 1 1 ORL A,direct OR direct byte to Accumulator 2 1 ORL A,@Ri OR indirect RAM to Accumulator 1 1 ORL A,#data OR immediate data to Accumulator 2 1 ORL direct,a OR Accumulator to direct byte 2 1 ORL direct,#data OR immediate data to direct byte 3 2 XRL A,Rn Exc-OR register to Accumulator 1 1 XRL A,direct Exc-OR direct byte to Accumulator 2 2 XRL A,@Ri Exc-OR indirect RAM to Accumulator 1 1 XRL A,#data Exc-OR immediate data to Acc. 2 1 XRL direct,a Exc-OR Accumulator to direct byte 2 1 XRL direct,#data Exc-OR imm. data to direct byte 3 2 CLR A Clear Accumulator 1 1 CPL A Complement Accumulator 1 1 RL A Rotate Accumulator left 1 1 Byte Cycle C OV AC RLC A Rotate Acc. left through Carry 1 1 X RR A Rotate Accumulator right 1 1 RRC A Rotate Acc. right through Carry 1 1 X SWAP A Swap nibbles within the Accumulator 1 1 Page 16 of 19

17 Data transfer: MOV A,Rn Move register to Accumulator 1 1 MOV A,direct Move direct byte to Accumulator 2 1 MOV A,@Ri Move indirect RAM to Accumulator 1 1 MOV A,#data Move immediate data to Accumulator 2 1 MOV Rn,A Move Accumulator to register 1 1 MOV Rn,direct Move direct byte to register 2 2 MOV Rn,#data Move immediate data to register 2 1 MOV direct,a Move Accumulator to direct byte 2 1 MOV direct,rn Move register to direct byte 2 2 MOV direct,direct Move direct byte to direct byte 3 2 MOV direct,@ri Move indirect RAM to direct byte 2 2 MOV direct,#data Move immediate data to direct byte 3 2 Move Accumulator to indirect RAM 1 1 Move direct byte to indirect RAM 2 2 Move immediate data to indirect RAM 2 1 MOV DPTR,#data16 Load Data Pointer with 16-bit const 3 2 MOVC A,@A+DPTR Move Code byte rel. to DPTR to Acc. 1 2 MOVC A,@A+PC Move Code byte rel. to PC to Acc. 1 2 PUSH direct Push direct byte onto stack 2 2 POP direct Pop direct byte from stack 2 2 XCH A,Rn Exchange register with Accumulator 1 1 XCH A,direct Exchange direct byte with Acc. 2 1 XCH A,@Ri Exchange indirect RAM with Acc. 1 1 XCHD A,@Ri Exchange low order digit indirect RAM with Accumulator 1 1 Byte Cycle C OV AC Number and String Formats: Numbers : Decimal - 34 Binary B Hexadecimal - a leading $ or a trailing h or H. e.g. $7F, 7Fh, 0FFH, $FF 0A8H Note: if not preceded by $ hex constants must start with 0-9. eg 0C7h Characters: Strings : Operators : 'A' - 'Abc' - A,00DH,00AH (mixed mode), "T" Only with DB directive for putting strings into CODE memory 'abc' or "abc" () + - / * MOD SHR SHL NOT AND OR XOR Page 17 of 19

18 Boolean variable manipulation: Byte Cycle C OV AC CLR C Clear Carry CLR bit Clear direct bit 2 1 SETB C Set Carry SETB bit Set direct bit 2 1 CPL C Complement Carry 1 1 X CPL bit Complement direct bit 2 1 ANL C,bit AND direct bit to Carry 2 2 X ANL C,/bit AND complement of dir. bit to Carry 2 2 X ORL C,bit OR direct bit to Carry 2 2 X ORL C,/bit OR complement of dir. bit to Carry 2 2 X MOV C,bit Move direct bit to Carry 2 1 X MOV bit,c Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 JNC rel Jump if Carry not set 2 2 JB bit,rel Jump if direct bit is set 3 2 JNB bit,rel Jump if direct bit is not set 3 2 JBC bit,rel Jump if dir. bit is set & clear bit 3 2 Program Branching: ACALL addr11 Absolute subroutine call 2 2 LCALL addr16 Long subroutine call 3 2 RET Return from subroutine 1 2 RETI Return from interrupt 1 2 AJMP addr11 Absolute jump 2 2 LJMP addr16 Long jump 3 2 SJMP rel Short jump (relative address) 2 2 Jump indirect relative to the DPTR 1 2 JZ rel Jump if Accumulator is zero 2 2 JNZ rel Jump if Accumulator is not zero 2 2 Byte Cycle C OV AC CJNE A,direct,rel Compare direct byte to Accumulator and jump if not equal 3 2 X CJNE A,#data,rel Compare immediate data to Accumulator and jump if not equal 3 2 X CJNE Rn,#data,rel Compare immediate data to register and jump if not equal 3 2 X Compare immediate data to indirect RAM and jump if not equal 3 2 X DJNZ Rn,rel Decr. register and jump if not zero 2 2 DJNZ direct,rel Decrement direct byte and jump if 3 2 not zero NOP No operation 1 1 Page 18 of 19

19 Assembler Directives and Controls ; Everything after a semicolon (;) on the same line is a comment Label: Must start in column 1 Defines a new Label - colon is optional. Controlling Memory Spaces and Code location ORG 56H Specify a value for the current segment's location counter. USE IRAM Makes the data space the currently selected segment USE ROM Makes the code space the currently selected segment Defining Byte and Bit values TEN EQU 10 EQUates 10 to symbol TEN, like #define in C, CONST in Delphi ON_FLAG BIT 6 Assigns BIT 6 (in data or SFR space) to the symbol ON_FLAG Allocating Memory SP_BUFFER: RMB 6 Reserves Memory Byte reserves 6 bytes of storage in current memory space (affected by most recent USE IRAM/ROM). Message: DB 'Hi' Define Byte(s): Store byte constants in code space. The following are all equivalent the string hello followed by a newline and a null. newline EQU 13 DB "H","E","L","L","O",13,0 DB "Hello",13,0 DB "Hello",newline,0 Page 19 of 19