AMBA PCI Bridge Quick Start

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1 AMBA PCI Bridge Quick Start v Sep 2002 PLDApplications, Quick Start PLDApplications Europarc Pichaury A2 1330, rue Guillibert Aix en Provence CEDEX 3 France Web: USA : Intl : Fax : support@plda.com (toll free)

2 Table of Contents TABLE OF CONTENTS BEFORE YOU START HARDWARE AND SOFTWARE REQUIREMENTS PACKAGE INSTALLATION INSTALLED FILES GETTING STARTED INSTALLING THE CORE Installing source files library Installing license code CREATING AN INSTANCE WITH THE BRIDGE WIZARD SETTING UP QUARTUS PROJECT CREATING A PCI SIMULATION TESTBENCH SIMULATION WITH ACTIVE HDL SIMULATION WITH MODELSIM CREATING A POST SYNTHESIS MODEL OF THE CORE TUTORIALS SIMPLE BRIDGE TUTORIAL Simulation environment Memory mapping Running simulation ARM HOST TUTORIAL Simulation environment Memory Mapping Running Simulation Quartus Project Software Compiling the design Testing the design on XA10 board THIRD PARTY SYNTHESIS

3 1 Before you start.. About this Guide u The primary focus of this guide is to show you how to create designs using PLDApplications AMBA PCI bridge core. This guide should be used as a manual for installing this product, as well as a learning tool for designers who want to get familiar with the design environment and flow. The tutorials included in this guide will be particularly useful for those who want a complete understanding of the design flow with AMBA PCI bridge and would like to practice all the steps involved in a programmable device based design HARDWARE AND SOFTWARE REQUIREMENTS u In order to install and use AMBA PCI core materials, the following configuration is required : A system running Windows 95/ 98/NT4/2000/XP, or any UNIX platform supporting Java. At least 64 MB of free disk space Altera Quartus II 2.1 or later when targeting Altera ARM Excalibur devices ARM Developer Suite or Gnu Pro ARM when targeting Altera ARM Excalibur devices PACKAGE INSTALLATION u Two versions of the AMBA PCI package are available : A Windows version for Windows 95, 98, NT 4.0, 2000, XP A UNIX version for all UNIX and Solaris workstations Open the install.htm file located on the release CD ROM with your web browser and select the installer that corresponds to your system. Follow on line instructions. u PCI core package is installed to the selected location on the host system and a ambapci_v2 folder is added to your program folder, location is platform dependant. It is located in the Start Programs menu on Windows systems. ambapci_v2 folder contains the following items : Ambapci_qs.pdf : this document in acrobat format Ambapci_ug.pdf : AMBA PCI core user's guide Uninstall : installer software also creates a un installer script that make it easy to remove complete package. Select Uninstall in the Start Programs ambapci_v2 menu. PCI core package is automatically removed from the host system. Bridge Wizard : Bridge customization assistant.

4 1.3. INSTALLED FILES u Once installed, AMBA PCI core package contains the following directory structure : core altera_lib asic_lib simulation_lib ref_designs Synthesis libraries for Altera Quartus source files for ASIC designs Simulation libraries for Active HDL, ModelSim & NCSim Reference designs testbench vhdl_sources simulation_lib PCI Testbench source files (1) Simulation libraries (2) software mac_os windows plda_api tools_sources labview_api PCI software tools for MacOS 8/9 PCI software tools for Windows 95 / 98 / NT 4.0 / 2000 / XP PLDA software API Source code of PCI software tools Package for using PLDA API with Labview doc User guides and documents in PDF format wizard Wizard packages (1) Source files are available in ASIC packages only. (2) This special version of the PCI Testbench can only be used with PLDA PCI products. 4

2 Getting Started 2.1. INSTALLING THE CORE u PCI core design files are encrypted : it is necessary to install a valid license code that will allow Quartus to read and process PCI core design files.

5 2 Getting Started 2.1. INSTALLING THE CORE u PCI core design files are encrypted : it is necessary to install a valid license code that will allow Quartus to read and process PCI core design files. Each license type requires a different license code that enables specific features : If you have an You can You must use this library Opencore license (evaluation only) Purchased license for Altera devices ASIC license Compile, synthesize and simulate AMBA PCI bridge. This license is limited to two months and no device programming is possible. Compile, synthesize and simulate AMBA P CI bridge, generate programming files for any Altera device. Compile, synthesize, simulate AMBA PCI bridge, implement this product in any device. core altera_lib amba_pci_v2_opencore.vhd core altera_lib amba_pci_v2_license.vhd core asic_lib asic Installing source files library u AMBA PCI core file corresponding to your license must be installed prior to working with the core. Follow these steps to install this file : Create a new project or edit an existing project in Quartus II Open the <Add Files Pathnames> dialog box and enter the select the PCI core.vhd file, then click <Add> The <Add Files> box should now display the PCI core file, always make sure that only one PCI core file is installed : There should not be more than AMBA PCI core file installed at a time or this could lead to unexpected compilation errors.

2.1.2. Installing license code u A license code is generated given the information provided when ordering a product or downloading an evaluation version.

6 Installing license code u A license code is generated given the information provided when ordering a product or downloading an evaluation version. A license code must be installed prior to using Altera tools : this authorization code is usually sent by and contains a FEATURE line such the one below : FEATURE 73E2_E364 alterad oct 1999 uncounted BFAC4DAF1DA5 \ VENDOR_STRING=lgjJa425iggBQADhOjRVzd$$ Follow these instructions if you have a license for your local machine, either dongle locked or network interface card locked : Dongle or NIC locked license Edit the license.dat file located in Quartus installation directory Add the complete PCI core license FEATURE lines to this file Quartus must be restarted for changes to take effect If you have a network floating license then this license must be installed on your Altera license server machine : Network floating license Have your system administrator add the complete PCI core license FEATURE lines to your server's Altera license file License server must be re started for changes to take effect 6

7 2.2. CREATING AN INSTANCE WITH THE BRIDGE WIZARD u Bridge Wizard is an easy to use tool that helps users define their custom bridge interface. It creates a VHDL or Verilog wrapper that instantiates the core with custom parameter values, input ports and output ports. Bridge Wizard is a standalone software that can be started directly from your computer's desktop : On Windows systems : select Start Programs ambapci_v2 Bridge Wizard then select an instance to create or edit, then follow instructions. On UNIX systems : Open a terminal window and type : /bin/sh Bridge_wiz (this executable is located in Wizard installation directory). Select an instance to create or edit, then follow instructions. u Once Bridge Wizard is started, user can define a custom AMBA PCI interface according to design's requirements. First page allows you to define core instance's main characteristics : On line help is available for all possible settings : click Help button at any time. u Bridge wizard creates an instance file when customization is complete : <design_name>.vhd is bridge instance wrapper that must be included with your design files when synthesizing or simulating your design. Note that for simulation bridge PCI ready length is reduced from 2 25 to 2 9 clock cycles. AMBA PCI bridge instances created with previous versions of this product must be upgraded before design can be recompiled. Edit the instance with Bridge Wizard, then click <Skip Customization> button on the first page. 7

2.3. SETTING UP QUARTUS PROJECT u It is highly recommended that you use a suitable constraints file in order to get optimal timing performance and chip layout.

Bridge Wizard creates a TCL project setup file for Quartus named <project_name>_setup.

8 2.3. SETTING UP QUARTUS PROJECT u It is highly recommended that you use a suitable constraints file in order to get optimal timing performance and chip layout. Following window will appear once you have customized your core : Check Create pin out and constraints for Quartus box and specify project parameters. Bridge Wizard creates a TCL project setup file for Quartus named <project_name>_setup.tcl that contains : instructions to set up a Quartus project appropriate logic & timing constraints for your core instance an optimized PCI pin out for the selected device Run Quartus select View Auxiliary Windows Tcl console menu in the Tcl console window type the following commands : cd <path to the directory were TCL file is located> source <project_name>_setup.tcl Note that 66 MHz PCI designs may require some additional logic assignments to achieve full timing compliance. Contact PLDA for more information. 8

2.4. CREATING A PCI SIMULATION TESTBENCH u Bridge Wizard can create custom top level simulation environments using PLD Applications PCI Testbench.

9 2.4. CREATING A PCI SIMULATION TESTBENCH u Bridge Wizard can create custom top level simulation environments using PLD Applications PCI Testbench. It creates fully commented VHDL or Verilog simulation testbench skeletons in which you can insert your design easily : Edit output file and insert your own PCI design in it. Refer to inline comments for more information You can write your own PCI test bench scripts and simulate entire designs. Refer to the testbench user s manual for detailed explanations. u You may edit the script files to view the set of commands that the test bench will read and convert into PCI transactions. An example script file is shown below : Start the simulation. The simulation is automatically stopped once script.txt file has been fully processed. You can view simulation results from the waveform display and from the script.log file 9

2.5. SIMULATION WITH ACTIVE HDL u AMBA PCI core package contains all the elements required for VHDL or Verilog simulation with Aldec Active HDL version 4.2 and later.

10 2.5. SIMULATION WITH ACTIVE HDL u AMBA PCI core package contains all the elements required for VHDL or Verilog simulation with Aldec Active HDL version 4.2 and later. AMBA PCI Core and PCI Testbench come into ready to use pre compiled libraries. Follow these steps to create and simulate a design : Start Active HDL and select File New design menu. Create a new project : Click Next >, then select Add Existing Files.. on the next page and select source files, including the PCI Wizard instance you must have created before. Now you must map AMBA PCI core and PCI testbench libraries : select View Library manager menu Add libraries to the libraries list : click on button and then add the following libraries : core / simulation_lib / activehdl / amba_pci_v2.lib testbench / simulation_lib / activehdl / pci_testbench.lib It is now possible to simulate any custom instance of the PCI core and backend logic with the PCI testbench. Refer to Testbench Wizard section and PCI Testbench User's guide. 10

2.6. SIMULATION WITH MODELSIM u AMBA PCI core package contains all the elements required for VHDL or Verilog simulation with Mentor ModelSim version 5.6 and later.

11 2.6. SIMULATION WITH MODELSIM u AMBA PCI core package contains all the elements required for VHDL or Verilog simulation with Mentor ModelSim version 5.6 and later. AMBA PCI Core and PCI Testbench come into ready to use pre compiled libraries. Environment variables necessary to run simulation with ModelSim are set by installer. Set following system variables before starting simulation with ModelSim :..set AMBAPCI_LIB variable to amba_pci_v2..set AMBAPCI_ROOT variable to the path to AMBA PCI core install directory Follow these steps to create and simulate a design : Start ModelSim and create a new project Add your source files to the project, including the Bridge Wizard instance you must have created before. Now you must map AMBA PCI core and PCI testbench libraries. Type following commands : vmap pci_testbench /testbench/simulation_lib/modelsim/pci_testbench vmap ambapci_v2 /core/simulation_lib/modelsim/amba_pci_v2 ambapci_v2 and pci_testbench libraries should appear in the library browser : It is now possible to simulate any custom instance of the PCI core and backend logic with the PCI testbench. Refer to Testbench Wizard section and PCI Testbench User's guide. Updating the pre compiled library may be necessary when using a newer version of ModelSim. Type the following commands at ModelSim command prompt : vcom refresh work ambapci_v2 vcom refresh work pci_testbench Simulation with AMBA PCI Core and PCI Testbench requires a VHDL license even if all your source files are written in Verilog. 11

2.7. CREATING A POST SYNTHESIS MODEL OF THE CORE u Bridge Wizard generated instance of the core must be compiled with Quartus in order to create a VHDL behavioral post synthesis model of the core.

12 2.7. CREATING A POST SYNTHESIS MODEL OF THE CORE u Bridge Wizard generated instance of the core must be compiled with Quartus in order to create a VHDL behavioral post synthesis model of the core. This will make it possible to simulate PCI core in any VHDL or Verilog simulator. Proceed as detailed below : Open Quartus and create a new project to compile your PCI core instance. Select Project EDA Tool settings menu. Then select your simulation tool (or any tool if your simulator is not listed) : Start compilation Compilation generates a VHDL/Verilog netlist and saves it to a.vho or.vo file. Rename it to.vhd /.v, this file can now be used with a simulator u Altera tools also generate a SDF file (.sdo) that contains timing information. This file can be used to perform VITAL timing simulation, however Altera VITAL libraries must be available in the simulator. 12

13 3 Tutorials u AMBA PCI packages contain two tutorial designs in order to help designers build their applications. Each tutorial is simple and illustrates a single topic in order to show designers how to implement some commonly used functions : ref_designs simplebridge vhdl verilog A simple bridge design, only for simulation. armhost verilog vhdl A complete system including a hostbridge and an ARM922 processor. Covers simulation, software and hardware development SIMPLE BRIDGE TUTORIAL u Simple bridge tutorial design only contains a basic AMBA PCI core instance created with the Bridge Wizard. This design is extremely simple and makes it possible to exercise AHB and PCI side of the bridge directly : Simple Bridge Core Instance AHB Bus PCI Bus simplebridge.vhd This design contains only one design file : simplebridge is a basic AMBA PCI bridge simple bridge instance created with the Bridge Wizard. Edit this file with the Bridge Wizard in order to view/modify settings. It features two DMA channels and a two PCI AHB window. simplebridge_tutorial is not a complete design and thus cannot be tested in hardware as is. It must be first connected to a processor. 13

14 3.1.1 Simulation environment u A testbench (simulation environment) is provided so that this design can be directly simulated in any VHDL or Verilog simulator. This testbench connect the bridge instance to PCI and AHB bus emulation modules : simplebridge_testb.vhd Altera Bus Functional Model Simple Bridge Core Instance PCI Testbench altera_bfm.vhd + bfm_inst.vhd AHB Bus simplebridge.vhd PCI Bus Target Device Master Device.LOG.LOG ahb.dat ahb.log script.txt script.log.htm exc_bus_translate Altera utility ahb.txt simplebridge_testb is the top level design : it is a simulation testbench generated with the Testbench Wizard that connects all design elements together. It also generates power on reset and clocks for the processor. altera_bfm is an AHB bus functional model designed by Altera that emulates an AHB master/slave device. This module reads ahb.dat file and issues transactions on the AHB bus according to instructions stored in this file. ahb.dat file is obtained by processing ahb.txt file with Altera exc_bus_translate utility, part of Quartus II software package. Refer to Altera "Bus Functional Model User Guide" document for detailed information. pci_testbench is a module that emulates a PCI chipset including a master, a target and a PCI arbiter modules. PCI Testbench read commands from script.txt file and issues transactions on the PCI bus accordingly. Refer to "PCI Testbench User Guide" for detailed information on this product. u User is free to modify ahb.txt and script.txt files in order to modify simulation scenario and test other operating conditions. 14

15 3.1.2 Memory mapping u Some data transfers are performed during simulation between AHB and PCI memory locations. Figure below shows addresses of memory ranges that are define in the testbench : Altera Bus Functional Model Simple Bridge Core Instance PCI Testbench Memory #0 A00h AHB AHBPCI NP 100h PCI Bus Buffer #0 300h Memory #1 B00h AHBPCI PF 200h AHB Bridge Regs h Buffer #1 400h Altera BFM contains two 256 bytes memories connected to AHB bus, at AHB address A00h and B00h. PCI Testbench features a built in target device that implements two 256 bytes buffers in BAR0 and BAR1 address spaces at PCI address 300h and 400h (these addresses are initialized by a PCI transfer, see script.txt) PCI AHB window contain a non prefetchable and a prefetchable ranges implemented in bridge BAR3 and BAR4 address space, at PCI address 100h and 200h (these address are initialized by a PCI transfer, see script.txt) Bridge registers are accessible from AHB bus, at AHB address h Running simulation u ModelSim : there is a ready to use modelsim.do macro that compiles design files and sets up simulation automatically : Start Modelsim, you do not need to create a project Select <File/Change Directory> menu and select 'vhdl' or 'verilog' directory as the working directory. Type 'do modelsim.do' at Modelsim prompt to set up simulation Check that no error occurred then type 'run all' to start simulation u ActiveHdl : First you must create a new project and add AMBA PCI and PCI Testbench to the design libraries list. Then compile design files in the following order : altera_bfm bfm_inst memmap ahb_decoder simplebridge simplebridge_testb You can now start simulation. 15

16 3.2. ARM HOST TUTORIAL u ARM host tutorial design is complete system designed to run on Altera XA10 development board. This design features an embedded ARM922 processor with integrated peripherals and a AMBA PCI host bridge core. This system is completely stand alone : arm_stripe.vhd ARM922 System Sram0 Sram1 AHB Bus Host Bridge Core Instance PCI Bus PCI Device PCI Device EBI UART hostbridge.vhd Add on PCI boards arm_host.vhd On board flash VT100 Terminal PCI bus is designed to be connected to two on board PCI slots. Each slot can receive any 3.3V or universal PCI add on board. Software is stored in on board flash (connected to AHB bus through EBI interface) and is downloaded to SRAM0 internal memory at power up. Program data and variables are stored in SRAM1 internal memory. Integrated UART port can be connected to a VT100 terminal so that it is possible to communicate with CPU from a remote computer. u ARM922 system and host bridge logic are both implemented in an Altera EPXA10 device : arm_host is the complete system that is ready to be implemented : it just connects CPU to the host bridge. This design can be either simulated or compiled with Quartus and tested on XA10 development board. hostbridge is a basic AMBA PCI bridge host bridge instance created with the Bridge Wizard. Edit this file with the Bridge Wizard in order to view/modify settings. It features two DMA channels, a PCI AHB window and an AHB PCI window. arm_stripe is a processor instance create with Altera SOPC system builder tool. It instantiates an embedded ARM 32 bit processor with some integrated peripherals. You can edit this file and view settings from within Quartus software with the SOPC builder. Check Altera web site for a complete description of XA10 development board and ARM based Excalibur devices. 16

17 3.2.1 Simulation environment u A testbench (simulation environment) is provided so that this design can be directly simulated in ModelSim. This testbench connect the design to a PCI bus emulation module : arm_host_testb.vhd arm_stripe.vhd PCI Testbench ARM922 System AHB Bus Host Bridge Core Instance PCI Bus Target Device Sram0 EBI Sram1 UART hostbridge.vhd Master Device arm_host.vhd memory initialisation files script.txt.log script.log.htm arm_host_testb is the top level design : it is a simulation testbench generated with the Testbench Wizard that connects all design elements together. It also generates power on reset and clocks for the processor. pci_testbench is a module that emulates a PCI chipset including a master, a target and a PCI arbiter modules. PCI Testbench read commands from script.txt file and issues transactions on the PCI bus accordingly. Refer to "PCI Testbench User Guide" for detailed information on this product. u Processor is simulated with a full model provided by Altera in Quartus software package. CPU is initialized using a set of memory initialization files (memory.regs, memory.sram0 ) and then software code is automatically executed after reset and initialization sequence. User is free to modify script.txt files in order to modify simulation scenario and test other operating conditions. Software code can be modified but it must be compiled with Quartus (using simulation build) in order to generate new memory initialization files. 17

18 3.2.2 Memory Mapping u Some data transfers are performed during simulation between AHB and PCI memory locations. Figure below shows addresses of memory ranges that are defined in the system : ARM922 System Host Bridge Core Instance PCIAHB NP h SRAM # h SRAM # h AHB Bus PCIAHB PF h Bridge Regs h AHBPCI NP h PCI Bus PCI Testbench AHBPCI PF C h SRAM1 contains a 1KB memory buffer (buffer[] variable in the C code) connected to AHB bus, however it is dynamically allocated and depends on software build. PCI Testbench features a built in target device that implements a 1KB memory buffer in BAR0 address space at PCI address CCCC0000h (this offset is initialized by CPU using a configuration access, see software code) CPU window is a 1KB address range implemented in bridge BAR4 address space, at PCI address AAAA0000h (this address is hardwired and set in the Bridge Wizard) Bridge registers are accessible from AHB bus, at AHB address h Running Simulation u ModelSim : there is a ready to use modelsim.do macro that compiles design files and sets up simulation automatically : Start Modelsim, you do not need to create a project Select <File/Change Directory> menu and select 'quartus_vhdl' or 'quartus_verilog' directory as the working directory. Type 'do modelsim.do' at Modelsim prompt to set up simulation Check that no error occurred then type 'run all' to start simulation 18

19 3.2.4 Quartus Project u A complete Quartus project is available in quartus_vhdl or quartus_verilog directory. Essential files are detailed below : quartus_xxx arm_host.quartus arm_host.esf arm_host.psf arm_host.csf software Gnu_build ADS_build memory.* program_board Quartus project file Defines PCI timing constraints Project settings file This file defines target device and pin out Contains software source code files Holds output files of "Gnu_build" mode Holds output files of "ADS_build" mode Memory initialization files for simulation. These files are generated by Quartus after compilation. Script that downloads program to XA10 board Software u Quartus project defines two sets of software build settings : Gnu_build for use with GNU Pro ARM toolkit Ads_build for use with ARM ADS toolkit Source code files are located in <quartus_project/software> directory : main.c amba_pci.c amba_pci_pnp.c Main source file : this file contains a separate main() function for both builds. Edit and modify this file in order to change system's behavior. AMBA PCI SDK : provides basic functions to access the bridge AMBA PCI PCI Plug n play : basic plug n play function that scans PCI slots and automatically detects and configures PCI devices. sdk Low level and initisalisation functions for ARM processors sdk / gnu Low level functions for use with ARM ADS only sdk / ads Low level functions for GNU Pro ARM only 19

20 3.2.6 Compiling the design u Follow procedure below in order to recompile the design. Note that either GNUPro for ARM toolkit or ARM ADS toolkit must be installed on your machine in order to be able to compile software : 1. Close simulation then open arm_host.quartus project file 2. Select <Project Project Wizard> menu, then click <Next> button : 3. A list display project's source files. Add AMBA PCI source file to the source files list. 4. Click on <Software Mode> icon in order to switch to software mode 5. Edit and modify software source code and design files as needed 6. Click on software build button in order to start compilation. 7. Wait for compilation completion, programming file is ready to be downloaded to the board. Now, prepare the board as explained in the next chapter. 20

21 3.2.7 Testing the design on XA10 board u This section details how to set up XA10 development board in order to test the design : 1. Install the board as specified in Altera "EPXA10 Development Board Getting Started" document and set the board in Boot from Flash configuration as shown in table 1 in this document. 2. Connect ByteBlaster or MasterBlaster cable to JTAG port 3. Connect UART1 serial port to your computer's serial port using a crossed serial cable 4. Open a terminal on your computer (HyperTerminal or equivalent software) with the following settings : bauds, 8 bits, no parity, 1 stop bit, no flow control 5. Turn on the board and run program_board script in order to download program to onboard flash and restart the processor. 6. Program is downloaded to the board and processor is automatically restarted. Software is executed and scans PCI slots and output should be displayed in terminal window : 7. Try to insert or remove PCI cards from the two on board PCI slots (board must be poweredoff), then restart the board to see the changes. Please note that XA10 board only supports 3.3V or universal 3.3/5V PCI cards. 5V only PCI cards can not be used in this system. 21

22 4 Third Party Synthesis u A design that incorporate a AMBA PCI core instance can be synthesized with a 3 rd party synthesis tool. However synthesis cannot be performed on the core itself but on backend logic only : AMBA PCI core library.edf Quartus User design files Synthesis Tools EDIF file Follow these steps : Add all design source files to synthesis tool's project. Declare the AMBA PCI core instance as a black box Select target device (device, package, speed grade) and start synthesis The synthesizer outputs an EDIF or.vqm file for Quartus Start the compilation in Quartus : EDIF design is combined with AMBA PCI core automatically and design fitting is performed.

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