Computer Architecture

Transcription

1 Computer Architecture

2 Springer-Verlag Berlin Heidelberg GmbH

3 Silvia M. Mueller Wolfgang J. Paul Computer Architecture Complexity and Correctness With 214 Figures and 185 Tables Springer

4 Silvia Melitta Mueller IBM Lab Boblingen - Dept SchOnaicherstr lO32 Boblingen, Germany SMM@de.ibm.com Wolfgang J. Paul Fachbereich Informatik Universitat des Saarlandes 1m Stadtwald, Gebaude Saarbriicken, Germany wjp@cs.uni-sb.de Cover picture by Jantje JanSen, Karlsruhe Library of Congress Cataloging-in-Publication Data applied for Die Deutsche Bibliothek - CIP-Einheitsaufnahme Muller, Silvia Melitta: Computer architecture: complexity and correctness; with 185 tablesl Silvia M. Muller; Wolfgang J. Paul. - Berlin; Heidelberg; New York; Barcelona; Hong Kong; London; Milan; Paris; Singapore; Tokyo: Springer, 2000 ACM Subject Classification (1998): B, C ISBN ISBN (ebook) DOI / This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilm or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag. Violations are liable for prosecution under the German Copyright Law. Springer-Verlag is a company in the BertelsmannSpringer publishing group. Springer-Verlag Berlin Heidelberg 2000 Originally published by Springer-Verlag Berlin Heidelberg New York in Softcover reprint of the hardcover 1st edition 2000 The use of general descriptive names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. Typesetting: Camera-ready by the authors Design: design + production GmbH, Heidelberg Printed on acid-free paper SPIN /3l42SR

5 Preface I N THIS BOOK we develop at the gate level the complete design of a pipelined RISe processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEEcompliant floating point unit. The design is completely modular. This permits us to give rigorous correctness proofs for almost every part of the design. Also, because we can compute gate counts and gate delays, we can formally analyze the cost effectiveness of all parts of the design. Acknowledgments This book owes much to the work of the following students and postdocs: P. Dell, G. Even, N. Gerteis, C. Jacobi, D. Knuth, D. Kroening, H. Leister, P.-M. Seidel. March 2000 Silvia M. Mueller Wolfgang 1. Paul

6 Contents 1 Introduction 1 2 Basics Hardware Model Components Cycle Times Hierarchical Designs Notations for Delay Formulae Number Representations and Basic Circuits Natural Numbers Integers Basic Circuits Trivial Constructions Testing for Zero or Equality Decoders Leading Zero Counter Arithmetic Circuits Carry Chain Adders Conditional Sum Adders Parallel Prefix Computation Carry Lookahead Adders Arithmetic Units Shifter... 31

7 Table of contents viii 2.5 Multipliers School Method Carry Save Adders Multiplication Arrays /2-Trees Multipliers with Booth Recoding Cost and Delay of the Booth Multiplier Control Automata Finite State Transducers Coding the State Generating the Outputs Computing the Next State Moore Automata Precomputing the Control Signals Mealy Automata Interaction with the Data Paths.. Selected References and Further Reading Exercises A Sequential DLX Design 3.1 Instruction Set Architecture Instruction Formats Instruction Set Coding Memory Organization 3.2 High Level Data Paths Environments General Purpose Register File Instruction Register Environment PC Environment ALU Environment Memory Environment Shifter Environment SHenv Shifter Environment SH4Lenv 3.4 Sequential Control Sequential Control without Stalling Parameters of the Control Automaton A Simple Stall Engine 3.5 Hardware Cost and Cycle Time Hardware Cost Cycle Time Selected References and Further Reading

8 4 Basic Pipelining 4.1 Delayed Branch and Delayed PC 4.2 Prepared Sequential Machines Prepared DLX Data Paths FSD for the Prepared Data Paths Precomputed Control A Basic Observation Pipelining as a Transformation Correctness Hardware Cost and Cycle Time Result Forwarding Valid Flags Stage Forwarding Correctness. Hardware Interlock Stall Engine Scheduling Function Simulation Theorem Cost Performance Analysis Hardware Cost and Cycle Time Performance Model Delay Slots of Branch/Jump Instructions CPI Ratio of the DLX Designs Design Evaluation Selected References and Further Reading Exercises Table of contents 5 Interrupt Handling 5.1 Attempting a Rigorous Treatment of Interrupts 5.2 Extended Instruction Set Architecture Interrupt Service Routines For Nested Interrupts Admissible Interrupt Service Routines Set of Constraints Bracket Structures Properties of Admissible Interrupt Service Routines Interrupt Hardware Environment PCenv Circuit Daddr Register File Environment RFenv Modified Data Paths Cause Environment CAenv Control Unit ix

9 Table of contents 5.6 Pipelined Interrupt Hardware PC Environment., Forwarding and Interlocking Stall Engine Cost and Delay of the DLXn Hardware Correctness of the Interrupt Hardware Selected References and Further Reading Exercises Memory System Design A Monolithic Memory Design. ' The Limits of On-chip RAM A Synchronous Bus Protocol Sequential DLX with Off-Chip Main Memory The Memory Hierarchy The Principle of Locality The Principles of Caches Execution of Memory Transactions A Cache Design Design of a Direct Mapped Cache Design of a Set Associative Cache Design of a Cache Interface Sequential DLX with Cache Memory Changes in the DLX Design Variations of the Cache Design Pipelined DLX with Cache Memory Changes in the DLX Data Paths Memory Control Design Evaluation Selected References and Further Reading Exercises x 7 IEEE Floating Point Standard and Theory of Rounding Number Formats / Bmary Fractions Two's Complement Fractions Biased Integer Format IEEE Floating Point Numbers Geometry of Representable Numbers Convention on Notation Rounding Rounding Modes

10 7.2.2 Two Central Concepts Factorings and Normalization Shifts Algebra of Rounding and Sticky Bits Rounding with Unlimited Exponent Range Decomposition Theorem for Rounding Rounding Algorithms Exceptions Overflow Underflow Wrapped Exponents Inexact Result Arithmetic on Special Operands Operations with NaNs Addition and Subtraction Multiplication Division Comparison Format Conversions Selected References and Further Reading Exercises Floating Point Algorithms and Data Paths Unpacking Addition and Subtraction Addition Algorithm Adder Circuitry Multiplication and Division Newton-Raphson Iteration Initial Approximation Newton-Raphson Iteration with Finite Precision Table Size versus Number of Iterations Computing the Representative of the Quotient Multiplier and Divider Circuits Floating Point Rounder Specification and Overview Normalization Shift Selection of the Representative Significand Rounding Post Normalization Exponent Adjustment Exponent Rounding Circuit SPEcFPRND 410 Table of contents xi

11 Table of contents xii 8.5 Circuit FCon Floating Point Condition Test Absolute Value and Negation IEEE Floating Point Exceptions 8.6 Format Conversion Specification of the Conversions Implementation of the Conversions 8.7 Evaluation of the FPU Design Selected References and Further Reading 8.9 Exercises Pipelined DLX Machine with Floating Point Core 9.1 Extended Instruction Set Architecture FPU Register Set Interrupt Causes FPU Instruction Set Data Paths without Forwarding Instruction Decode Memory Stage Write Back Stage Execute Stage Control of the Prepared Sequential Design Precomputed Control without Division Supporting Divisions Pipelined DLX Design with FPU PC Environment Forwarding and Interlocking Stall Engine Cost and Delay of the Control Simulation Theorem Evaluation Hardware Cost and Cycle Time Variation of the Cache Size. 9.6 Exercises A DLX Instruction Set Architecture Al DLX Fixed-Point Core: FXU. AI.I Instruction Formats.. Al.2 Instruction Set Coding A2 Floating-Point Extension.. A2.1 FPU Register Set.. A2.2 FPU Instruction Set

12 B Specification of the FDLX Design 527 B.I RTL Instructions of the FDLX 527 Bol.1 Stage IF Bol.2 Stage ID 527 B.l.3 Stage EX 529 Bol.4 StageM B.l.5 StageWB B.2 Control Automata of the FDLX Design 534 Bo201 Automaton Controlling Stage ID B.202 Precomputed Control Table of contents Bibliography 543 Index 549 xiii