EE Dept., SJSU 9/6/98 VHDL.1 Fundamental of VHDL Design for FPGA All rights reserved /chp

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2 Agenda Chapter 1: Who is in attendant? What is VHDL? Chapter 2: VHDL Design w/ Max+PlusII Chapter 3: ABC s of VHDL Chapter 4: Introduction to Data Types Chapter 5: Processes Chapter 6: Basic syntax Chapter 7: Attributes & Data types Chapter 8: Signals & Signal Assignments Chapter 9: Concurrent Assignments Chapter 10: Summary EE Dept., SJSU 9/6/98 VHDL.2 Fundamental of VHDL Design for FPGA All rights reserved /chp

3 Chapter 1 - Who is in Attendance? Designers to perform digital design with VHDL Target to Altera FPGA using MaxPlusII as a design tool Possess little or no VHDL background, however, familiar to C programming language Intermediate digital design knowledge, e.g., comfortable with sync/async digital design EE Dept., SJSU 9/6/98 VHDL.3 Fundamental of VHDL Design for FPGA All rights reserved /chp

4 Chapter 1 - What is VHDL? Acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. Design language for digital & VLSI systems Developed by IEEE Analysis/Standard group & approved by IEEE Standards Boards in 1987 (IEEE Standard ) - Newer standard is available: IEEE Supports behavioral, dataflow, and structural modeling features. Top-down hierarchical modeling. Powerful features: technology independence, logic synthesis, test vector generation, and design verification. EE Dept., SJSU 9/6/98 VHDL.4 Fundamental of VHDL Design for FPGA All rights reserved /chp

5 Architectural Design Architectural Design in VHDL is portable among VHDL compilers Synthesis Many different synthesis tools produce gate level schematics from VHDL Manufacture The manufacturing design tools are targeted specifically for one silicon technology, e.g., FPGA, gate arrays, custom IC Silicon Chip Prototype EE Dept., SJSU 9/6/98 VHDL.5 Fundamental of VHDL Design for FPGA All rights reserved /chp

6 Chapter 2 Designing with VHDL in MaxPlusII Environment (1) Step1: An algorithm is coded in VHDL, ex: lab1.vhd (MaxPlusII=>TextEditor) Step2: Define MaxPlusII project lab1.vhd & VHDL syntax check (FILE=>Project=>Save&Check) Step4: MaxPlusII complete compilation if no syntax error ( press START button) EE Dept., SJSU 9/6/98 VHDL.6 Fundamental of VHDL Design for FPGA All rights reserved /chp

Define a project EE Dept., SJSU 9/6/98 VHDL.

9 Simulation for Zero-Delay Events (Functional Sim.) (not in student version) Select Functional SNF Extractor, recompile & simulate Note: only 3 boxes EE Dept., SJSU 9/6/98 VHDL.9 Fundamental of VHDL Design for FPGA All rights reserved /chp

10 Designing with VHDL in MaxPlusII Environment (2) Step5: Define simulation waveform (MaxPlusII=>WaveformEditor) Step6: Simulate (MaxPlusII=>Simulator or File=>Project=>Save&Simulate) Step7: Timing Analyze (MaxPlusII=>TimingAnalyzer) May require iterations until all design specifications are satisfied EE Dept., SJSU 9/6/98 VHDL.10 Fundamental of VHDL Design for FPGA All rights reserved /chp

11 Chapter 3 - ABC s of VHDL Hardware Behavior & Structure Two basic questions about hardware: How does it behave? What does it consist of? HW behavior: function & timing HW structure: component, port & signals In VHDL, a component is represented by the Design Entity A port is the component s connection to the outside A signal is a connection between components EE Dept., SJSU 9/6/98 VHDL.11 Fundamental of VHDL Design for FPGA All rights reserved /chp

12 Design Entity entity LAB1 is port( A, B, C : in BIT; Z : out BIT ); end LAB1; entity: name the design & its ports architecture INTERNAL of LAB1 is begin Z <= (A and B) or C; end INTERNAL; architecture: provides details of the design EE Dept., SJSU 9/6/98 VHDL.12 Fundamental of VHDL Design for FPGA All rights reserved /chp

13 Entity The syntax is: <Entity Declaration> ::= entity ENTITY_NAME is <Generic> <Ports> end ENTITY_NAME ; Example entity LAB1 is port( A, B, C : in BIT; Z : out BIT ); end LAB1; A B C Z EE Dept., SJSU 9/6/98 VHDL.13 Fundamental of VHDL Design for FPGA All rights reserved /chp

14 Architecture The syntax is: <Architecture Body> ::= architecture ARCH_NAME of ENTITY_NAME is [architecture_declarative_part] begin [architecture_statement_part] end ARCH_NAME Example: architecture INTERNAL of LAB1 is begin Z <= (A and B) or C; end INTERNAL; NOTE: architecture_declarative_part declares items (types, constants & signals) used only in this architecture architecture_statement_part is the actual design description EE Dept., SJSU 9/6/98 VHDL.14 Fundamental of VHDL Design for FPGA All rights reserved /chp

15 3 Styles of Design Description(1) ENTITY LAB1 architecture AR1 of LAB1 is architecture AR2 of LAB1 is architecture AR3 of LAB1 is behavior data flow structure EE Dept., SJSU 9/6/98 VHDL.15 Fundamental of VHDL Design for FPGA All rights reserved /chp

16 3 Styles of Design Description(2) Behavioral description specifies the architecture in an algorithmic way like a computer program The Data Flow description utilizes the concurrent statements Structural description defines interconnections of components (previously compiled design units) EE Dept., SJSU 9/6/98 VHDL.16 Fundamental of VHDL Design for FPGA All rights reserved /chp

17 3 Styles of Design Description(3) Example: Behavioral Description architecture AR1 of COMPARE is begin process( A, B) begin if (A = B) then C <= 1 ; else C <= 0 ; end if; end process; end AR1; EE Dept., SJSU 9/6/98 VHDL.17 Fundamental of VHDL Design for FPGA All rights reserved /chp

18 3 Styles of Design Description(4) Structural Description Example: (XORGATE & NOTGATE are previously compiled design units) architecture STRUC of COMPARE is signal I: bit; component XORGATE port(x, Y: in bit; Z: out bit); end component; component NOTGATE port(x: in bit; Z: out bit); end component; begin U1: XORGATE port map( A, B, I); U2: NOTGATE port map(i, C); end STRUC; A B X Y Z I X Z C EE Dept., SJSU 9/6/98 VHDL.18 Fundamental of VHDL Design for FPGA All rights reserved /chp

19 3 Styles of Design Description(5) Data Flow (Concurrent) Description (1) This is a new & abstract idea, so be patient :-) Concurrent statements are executed with no defined order Concurrent statements are also used for structural descriptions They synthesize combinational circuitry EE Dept., SJSU 9/6/98 VHDL.19 Fundamental of VHDL Design for FPGA All rights reserved /chp

20 3 Styles of Design Description(6) Data Flow (Concurrent) Description (2) Example: A <= B + C; D <= E + F; B C E F A B If B or C changes statement 1 is executed If E or F changes statement 2 is executed More details later EE Dept., SJSU 9/6/98 VHDL.20 Fundamental of VHDL Design for FPGA All rights reserved /chp

21 VHDL Libraries A library is a directory of files associated with previously compiled units The default library is called WORK, referring to the current working directory 4 main libraries: altera: primitives & TTL 74xxx family ieee: see VHDL packages (p.21) std: defines types & text I/O vital (not popular) EE Dept., SJSU 9/6/98 VHDL.21 Fundamental of VHDL Design for FPGA All rights reserved /chp

22 VHDL Packages (1) Altera provides several packages for use with MaxPlusII. They are in sub-dir \maxplus2\max2vhdl. A package is used to store commonly referenced TYPES, CONSTANTs, FUNCTIONs, PROCEDUREs, or COMPONENTs. EE Dept., SJSU 9/6/98 VHDL.22 Fundamental of VHDL Design for FPGA All rights reserved /chp

23 VHDL Packages (2) Syntax: library LIBRARY_NAME use LIBRARY_NAME.PACKAGE_NAME.ITEM_NAME Example: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY lab2a IS PORT (op1, op2 : IN UNSIGNED(7 downto 0); result : OUT INTEGER); END lab2a; ARCHITECTURE adder_maxpld OF lab2a IS BEGIN result <= CONV_INTEGER(op1 + op2); END adder_maxpld; EE Dept., SJSU 9/6/98 VHDL.23 Fundamental of VHDL Design for FPGA All rights reserved /chp

24 VHDL Packages (3) File: Package: Library: Contents: maxplus2.vhd maxplus2 altera MAX+PLUS II logic functions supported by VHDL. std1164.vhd std_logic_1164 ieee Standard for describing interconnection data types for VHDL std1164b.vhd modeling, and the STD_LOGIC and STD_LOGIC_VECTOR types. arith.vhd std_logic_arith ieee SIGNED and UNSIGNED types, arithmetic and comparison arithb.vhd functions for use with SIGNED and UNSIGNED types, and the conversion functions CONV_INTEGER, CONV_SIGNED, and CONV_UNSIGNED. signed.vhd std_logic_signed ieee Functions that allow MAX+PLUS II to use STD_LOGIC_VECTOR types as if they are SIGNED types. signedb.vhd SIGNED types. unsigned.vhd std_logic_unsigned ieee Functions that allow MAX+PLUS II to use STD_LOGIC_VECTOR types as if they are UNSIGNED types. unsignedb.vhd If you use more than one of these packages in a single VHDL Design File, you must use them in the order in which they are listed in this table. SEE ALSO APPENDIX A. EE Dept., SJSU 9/6/98 VHDL.24 Fundamental of VHDL Design for FPGA All rights reserved /chp

25 Delimiters Case insensitive White space insensitive Statement terminator (;) Item seperator (,) Comment (--) EE Dept., SJSU 9/6/98 VHDL.25 Fundamental of VHDL Design for FPGA All rights reserved /chp

26 Chapter 4: Introduction to Data Types TYPES SCALAR COMPOSITE ENUM NUMERIC PHYSICAL ARRAY RECORD REAL INTEGER TYPE is a named set of values with common characteristics SUBTYPE is a subset of the values of a type SCALAR is one-dimensional while COMPOSITE is multidimensional Types are defined in the IEEE and STD libraries EE Dept., SJSU 9/6/98 VHDL.26 Fundamental of VHDL Design for FPGA All rights reserved /chp

27 Scalar Data Types Enumeration type: most frequently used. Ex: type BIT is ( 0, 1 ); type logic is ( x, 0, 1, z ); Numerical: INTEGER & REAL (not supported by MaxPlusII???) Physical: used to represent some physical quantities such as time, voltage & capacitance. Ex: fs = femtosecond, ps = 1000fs, ns = 1000ps, us = 1000ns, ms = 1000us, sec = 1000ms, min = 60sec, hr = 60min EE Dept., SJSU 9/6/98 VHDL.27 Fundamental of VHDL Design for FPGA All rights reserved /chp

28 Composite Data Type Array type: Ex: type BYTE is array (0 to 7) of BIT; type BIT_VECTOR is array( NATURAL range <>) of BIT; -- <> means that user must specify this range when this type is employed Record type: Ex: type DATE is Record DAY: INTEGER range 1 to 31; MONTH: MONTH_NAME; YEAR: INTEGER range 0 to 3000; end record; The type MONTH_NAME whould be an enum type consisting of the names of the month. EE Dept., SJSU 9/6/98 VHDL.28 Fundamental of VHDL Design for FPGA All rights reserved /chp

29 Objects (1) Objects are containers of values within a model Each object has a type and class Type indicates what type of data it contains Class indicates what can be done with data There are 3 classes of objects: constant, variable and signal EE Dept., SJSU 9/6/98 VHDL.29 Fundamental of VHDL Design for FPGA All rights reserved /chp

30 Objects (2) Constant: can be of any type value does not change declared in any declarative parts Variable can be of any type value changes with assignment declared in processes, subprograms updated immedately Signal can only be of BIT types function of drivers over time declared as ports or in blocks or in architecture bodies EE Dept., SJSU 9/6/98 VHDL.30 Fundamental of VHDL Design for FPGA All rights reserved /chp

31 Constant Declaration Syntax: constant IDENTIFIER: type_indication[:=static expression] Examples constant FIVE: integer := 6; constant FIVE: bit_vector[0 to 3] := 0101 ; constant FIFTEEN: integer := 5+10; constant MESSAGE1: string := Happy Birthday ; constant HI_IMPEDANCE: tristate := Z ; constant INIT_STATE: state := S0; EE Dept., SJSU 9/6/98 VHDL.31 Fundamental of VHDL Design for FPGA All rights reserved /chp

32 Variable Declaration (1) A variable is changed by executing a variable assignment statement, e.g., A:=B+C. A variable has no time dimension & its assignment occurs immediately in simulation. It has no corresponding hardware components EE Dept., SJSU 9/6/98 VHDL.32 Fundamental of VHDL Design for FPGA All rights reserved /chp

33 Variable Declaration (2) Syntax: variable IDENTIFIER(S) : type_indication [:= static expression]; Examples variable INDEX: integer := 50; variable CYCLE_TIME: TIME := 10ns; variable MEMORY: bit_vector(0 to 7); variable MAP_COLOR: COLOR_ARRAY(5 to 7) := (VIOLET, ORANGE, BLUE); variable REG: bit_vector (15 downto 0) := X F5A2 EE Dept., SJSU 9/6/98 VHDL.33 Fundamental of VHDL Design for FPGA All rights reserved /chp

34 Signals (1) Signals connect design units together & communicate changes among them Signals model hardware & have a time dimension Signal assignment: SIGNAL_NAME <= expression; In a particular simulation cycle, a signal has a transaction if an assignment for the signal occurs EE Dept., SJSU 9/6/98 VHDL.34 Fundamental of VHDL Design for FPGA All rights reserved /chp

35 Signals (2) Syntax: signal IDENTIFIER : type_indication [:= static expression]; Examples of signal declarations signal SYS_CLK: bit := 0 ; signal BUS: bit_vector(4 downto 1) := 0101 Examples of signal assignments X1 <= 1 ; X5 <= (X1 and X2) or (X3 and X4); --OR of 2 ANDs X5 <= not ( X1 and X2 and X3); -- 3-input NAND EE Dept., SJSU 9/6/98 VHDL.35 Fundamental of VHDL Design for FPGA All rights reserved /chp

36 Lower Precedence Expressions CLASS CLASS member Logical AND, OR, NAND, NOR, XOR Relational =, /=, <, <=, >, >= Adding +, -, &(concatenation) Signing + (unary plus), - (unary minus) Multiplying/ *, /, MOD (A MOD B) has the sign of B, Dividing REM ( A REM B) has the sign of A Miscellaneous **, NOT, ABS Higher Precedence EE Dept., SJSU 9/6/98 VHDL.36 Fundamental of VHDL Design for FPGA All rights reserved /chp

37 Chapter 5 - Processes (1) PROCESS statements are the fundamental building blocks of architectural bodies They define the values of their output signals as a function of their input signals The values produced are placed, with delay, in drivers 2 types of process: implicit & explicit EE Dept., SJSU 9/6/98 VHDL.37 Fundamental of VHDL Design for FPGA All rights reserved /chp

38 Processes (2) Implicit processes are represented by signal assignments Explicit processes are concurrent, but all statements inside a process are executed sequentially A process may include a sensitivity list enumerating signals to which the process is sensitive to, e.g., any change in these signals causes the process to execute A process without a sensitivity list uses wait statements to control sensitivity Each process is invoked once at the beginning of simulation, suspending, resuming, and looping indefinitely EE Dept., SJSU 9/6/98 VHDL.38 Fundamental of VHDL Design for FPGA All rights reserved /chp

39 Processes (3) Syntax: [PROCESS_LABEL:] process [(SENSITIVITY_LIST)] type_declaration constant_declaration variable_declaration begin sequential statements end process [PROCESS_LABEL]; EE Dept., SJSU 9/6/98 VHDL.39 Fundamental of VHDL Design for FPGA All rights reserved /chp

40 Processes (4) Examples LAB1: process (A, B, XX) begin if (XX=1) then S <= A or B; elsif (XX=2) then S <= A and B; else S <= A xor B; end if; end process LAB1; STATE_EX: process( S1, S2, A, B, D) begin case (S1 + S2) is when 0 => C<= A; when 1 to INTEGER high => C <= B; when others => C <= D; end case; end process STATE_EX; EE Dept., SJSU 9/6/98 VHDL.40 Fundamental of VHDL Design for FPGA All rights reserved /chp

41 Multiple Processes (1) Processes can be independent signals a,b,c Low High Low_High *This entity Low_High contains 2 independent processes. Each process has its own variables (registers) *Process Low & High depend on the input signal a,b,c from outside of the entity but are visible to these 2 processes through the entity s ports EE Dept., SJSU 9/6/98 VHDL.41 Fundamental of VHDL Design for FPGA All rights reserved /chp

42 Multiple Processes (2) Example: A single ENTITY containing 2 independent PROCESSes. Each process has its own variables. entity LOW_HIGH is port( A, B, C: in bit_vector(0 to 3); end LOW_HIGH; architecture BEHAVIOR of LOW_HIGH is begin L: process variable LOW: bit_vector(0 to 3) := 0000 ; begin wait on A, B, C; if (A<B) then LOW:=A; else LOW:=B; end if; if (C<LOW) then LOW:=C; end if; end process; H: process variable HIGH: bit_vector(0 to 3) := 0000 ; begin wait on A, B, C; if (A>B) then HIGH:=A; else LOW:=B; end if; if (C>HIGH) then HIGH:=C; end if; end process; end BEHAVIOR; EE Dept., SJSU 9/6/98 VHDL.42 Fundamental of VHDL Design for FPGA All rights reserved /chp

43 Multiple Processes (3) The running of a process can depend on the results of other process(es) signals A,B,C L H signal D signal E K Process K depends on signal D & E from process L & H for inputs EE Dept., SJSU 9/6/98 VHDL.43 Fundamental of VHDL Design for FPGA All rights reserved /chp

45 Sequential Statements Variable assignment statement Signal assignment statement If statement Null statement Case statement Loop statement Next statement Exit statement Wait statement Procedure & function call statements EE Dept., SJSU 9/6/98 VHDL.45 Fundamental of VHDL Design for FPGA All rights reserved /chp

46 Variable Assignment The variable assignment statement assigns the value of an expression to a variable. Syntax: variable_name:=expression variable_name & expression must be of the same type The right side of the variable assignment statement is an expression using variable, signals, and literals. Example: Y := X*Z; EE Dept., SJSU 9/6/98 VHDL.46 Fundamental of VHDL Design for FPGA All rights reserved /chp

47 Signal Assignment Signal assignment can also appear within a process block Signal assignment statement as an implicit process can appear anywhere within the executable section of an architecture body Syntax: signal_name <= expression; signal_name & expression must be of the same type Example: Y <= not DATA_IN; EE Dept., SJSU 9/6/98 VHDL.47 Fundamental of VHDL Design for FPGA All rights reserved /chp

48 If Statement An IF statement allows conditional execution of sequential statements. Syntax: if CONDITION then sequence_of_statements [elsif CONDITION then sequence_of_statements] [else sequence_of_statements] end if; Example: if (DAY = 7) then WEEKEND := TRUE; elsif (DAY = 6) then WEEKEND := FALSE; end if; EE Dept., SJSU 9/6/98 VHDL.48 Fundamental of VHDL Design for FPGA All rights reserved /chp

49 Sequential vs.. Concurrent Behavior Concurrent Behavior (RS FF w/ active low S/R) architecture BEHAVE of RSFF is begin Q <= not( QB and SET); QB <= not( Q and RESET); end BEHAVE; Sequential Behavior (RS FF w/ active low S/R) architecture SEQUENTIAL of RSFF is begin process( SET, RESET) begin if (SET = 1 and RESET = 0 ) then Q <= 0 ; QB <= 1 ; elsif (SET = 0 and RESET = 1 ) then Q <= 1 ; QB <= 0 ; elsif (SET = 0 and RESET = 0 ) then Q <= 1 ; QB <= 1 ; end if; end process; end SEQUENTIAL; EE Dept., SJSU 9/6/98 VHDL.49 Fundamental of VHDL Design for FPGA All rights reserved /chp

51 Case Statement (1) Case statements provide conditional execution depending on an expression to evaluate The expression value is compared to a list of choices, and a corresponding sequence of statements is executed case EXPRESSION is when VALUE => sequence_of_statements when VALUE => sequence_of_statements end case; EE Dept., SJSU 9/6/98 VHDL.51 Fundamental of VHDL Design for FPGA All rights reserved /chp

52 Case Statement (2) Case expression must evaluate to an object of integer or enumeration (includes BOOLEAN and BIT) types Case statement options case EXPRESSION is when VALUE VALUE VALUE => statement1; statementn; when LOW_VALUE to HI_VALUE => statement1; statementn; when OTHERS => statement1; statement2; statementn; end case; means OR to or downto specifies a range OTHERS catches all remaining possible values (default) EE Dept., SJSU 9/6/98 VHDL.52 Fundamental of VHDL Design for FPGA All rights reserved /chp

53 Case Statement (3) Example case VALID_BIT is when Z Z => A := TRUE; when OTHERS => A := FALSE; end case; type BIT covers 0 and 1 EE Dept., SJSU 9/6/98 VHDL.53 Fundamental of VHDL Design for FPGA All rights reserved /chp

54 Loop statement (1) Syntax: [LOOP_LABEL] [ITERATION_SCHEME] loop sequence_of_statements end loop [LOOP_LABEL]; 3 types of loops: simple, FOR and WHILE loops EE Dept., SJSU 9/6/98 VHDL.54 Fundamental of VHDL Design for FPGA All rights reserved /chp

55 Loop statement (2) FOR loop iteration index, no need to declare iteration range for I in 1 to 10 loop squared(i) := I*I; end loop; WHILE loop variable I must be declared continuation cond. I := 1; while (I < 1) loop squared(i) := I*I; end loop; EE Dept., SJSU 9/6/98 VHDL.55 Fundamental of VHDL Design for FPGA All rights reserved /chp

56 Loop statement (3) The simple loop example L1: process( A, B ) variable X: integer := 0; variable Y: integer; begin loop X := X + 1; Y := 20; loop if (Y < (X*X)) then exit; end if; Y := Y - X; end loop; exit when ( Y > 10); end loop; end process; EE Dept., SJSU 9/6/98 VHDL.56 Fundamental of VHDL Design for FPGA All rights reserved /chp

57 Next statement This command terminates the current iteration and advances to the next iteration. Syntax: next [when condition]; for I in 0 to MAX_LIMIT loop if (DONE(I) = TRUE) then next; end if; Q(I) <= A(I); end loop; EE Dept., SJSU 9/6/98 VHDL.57 Fundamental of VHDL Design for FPGA All rights reserved /chp

58 Exit Statement An EXIT statement terminates tthe loop altogether. Syntax: exit [when condition]; for I in 0 to MAX_LIMIT loop if ( DONE(I) = TRUE ) then exit; end if; Q(I) <= A(I); end loop; EE Dept., SJSU 9/6/98 VHDL.58 Fundamental of VHDL Design for FPGA All rights reserved /chp

59 Wait Statement (1) The WAIT statement suspends a process The wait statement may include a sensitivity clause, condition clause, and/or timeout clause The wait statement causes a simulator to suspend execution of a process or a procedure, until some conditions are met EE Dept., SJSU 9/6/98 VHDL.59 Fundamental of VHDL Design for FPGA All rights reserved /chp

60 Wait Statement (2) wait on A, B; -- signals A process containing this wait statement will hang at this line until signal A or signal B changes value. If A = 1 & B = 1, the process waits until A = 0 or B = 0 wait until VALID_BIT > 0 ; -- event A process will hang at this line until signal VALID_BIT changes and the condition VALID_BIT > 0 is true. The condition is not evaluated until signal VALID_BIT changes wait for 10 ns; -- not recommended (FPGA) Suspend execution of a process at this line for 10 ns. This is not recommended because FPGA has its own HW delay process (A, B); An alternative to wait on A, B; EE Dept., SJSU 9/6/98 VHDL.60 Fundamental of VHDL Design for FPGA All rights reserved /chp

61 2 types of Subprograms: Function & Procedure Function Procedure procedure function Syntax: function MIN( A1 AN: integer) return integer; Syntax: procedure DFF( signal D: bit_vector; signal CLK, RST, PST: bit; signal Q: out bit_vector); EE Dept., SJSU 9/6/98 VHDL.61 Fundamental of VHDL Design for FPGA All rights reserved /chp

62 Chapter 7 - Attributes & Data Type Attributes are used to describe characteristics about entities with which they are associated 2 kinds of attributes: Predefined & Userdefined User-defined attributes must always be constants EE Dept., SJSU 9/6/98 VHDL.62 Fundamental of VHDL Design for FPGA All rights reserved /chp

63 Predefined Attributes The characteristics contained in the attributes are implicit Examples type T is (BLUE, RED, GRN, YELLOW); variable V1, V2, V3: T; variable V4: integer; V1 := T LEFT; --BLUE V2 := T VAL(3); --YELLOW V3 := T SUCC( RED ); -- GREEN V4 := T POS( RED ); -- 1 architecture DFF of DFF is begin process (D) begin if( CLK = 1 ) and (CLK EVENT) then Q <= D; end process; end DFF; -- EVENT is used to detect the clock rising edge, see next slide EE Dept., SJSU 9/6/98 VHDL.63 Fundamental of VHDL Design for FPGA All rights reserved /chp

64 Predefined Attributes Detecting CLK Rising Edge The change from a value X to a value 1 appears to look like a rising edge when it is actually NOT. The attribute LAST_VALUE is used to resolve this problem if (CLK = 1 ) and (CLK EVENT) and (CLK LAST_VALUE = 0 ) then Q <= D; end if; end process; end DFF; EE Dept., SJSU 9/6/98 VHDL.64 Fundamental of VHDL Design for FPGA All rights reserved /chp

65 User-Defined Attributes User-defined attributes are constants of any type They are defined by attribute declaration and an attribute specification An attribute may be associated with an Architecture, Constant, Entity, Function, Label, Package, Procedure, Signal, Type, Variable EE Dept., SJSU 9/6/98 VHDL.65 Fundamental of VHDL Design for FPGA All rights reserved /chp

66 Attribute Declaration(1) Syntax: attribute NAME: type ([index[,index]]); Examples: attribute FAN_OUT: integer; attribute REQ_ARRIVAL_TIME: time; EE Dept., SJSU 9/6/98 VHDL.66 Fundamental of VHDL Design for FPGA All rights reserved /chp

67 Attribute Declaration (2) An attribute specification assigns a value to the attribute declared by the attribute declaration The form for an attribute specification is as follows: attribute ATTR_NAME of ENTITY~NAME_LIST:ENTITY~CLASS is expression Examples signal S1, S2, S3, S4: bit_vector( 0 to 7); signal CLK, S5: BIT; attribute FAN_OUT: integer; attribute FAN_OUT of S1: signal is 4; attribute FAN_OUT of OTHERS: signal is 2; EE Dept., SJSU 9/6/98 VHDL.67 Fundamental of VHDL Design for FPGA All rights reserved /chp

68 More on Data Types Predefined types Predefined data types User-defined type Enumeration Array Record Predefined array types EE Dept., SJSU 9/6/98 VHDL.68 Fundamental of VHDL Design for FPGA All rights reserved /chp

69 Boolean Type (1) Boolean is an enum type whose values are FALSE & TRUE Constants, variables may be of type boolean Values of type boolean may appear in expressions The relational operators (=, /=, <, <=, >, >=) are predefined for operands of type boolean The logical operators (AND, OR, NAND, NOR, XOR and NOT) are predefined for operands of type boolean EE Dept., SJSU 9/6/98 VHDL.69 Fundamental of VHDL Design for FPGA All rights reserved /chp

70 Boolean Type (2) Example variable FIRST_NAME : boolean := TRUE; if FIRST_NAME then FIRST_NAME := FALSE; end if; EE Dept., SJSU 9/6/98 VHDL.70 Fundamental of VHDL Design for FPGA All rights reserved /chp

71 Integer Types (1) Values of type integer represent 32-bit integer: to Constant, variables may be of type integer The default base of integer literals is 10 The relational operators (=, /=, <, <=, >, >=) are predefined for operands of type integer The arithmetic operators (+, -, *, /, MOD, REM, **, ABS) are allowed on operands of type integer, producing integer results Examples: constant MIN: integer := 0; constant MAX: integer := 16#FF#; EE Dept., SJSU 9/6/98 VHDL.71 Fundamental of VHDL Design for FPGA All rights reserved /chp

72 BIT types BIT is an enum type whose values are X, Z, 0 and 1 Bit literal are enclosed in single quotes Constant, variables and signals may be of type BIT The relational operators (=, /=, <, <=, >, >=) are predefined for operands of type BIT The logical operators (AND, OR, NAND, NOR, XOR and NOT) are predefined for operands of type BIT Example signal OP1, OP2, RESULT: bit := 1 ; result <= OP1 AND OP2; EE Dept., SJSU 9/6/98 VHDL.72 Fundamental of VHDL Design for FPGA All rights reserved /chp

73 Character Types (1) Character is an enum type whose value are the 128 ASCII characters A character literal is single character value enclosed in single quotes: a Constant, variables may be of type character Type string is an unconstrained one dimensional array of character, indexed by integer values greater than or equal to 1 Literal string are enclosed in double quotes: Hello The relational operators (=, /=, <, <=, >, >=) are predefined for operands of type character EE Dept., SJSU 9/6/98 VHDL.73 Fundamental of VHDL Design for FPGA All rights reserved /chp

74 Character Types (2) Example -- NOTE: not synthesizable variable NEXT_CHAR: character := CR; variable line : string(1 to 21) := accumulator overflow ; constant CHAR_POSITION: integer := 21; line( CHAR_POSITION) := NEXT_CHAR; put( line ); EE Dept., SJSU 9/6/98 VHDL.74 Fundamental of VHDL Design for FPGA All rights reserved /chp

77 Enumeration Types Enumeration types are scalar types Object of an enum type defines a unique set of literal values Objects declared to be of enum types may take on the value defined by the enum literals of their type The relational operators (=, /=, <, <=, >, >=) are predefined for operands of type enum types Enum literals are identifiers or character literals Example type OP_TYPE is (OPADD, OPOR, OPAND, OPXOR); type BIT is( X, 0, 1, Z ); variable A: OP_TYPE; A := OPOR; EE Dept., SJSU 9/6/98 VHDL.77 Fundamental of VHDL Design for FPGA All rights reserved /chp

78 Array Types(1) Array types are composite types Consist of group of elements of identical type Arrays may be ordered low to high or high downto low A( 3 downto 0) = A(3) A(2) A(1) A(0) where A(3) is MSB A( 0 to 3) = A(0) A(1) A(2) A(3) where A(0) is the MSB Array s range always goes from left to right The logical operators (AND, OR, NAND, NOR, XOR, and NOT) are defined for one-dimensional arrays of BIT or BOOLEAN elements The relational operators (=, /=, <, <=, >, >=) are defined for one-dimensional array types EE Dept., SJSU 9/6/98 VHDL.78 Fundamental of VHDL Design for FPGA All rights reserved /chp

79 Array Types(2) Array type declarations are either constrained or unconstrained. A constrained type declaration defines the dimensionality and the size of every object of its type An unconstrained type declaration defines the dimensionality of objects of its type without defining their sizes EE Dept., SJSU 9/6/98 VHDL.79 Fundamental of VHDL Design for FPGA All rights reserved /chp

80 Example entity NOR8 is port( A, B: in bit_vector( 0 to 7); C: out bit_vector( 0 to 7)); end NOR8; Array Types(3) architecture BEHAV of NOR8 is type BIT_ARRAY is array(0 to 7) of bit; type DATA_MEM_TYPE is array( integer range<>) of BIT; begin process( A, B) variable DATA_MEM: DATA_MEM_TYPE( 0 to 255); begin C <= A NOR B; end process; end BEHAV; EE Dept., SJSU 9/6/98 VHDL.80 Fundamental of VHDL Design for FPGA All rights reserved /chp

81 Record Type (1) Record types are composite types Record consists of a group of elements of various types which are selected by name Only the equality expression operators (=, /=) are defined for record types EE Dept., SJSU 9/6/98 VHDL.81 Fundamental of VHDL Design for FPGA All rights reserved /chp

82 Record Type (2) Syntax: type TYPE_NAME is record element_declaration {element_declaration} end record; Hint: structure in C language Example type IO_CELL is record BUFFER_IN: bit_vector(7 downto 0); ENABLE: bit; BUFFER_OUT: bit_vector(7 downto 0); end record; signal BUSA, BUSB, BUSC: IO_CELL; signal VEC: bit_vector( 7 downto 0); BUSA.BUFFER_IN <= VEC; BUSB.BUFFER_IN <= BUSA.BUFFER_IN; BUSB.ENABLE <= 1 ; BUSC <= BUSB; EE Dept., SJSU 9/6/98 VHDL.82 Fundamental of VHDL Design for FPGA All rights reserved /chp

83 Type Conversion(1) VHDL language does not provide any builtin type conversion. Altera MaxPlusII: The std_logic_arith package in the ieee library includes three sets of functions to convert values between SIGNED and UNSIGNED types and the predefined type INTEGER. EE Dept., SJSU 9/6/98 VHDL.83 Fundamental of VHDL Design for FPGA All rights reserved /chp

84 Type Conversion(2) Four versions of each function are available; the correct version for each function call is determined through operator overloading. CONV_INTEGER--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an INTEGER value. The size of operands in CONV_INTEGER functions are limited to the range to , i.e., to a 31-bit UNSIGNED value or a 32-bit SIGNED value. CONV_UNSIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to an UNSIGNED value with SIZE bits. CONV_SIGNED--Converts a parameter of type INTEGER, UNSIGNED, SIGNED, or STD_ULOGIC to a SIGNED value with SIZE bits. EE Dept., SJSU 9/6/98 VHDL.84 Fundamental of VHDL Design for FPGA All rights reserved /chp

85 Type Conversion(3) Two operands are required for the CONV_UNSIGNED and CONV_SIGNED functions: the value to be converted and an integer that specifies the size of the converted value. If the value to be converted is smaller than the expected size, the value is extended as necessary. The MAX+PLUS II Compiler adds zeros to the MSBs for UNSIGNED values and uses sign-extension for SIGNED values. The following example shows an 8-bit adder with UNSIGNED-type inputs and an INTEGER-type output. EE Dept., SJSU 9/6/98 VHDL.85 Fundamental of VHDL Design for FPGA All rights reserved /chp

86 Type Conversion(4) Example LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY adder IS PORT (op1, op2: IN UNSIGNED(7 downto 0); result : OUT INTEGER); END adder; ARCHITECTURE maxpld OF adder IS BEGIN result <= CONV_INTEGER(op1 + op2); END maxpld; In this example, the ieee library is declared, and the std_logic_1164 and std_logic_arith packages are specified. The inputs are declared with type UNSIGNED, and the output is declared with type INTEGER. In the architecture, op1 and op2, which are both of type UNSIGNED, are added together, converted to type INTEGER with the CONV_INTEGER conversion function, and assigned to result. If this assignment was made without using the CONV_INTEGER conversion function, the MAX+PLUS II Compiler would generate an error during processing. EE Dept., SJSU 9/6/98 VHDL.86 Fundamental of VHDL Design for FPGA All rights reserved /chp

87 Arithmetic Operators Addition(+), subtraction(-), multiplication(*), division(/) and exponentiation(**) The arithmetic operators (+, -, /, MOD, REM, **, ABS) are allowed on operands of type time and integer, producing time and integer results EE Dept., SJSU 9/6/98 VHDL.87 Fundamental of VHDL Design for FPGA All rights reserved /chp

88 Concatenation Operator(FYI) Concatenation Operator(FYI) NOT supported by MaxPlusII Concatenation operator (&) accepts operands of any type Left & right operand types must match Both operands may be single elements, or both operands may be one dimensional arrays, or one operand may be a single element while the other is a one dimensional array The result is a one-dimensional array whose left part is composed of the left operand and whose right part is composed of the right operand Examples: constant B1: boolean := false; constant B2: boolean := true; constant B: arr(0 to 1) := B1&B2; --(false, true) EE Dept., SJSU 9/6/98 VHDL.88 Fundamental of VHDL Design for FPGA All rights reserved /chp

89 Relational Operators The relational operators = and /= accept operands of any type The relational operators <, <=, >, >= accept operands of any scalar type The relational operators produce boolean results. For these operators, the sizes of the operands need not match Two operands are equal if and only if they are of equal sizes and all of their elements are equal The ordering of enum values is determined by their order of appearance in their type declaration. EE Dept., SJSU 9/6/98 VHDL.89 Fundamental of VHDL Design for FPGA All rights reserved /chp

90 Logical Operators Logical Operators The logical operators (AND, OR, NAND, NOR, XOR and NOT) accept boolean or bit operands of one-dimensional arrays of these types Left & right operand types and sizes must match On array operands, the operation are performed element by element, producing array of the same size as the operands The result of these operators is of the same type as those of the operands Logical operators perform their conventional boolean functions, except when BIT values X or Z appear EE Dept., SJSU 9/6/98 VHDL.90 Fundamental of VHDL Design for FPGA All rights reserved /chp

91 Chapter 8 - Signals & Signal Assignments Local signals: used to connect the separate processes of an architecture to each other Port signals: (signals A and D) connect entity design units to the outside world (such as a simulation program and/or other components) EE Dept., SJSU 9/6/98 VHDL.91 Fundamental of VHDL Design for FPGA All rights reserved /chp

92 Local Signal EX: architecture DATA_FLOW of BOARD_DESIGN is signal A L: process signal B K: process signal D H: process N: process Signal B can come from only one process Processes K & N are dependent on signal B from process L architecture DATA_FLOW of BOARD_DESIGN is signal B: bit; -- declation of local signals EE Dept., SJSU 9/6/98 VHDL.92 Fundamental of VHDL Design for FPGA All rights reserved /chp

93 signal A L: process Port Signal signal B K: process signal D H: process N: process Signal A communicates from the ENTITY s input port to process L & H. Signal D communicates from process K to the ENTITY s output port entity BOARD_DESIGN is port( A: in bit; D: out bit); The key word IN, OUT, INOUT is required EE Dept., SJSU 9/6/98 VHDL.93 Fundamental of VHDL Design for FPGA All rights reserved /chp

94 Driver & Resolution Functions Created by signal assignment statements Multiple signal assignments produce multiple drivers for the signal Multiple drivers( e.g. bus, tristate) are resolved by use of resolution functions (vendor- or usersdefined). Altera MaxPlus II does NOT support the resolution functions architecture MULTIPLE of TEST is begin A <= B; A <= C; end TEST; EE Dept., SJSU 9/6/98 VHDL.94 Fundamental of VHDL Design for FPGA All rights reserved /chp

95 Signal Assignment in a Process Inside a process, signal assignment statements are sequential statements PROCESS Declarations (type, constant, signal, variable) Sequential statements Signal Assignments compute values & assign them to signals WAIT statements Wait for a clock signal A WAIT statement must be executed first for a signal assignment to schedule a transaction in a process without a sensitivity list. *More on next slide Procedure Calls Invoke predefined algorithms NEXT statements Skip remainder of LOOP LOOP statements Execute statements repeatedly Variable Assignments Store partial results in variables EXIT statements Terminate execution of a LOOP NULL statements Are place-holders, perform no action IF statements conditionally execute groups of sequential statements CASE statements Select a group of sequential statements to execute EE Dept., SJSU 9/6/98 VHDL.95 Fundamental of VHDL Design for FPGA All rights reserved /chp

96 WAIT Statements & Sensitivity List (1) A Wait Statement must be the first statement in a process, and it can only contain a condition clause. Examples -- Register with active-high Clock PROCESS BEGIN WAIT UNTIL clk = '1'; q1 <= d; END PROCESS; -- Register with active-low Clock PROCESS BEGIN WAIT UNTIL clk = '0'; q2 <= d; END PROCESS; ENTITY state_machine IS PORT( clk : IN BIT; input : IN BIT; output : OUT BIT); END state_machine; ARCHITECTURE a OF state_machine IS TYPE STATE_TYPE IS (s0, s1); SIGNAL state : STATE_TYPE; BEGIN PROCESS BEGIN WAIT UNTIL clk = '1'; CASE state IS WHEN s0=> state <= s1; WHEN s1=> IF input = '1' THEN state <= s0; ELSE state <= s1; END IF; END CASE; END a; END PROCESS; output <= '1' WHEN state = s1 ELSE '0'; EE Dept., SJSU 9/6/98 VHDL.96 Fundamental of VHDL Design for FPGA All rights reserved /chp

97 WAIT Statements & Sensitivity List (2) More examples (note the difference) proc1: process( A, B, C) begin X <= A and B and C; end process; proc2: process begin X <= A and B and C; wait on A, B, C; end process; Both of these processes will execute when a change in value of signal A, B or C occurs. process begin wait until (CLK = 1 ); Q <= D; end process; EE Dept., SJSU 9/6/98 VHDL.97 Fundamental of VHDL Design for FPGA All rights reserved /chp

98 Inertial vs.. Transport Delay (supported by MaxPlusII???) Inertial Delay: device delay model Transport Delay: wire delay model EE Dept., SJSU 9/6/98 VHDL.98 Fundamental of VHDL Design for FPGA All rights reserved /chp

99 Signal vs.. Variable Signal assignment: are updated only when the flow of sequential statements is interrupted with a WAIT statement Variable Assignment: are updated immediately PROCESS VARIABLE ans, verify: BIT; BEGIN verify := 1 ; signal1 <= verify; ans := signal1; WAIT; END PROCESS; variable assignment occurs immediately ans gets the old value of signal1, not the value of verify After WAIT is executed, signal1 gets verify (e.g. 1 ) EE Dept., SJSU 9/6/98 VHDL.99 Fundamental of VHDL Design for FPGA All rights reserved /chp

100 Structural Signals (port map) (1) This type of architecture contains no signal assignments An architecture of the structural type represents a schematic: An architecture declaration section declares COMPONENTs (previously compiled) The architecture is written as a netlist of the declared components EE Dept., SJSU 9/6/98 VHDL.100 Fundamental of VHDL Design for FPGA All rights reserved /chp

101 Structural Signals (port map) (2) Example (also note different coding style) ENTITY compare is PORT( a, b: in bit; c: out bit); END compare; ARCHITECTURE structural OF compare IS SIGNAL internal: bit; COMPONENT xor2 PORT( x, y: in bit; z: out bit); END COMPONENT; COMPONENT inv PORT( x: in bit; z: out bit); END COMPONENT; BEGIN END structural; COMP1: xor2 PORT MAP (a, b, internal); COMP2: inv PORT MAP (internal, c); EE Dept., SJSU 9/6/98 VHDL.101 Fundamental of VHDL Design for FPGA All rights reserved /chp

102 Chapter 9 - Concurrent Statements Concurrent Signal Assignment Conditional Concurrent Signal Assignment Selected Signal Assignment Block Statement EE Dept., SJSU 9/6/98 VHDL.102 Fundamental of VHDL Design for FPGA All rights reserved /chp

103 Concurrent Signal Assignments (1) Signal assignment statements that are outside a process are concurrent statements A concurrent signal assignment is an implicit process: Its sensitivity list is every signal on the right hand side of the <= symbol Their order is not important because all statements are not executed sequentially EE Dept., SJSU 9/6/98 VHDL.103 Fundamental of VHDL Design for FPGA All rights reserved /chp

104 Concurrent Signal Assignments (2) Type1: BOOLEAN ENTITY condsig IS PORT ( input0, input1, sel ); END condsig; output : IN BIT; : OUT BIT ARCHITECTURE maxpld OF condsig IS BEGIN END maxpld; output <= input0 WHEN sel = '0' ELSE input1; EE Dept., SJSU 9/6/98 VHDL.104 Fundamental of VHDL Design for FPGA All rights reserved /chp

105 Concurrent Signal Assignments (3) Type2: WHEN-ELSE (Conditional Concurrent Signal Assignments) ENTITY condsigm IS PORT ( high, mid, low ); END condsigm; q : IN BIT; : OUT INTEGER ARCHITECTURE maxpld OF condsigm IS BEGIN q <= 3 WHEN high = '1' ELSE -- when high 2 WHEN mid = '1' ELSE -- when mid but not high 1 WHEN low = '1' ELSE -- when low but not mid or high 0; -- when not low, mid, or high END maxpld; EE Dept., SJSU 9/6/98 VHDL.105 Fundamental of VHDL Design for FPGA All rights reserved /chp

106 Concurrent Signal Assignments (3) Type3: WITH-SELECT-WHEN (Selected Signal Assignment) library ieee; use ieee.std_logic_1164.all; entity MUX is port( A, B, C, D: in std_logic_vector( 3 downto 0); S: in std_logic_vector( 1 downto 0); X: out std_logic_vector( 3 downto 0)); end MUX; architecture ARCMUX of MUX is begin with S select X <= A when 00, B when 01, C when 10, D when others; end ARCMUX; EE Dept., SJSU 9/6/98 VHDL.106 Fundamental of VHDL Design for FPGA All rights reserved /chp

107 Block Statement SYNTAX: block_label: BLOCK [constant_declarations] [signal_declarations] [attribute_declarations] [attribute_specification] [component_declarations] [type_declarations] BEGIN [concurrent_statements] END BLOCK [block_label]; entify BLOCK_EX is port( I1, I2, CON: in BIT; O1, O2: out BIT); end BLOCK_EX; architecture EX of BLOCK_EX is begin A: block( )... B: block (CON = 1 ) begin O1 <= I1; O2 <= I2; end block B; C: block( )... end EX; EE Dept., SJSU 9/6/98 VHDL.107 Fundamental of VHDL Design for FPGA All rights reserved /chp

108 Chapter 10 - Summary What has been learned: Altera MaxPlusII FPGA tool Basics of VHDL Writing synthesizable VHDL code Ways to apply training: More self-reading material, including sample VHDL code & programs Labs, starting from basic building blocks EE Dept., SJSU 9/6/98 VHDL.108 Fundamental of VHDL Design for FPGA All rights reserved /chp

109 Where to get more information Other training classes: EE179 or industrial seminars Books, articles, electronic sources A GUIDE TO VHDL, 2nd edition, Mazor & Langstraat VHDL for PROGRAMMABLE LOGIC, Kevin Skahill, Cypress Semiconductor (comes with WARP2 for $99) STRUCTURED LOGIC DESIGN WITH VHDL, Armstrong & Gray, PTR Prentice Hall, 1993 DIGITAL SYSTEM DESIGN USING VHDL, Chin-Hwa Lee, Corral Tek WWW: good source to post question & learn (try the FAQ section) Altera MaxPlusII Help pages EE Dept., SJSU 9/6/98 VHDL.109 Fundamental of VHDL Design for FPGA All rights reserved /chp

110 Feedback Feedback are welcome Please direct your feedback to Christopher H. Pham, or (emergency only) Need more reading material? More projects? More practical projects? Too much material? Anything Let s talk :=) Have a nice VHDL time!!! Let s kick some code & have some fun!! EE Dept., SJSU 9/6/98 VHDL.110 Fundamental of VHDL Design for FPGA All rights reserved /chp

Contents. Appendix D VHDL Summary Page 1 of 23

Contents. Appendix D VHDL Summary Page 1 of 23 Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data