Σχεδιασμός Κυκλώματος Προσαύξησης στη VHDL

Transcription

1 Σχεδιασμός Κυκλώματος Προσαύξησης στη VHDL Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών Πανεπιστήμιο Κύπρου

2 Block Diagram of a 16-bit Adder A[0..15] B[ Ci n 16-bit adder S[0..15] Cou t

3 Coding a 16-bit Adder First declare 1-bit Full Adder entity and architecture entity Full_Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; S : out STD_LOGIC); end Full_Adder; architecture Behavioral of Full_Adder is Begin S <= A xor B xor Cin; Cout <= (A and B) or ((A or B) and Cin); end Behavioral; Simulate the 1-bit Full Adder and verify proper functionality

4 Coding a 16-bit adder Declare Full_Adder component and internal signals in adder16 architecture body architecture struct of adder16 is component Full_Adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; S : out STD_LOGIC); end component; signal int_cout: STD_LOGIC_VECTOR(15 downto 0);.

5 Coding a 16-bit adder Now use them to implement the 16-bit adder... adder_0: Full_Adder Port map ( A(0), B(0), Cin, int_cout(0), S(0) ); adder_1: Full_Adder Port map ( A(1), B(1), int_cout(0), int_cout(1), S(1) ); adder_15: Full_Adder Port map ( A(15), B(15), int_cout(14), int_cout(15), S(15) ); Cout <= int_cout(15); end struct;

6 Coding a 16-bit adder Alternatively, implement the adder using the generate command More efficient for adders with larger bit width... adder_0: Full_Adder Port map ( A(0), B(0), Cin, int_cout(0), S(0) ); adder_i_gen: for i in 1 to 15 generate adder_i : Full_Adder Port map ( A(i), B(i), int_cout(i-1), int_cout(i), S(i) ); end generate; Cout <= int_cout(15); end struct;

7 Simulation of the 16-bit adder

8 Block Diagram of a 16-bit register (parallel-in, parallel-out) d(0) bit0 d_latch d q q(0) clk d(1) bit1 d_latch d q q(1) d[0..15] clk clr clk 16-bit register q[0..15] d(15) bit15 d_latch d q q(15) gate clk en clk and2 a b y int_clk

9 Coding a 16-bit register First declare D-latch and and-gate entities and architectures entity d_latch is port ( d, clk : in bit; q : out bit ); end entity d_latch; architecture basic of d_latch is process (clk, d) if clk = 1 then q <= d; end if; end process; end basic; entity and2 is port ( a, b : in bit; y : out bit ); end entity and2; architecture basic of and2 is process (a, b) y <= a and b; end process ; end basic;

10 Coding a 16-bit register Declare corresponding components in register architecture body architecture struct of reg16 is... component d_latch port ( d, clk : in bit; q : out bit ); end component; component and2 port ( a, b : in bit; y : out bit ); end component; signal int_clk : bit;

11 Coding a 16-bit register Now use them to implement the register... bit0 : d_latch port map ( d(0), int_clk, q(0) ); bit1 : d_latch port map ( d(1), int_clk, q(1) ); bit2 : d_latch port map ( d(2), int_clk, q(2) ); bit15 : d_latch port map ( d(15), int_clk, q(15) ); gate : and2 port map ( en, clk, int_clk ); end struct;

12 Coding a 16-bit register Alternatively, implement the register using the generate command More efficient for larger registers... bit_i_gen: for i in 1 to 16 generate bit_i : d_latch port map ( d(i), int_clk, q(i) ); end generate; end struct;

13 Coding a 16-bit register A different approach using VHDL generics entity reg is generic (n : natural; init : STD_LOGIC); port (fx_in: in STD_LOGIC_VECTOR (n-1 downto 0); clock, enable, clear : in STD_LOGIC; fx_out : out STD_LOGIC_VECTOR (n-1 downto 0)); end reg; reg16_1 : reg generic map(16, '0') port map ( fx_in, CLK, '1', CLR, fx_out); architecture Behavioral of reg is signal sreg : STD_LOGIC_VECTOR (n-1 downto 0); process (clock) fx_out<=sreg; if clear='1' then sreg <= (others => init); elsif clock='1' and clock'event then if enable='1' then sreg<=fx_in; end if; end if; end process; end Behavioral;

14 Coding a 16-bit accumulator Declare 16-bit adder and register components in acc16 architecture body architecture struct of acc16 is... component adder16 port ( A, B : in std_logic_vector(15 downto 0); Cin : in std_logic ; S : out std_logic_vector(15 downto 0); Cout : out std_logic ); end component; component reg16 port ( d : in std_logic_vector(15 downto 0); clk, en, clear: in std_logic; q : out std_logic_vector(15 downto 0) ); end component; signal int_q, int_add, : std_logic_vector(15 downto 0);

15 Coding a 16-bit accumulator Now use them to implement the accumulator... adder16_1 : adder16 port map ( DIN, int_q, 0, int_add, open ); reg16_1 : reg16 port map ( int_add, clk, 1, CLR, int_add); DOUT <= int_q; end struct;

16 Ανακοινώσεις Η υλοποίηση του κυκλώματος προσαύξησης θα αναρτηθεί σήμερα στην ιστοσελίδα του μαθήματος Απορίες σχετικά με το εργαλείο ISE και τη γλώσσα VHDL στις ώρες γραφείου ή κατόπιν συνεννόησης