Design of Digital Systems II

Transcription

1 Design of Digital Systems II Combinational Logic Design Practices (3) Moslem Amiri, Václav Přenosil Embedded Systems Laboratory Faculty of Informatics, Masaryk University Brno, Czech Republic November, 2012

2 Exclusive-OR and Exclusive-NOR Gates An XOR gate is a 2-input gate whose output is 1 if its inputs are different X Y = X Y + X Y An XNOR gate is a 2-input gate whose output is 1 if its inputs are the same Table 1: Truth table for XOR and XNOR functions. X Y X Y (X Y ) Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

3 Exclusive-OR and Exclusive-NOR Gates ter 5 Combinational Logic Design Practices O NOT COPY O NOT COPY O NOT COPY O NOT COPY 0 igns for OR ND-OR; l NAND. (a) (a) (b) X Y X Y F = X Y F = X Y Figure 1: Multigate designs for the 2-input XOR function: (a) AND-OR; (b) three-level NAND. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

4 NOT COPY NOT COPY NOT COPY NOT COPY NOT COPY Exclusive-OR and Exclusive-NOR Gates ND-OR; NAND. (a) (b) Y Figure 2: 5-71 Equivalent Equivalent symbols symbols for (a) for (a) XOR XOR gates; (b) XNOR gates. The logic symbols for XOR and XNOR functions are shown in Figure There are four equivalent symbols for each function. All of these alternatives are a consequence of a simple rule: As seen in Fig. 2, any two signals (inputs or output) of an XOR or XNOR gate may be complemented without changing resulting logic function Any two signals (inputs or output) of an XOR or XNOR gate may be complemented without changing the resulting logic function. In bubble-to-bubble logic design, we choose the symbol that is most expressive of the logic function being performed. Four XOR gates are provided in a single 14-pin SSI IC, the 74x86 shown in Figure New SSI logic families do not offer XNOR gates, although they are readily available in FPGA and ASIC libraries and as primitives in HDLs. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

5 Parity Circuits Section 5.8 EXCLUSIVE OR Gates and Parity (a) (b) DO NOT COP DO NOT COP DO NOT COP DO NOT COP I1 I2 I3 I4 IN I1 I2 I3 I4 IM IN Figure 3: Cascading XOR gates: (a) daisy-chain connection; (b) tree structure Parity Circuits ODD ODD Figur Casca gates: conne structu Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

6 Parity Circuits Fig. 3 (a) is an odd-parity circuit Its output is 1 if an odd number of its inputs are 1 (b) is also an odd-parity circuit, but it is faster If output of either circuit is inverted, we get an even-parity circuit Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

7 Parity Circuits: The 74x280 9-Bit Parity Generator 74 Chapter 5 Combinational Logic Design Practices (a) A B C D E F G H I (8) (9) (10) (11) (12) (5) (13) (1) (2) (4) (b) 12 D E F G H I 74x280 Figure 4: The 74x280 Figure 9-bit 5-74 odd/even The 74x280 9-bit parity odd/even generator: parity generator: (a) logic(a) diagram, logic diagram, including pin numbers for a standard including pin 16-pin numbers dual for a in-line standard package; 16-pin dual (b) in-line traditional package; (b) traditional logic symbol. logic symbol. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / A B C EVEN ODD 5 6 (6) EVEN ODD

8 Parity Circuits: Parity-Checking Applications A parity bit is used in error-detecting codes to detect errors in transmission and storage of data In an even-parity code, parity bit is chosen so that total number of 1 bits in a code word is even Parity circuits like 74x280 are used both to generate correct value of parity bit when a code word is stored or transmitted, and to check parity bit when a code word is retrieved or received Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

9 Parity Circuits: Parity-Checking Applications Section 5.8 EXCLUSIVE OR Gates and Parity Circuits 375 D[0:7] RD WR x08 3 U1 74x280 D0 8 A D1 9 B D2 10 C D3 11 D4 12 D5 13 D E F EVEN ODD 5 6 D6 D7 RP G H I U2 74x PI PO D0 D1 D2 D3 D4 D5 D6 D7 74LS To store a byte into the memory chips, we specify an address (not shown), place Moslemthe Amiri, byte Václav on D[0 7], Přenosilgenerate its parity Design bit on of PIN, Digital and Systems assert II WR. The AND November, / 70 6 U1 U3 Memory Chips READ WRITE DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 PIN RD_L DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 POUT ERROR 74x541 1 G1 19 G2 DO D0 A1 Y1 DO D1 A2 Y2 DO D2 A3 Y3 DO D3 A4 Y4 DO D4 A5 Y5 DO D5 A6 Y6 DO D6 A7 Y7 DO D7 A8 Y8 U4 Figure Figure 5-75 Parity 5: Parity generation generation and checking andfor checking an 8-bit-wide formemory an 8-bit-wide system. memory.

10 Parity Circuits: Parity-Checking Applications In Fig. 5, to store a byte into memory Specify an address Place byte on D[0 7] Generate its parity bit on PIN Assert WR 280 s ODD output is connected to PIN, so that total number of 1s stored is even In Fig. 5, to retrieve a byte Specify an address Assert RD A 74x541 drives byte onto D bus, and 280 checks its parity If parity of 9-bit word is odd during a read, ERROR signal is asserted Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

11 Exclusive-OR Gates and Parity Circuits in Verilog Table 2: Dataflow-style Verilog module for a 3-input XOR device. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

12 Exclusive-OR Gates and Parity Circuits in Verilog Table 3: Behavioral Verilog program for a 9-input parity checker. 74x280 (b) A B C D EVEN E F ODD G DO (a) NOT COPY A H B I C DO D NOT COPY E F G DO H NOT COPY 374 Chapter 5 Combinational Logic Design Practices (8) (9) (10) (11) (12) (5) (13) (1) (2) (6) ODD Moslem Amiri, Václav Přenosil (4) I Design of Digital Systems II November, / EVEN

13 Exclusive-OR Gates and Parity Circuits in Verilog ASIC and FPGA libraries contain two- and three-input XOR and XNOR functions as primitives In CMOS ASICs, these primitives are realized very efficiently at transistor level using transmission gates Fast and compact XOR trees can be built using these primitives Typical Verilog synthesis tools are not smart enough to create an efficient tree structure from a behavioral program like Tab. 3 Instead, we can use a structural program to get exactly what we want Tab. 4 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

14 Exclusive-OR Gates and Parity Circuits in Verilog Table 4: Structural Verilog program for a 74x280-like parity checker. 74x280 (b) A B C D EVEN E F ODD G DO (a) NOT COPY A H B I C DO D NOT COPY E F G DO H NOT COPY EVEN I including pin numbers for a standard 16-pin dual in-line DO NOT package; (b) traditional COPY logic symbol. ODD 374 Chapter 5 Combinational Logic Design Practices 1 O NOT COPY (8) 2 (9) 4 (10) (8) A (11) (9) O B NOT (12) COPY (5) EVEN (10) (13) C (11) (1) D (2) (6) (12) (5) ODD E (4) O (13) F NOT COPY Figure 5-74 The 74x280 9-bit odd/even parity generator: (a) logic diagram, (1) G (2) (6) H (4) I Figure 5-75 shows how a parity circuit might be used to detect errors in the Moslem Amiri, Václav Přenosil Design of Digital memory Systems of a microprocessor II system. The November, memory stores bit bytes, 14 plus / 70 a

15 Comparators A comparator is a circuit that compares two binary words and indicates whether they are equal Magnitude comparators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship (greater or less than) between words Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

16 Comparators: Comparator Structure We can build an n-bit comparator using n XOR gates and an n-input OR gate Wider OR functions can be obtained by cascading individual gates A faster circuit is obtained by arranging gates in a tree-like structure Using NORs and NANDs in place of ORs makes circuit even faster Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70 XOR or XNOR gates may be viewed as 1-bit comparators Figure 6: Comparators using XOR gates: (a) 1-bit comparator; (b) 4-bit comparator.

17 Comparators: Comparator Structure Comparators can also be built using XNOR gates A 2-input XNOR gate produces a 1 output if its two inputs are equal A multibit comparator can be constructed using one XNOR gate per bit, and ANDing all of their outputs together Output of AND function is 1 if all of individual bits are pairwise equal n-bit comparators in this subsection are called parallel comparators They look at each pair of input bits simultaneously and deliver 1-bit comparison results in parallel to an n-input OR or AND function Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

18 Comparators: Iterative Circuits An iterative circuit contains n identical modules, each of which has both primary inputs and outputs and cascading inputs and outputs Left-most cascading inputs are called boundary inputs and are connected to fixed logic values Right-most cascading outputs are called boundary outputs and usually 382 Chapter 5 Combinational Logic Design Practices provide important information primary inputs PI DO 0 cascading PI NOT 1 cascading PI COPY n 1 input output PI PI PI C 0 C 1 C 2 C n 1 C n CI module CO CI module CO CI module boundary inputs PO PO 0 PO PO 1 primary outputs PO PO n 1 Figure 7: General Figure structure 5-78 General of structure an iterative of an iterative combinational circuit. boundary outputs Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

19 Comparators: Iterative Circuits Iterative circuits are suited to problems that can be solved by an iterative algorithm 1 Set C 0 to its initial value and set i to 0 2 Use C i and PI i to determine values of PO i and C i+1 3 Increment i 4 If i < n, go to step 2 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

20 Comparators: An Iterative Comparator Circuit To compare two n-bit values X and Y 1 Set EQ 0 to 1 and set i to 0 2 If EQ i is 1 and X i and Y i are equal, set EQ i+1 to 1, else set EQ i+1 to 0 3 Increment i 4 If i < n, go to step 2 Section 5.9 Comparators 383 X0 Y0 X1 Y1 X2 Y2 X(N 1) Y(N 1) (b) X Y X Y X Y X Y CMP CMP CMP CMP EQ1 EQ2 EQ3 EQ(N 1) EQN 1 EQI EQO EQI EQO EQI EQO EQI EQO X Y CMP (a) EQO EQI at Figure a time, 8: using Anmodules iterative like the comparator 74x85 4-bit comparator circuit: (a) and module 74x283 4-bit foradder, one bit; (b) complete are circuit. much more likely to be used in practical designs. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

21 Comparators: An Iterative Comparator Circuit Parallel comparators are preferred over iterative ones Iterative comparators are very slow Cascading signals need time to ripple from leftmost to rightmost module Iterative circuits that process more than one bit at a time (using modules like 74x85, discussed next) are much more likely to be used in practical designs Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

22 DO NOT C (AGTBOUT) and a less-than output (ALTBOUT) as well as an eq (AEQBOUT). The 85 also has cascading inputs (AGTBIN, ALTBIN DO NOT C for combining multiple 85s to create comparators for more than fou 74x85 is a 4-bitthe comparator cascading inputs whichand provides the outputs a greater-than are arranged in output a 1-out-of-3 co (AGTBOUT) and normal a less-than operation output exactly (ALTBOUT) one input and one as output well as should an equal be asserte output (AEQBOUT) The cascading inputs are defined so the outputs of an 85 tha 85 also hasless-significant cascading DO inputs bits (AGTBIN, are connected NOT ALTBIN, to the AEQBIN) inputs of an for 85 that Ccomp combining multiple 85s to create comparators for more than four bits 74x85 Figure ALTBIN ALTBOUT Traditional logic symbo 3 6 DO AEQBIN AEQBOUT NOT the 74x85 4-bit compar C 4 5 AGTBIN AGTBOUT 10 A0 9 B0 12 A1 11 DO B1 NOT C 13 A2 14 B2 15 A3 1 B3 Comparators: Standard MSI Magnitude Comparators Figure 9: Traditional logic symbol for the 74x85 4-bit comparator. Copyright 1999 by John F. Wakerly Copying Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

23 Comparators: Standard MSI Magnitude Comparators 384 Chapter 5 Combinational Logic Design Practices +5 V R 74x85 74x85 74x XLTY4 2 7 XLTY8 2 7 XLTY ALTBIN ALTBOUT ALTBIN ALTBOUT ALTBIN ALTBOUT DO 3 NOT 6 XEQY4 3 COPY 6 XEQY8 3 6 XEQY AEQBIN AEQBOUT AEQBIN AEQBOUT AEQBIN AEQBOUT 4 5 XGTY4 4 5 XGTY8 4 5 XGTY AGTBIN AGTBOUT AGTBIN AGTBOUT AGTBIN AGTBOUT XD0 10 XD4 10 XD8 10 A0 A0 A0 YD0 9 YD4 9 YD8 9 B0 B0 B0 XD1 12 XD5 12 XD9 12 A1 A1 A1 YD1 11 YD5 11 YD9 11 DO B1 NOT B1 COPY B1 XD2 13 XD6 13 XD10 13 A2 A2 A2 YD2 14 YD6 14 YD10 14 B2 B2 B2 XD3 15 XD7 15 XD11 15 A3 A3 A3 YD3 1 YD7 1 YD11 1 B3 B3 B3 XD[011] YD[011] Figure Figure 10: 5-81 A 12-bit A comparator using using 74x85s. 74x85s. DO significant NOT bits, as shown in Figure 5-81 COPY for a 12-bit comparator. This is an iterative circuit according to the definition in Section Each 85 develops its cascading outputs roughly according to the following pseudo-logic equations: 74x682 2 AGTBOUT = (A > B) + (A = B) AGTBIN P0 Moslem 3 Amiri, Václav Přenosil Design AEQBOUT of Digital = Systems (A = II B) AEQBIN November, / 70

24 Comparators: Standard MSI Magnitude Comparators Cascading inputs are defined so outputs of an 85 that compares less-significant bits are connected to inputs of an 85 that compares more-significant bits For each 85 AGTBOUT = (A > B) + (A = B) AGTBIN AEQBOUT = (A = B) AEQBIN ALTBOUT = (A < B) + (A = B) ALTBIN Arithmetic comparisons can be expressed using normal logic expressions, e.g., (A > B) = A3 B3 + (A3 B3) A2 B2 + (A3 B3) (A2 B2) A1 B1 + (A3 B3) (A2 B2) (A1 B1) A0 B0 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

25 Comparators: Standard MSI DO significant Magnitude Comparators NO bits, as shown ative circuit according t cascading outputs rough 74x682 2 AGTB P0 3 DO NO Q0 AEQB 4 P1 5 ALTB Q1 6 P2 The parenthesized subex 7 Q P EQ Q indicate an arithmetic c DO P3 inputs. NO 9 In other words, A Q3 11 P4 is asserted (if the higher 12 Q4 1 bits for the answer). We 13 P GT Q P5 ABEL comparator desig 14 Q5 15 expressed using normal DO P6 NO 16 Q6 (A > B) = A3 17 P7 18 (A3 Q7 (A3 Figure 11: Traditional logic Figure symbol5-82 for the 74x682 8-bit comparator. Traditional logic Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70 (A3

26 Comparators: Standard MSI Magnitude Comparators Q0 P0 Q1 P1 Q2 P2 Q3 P3 P4 (3) (2) (5) (4) (7) (6) (9) (8) Q4 (12) (11) Q5 (14) P5 (13) Q6 (16) P6 (15) Q7 (18) P7 (17) Section 5.9 Comparators 385 Copyright 1999 by John F. Wakerly Copying Prohibited Figure 12: Logic diagram for the 74x682 8-bit comparator, including pin numbers for a standard 20-pin dual in-line package. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70 (19) (1) PEQQ_L PGTQ_L

27 Comparators: Standard MSI Magnitude Comparators In Fig. 12 Top half of circuit checks two 8-bit input words for equality PEQQ L output is asserted if all eight input-bit pairs are equal Bottom half of circuit compares input words arithmetically PGTQ L is asserted if P[7 0] > Q[7 0] 74x682 does not have cascading inputs and a less than output However, any desired condition can be formulated as a function of PEQQ L and PGTQ L outputs Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

28 NOT COPY NOT COPY NOT COPY NOT COPY NOT COPY 85, the 682 does not provide a less than output. However, any desired dition, including and, can be formulated as a function of the PEQQ_L PGTQ_L outputs, as shown in Figure Comparators: Standard MSI Magnitude Comparators Figure 5-84 Arithmetic conditions derived from 74x682 outputs. 74x682 PEQQ PGTQ 19 1 U x04 74x04 74x00 74x08 2 U2 4 U2 3 U3 3 U4 PNEQ PEQQ PGTQ PGEQ PLEQ PLTQ Figure 13: Arithmetic conditions derived from 74x682 outputs. individual 1-bit comparators (XNOR gates) in the 682 are drawn in the opposite se as the examples of the preceding subsection outputs are asserted for equal Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

29 Comparators in HDLs Comparing two bit-vectors for equality or inequality is done in an HDL program, in relational expressions using operators such as == and!= Given relational expression (A==B), where A and B are bit vectors each with n elements, compiler generates the logic expression ((A 1 B 1 ) + (A 2 B 2 ) + + (A n B n )) In a PLD, this is realized as a complemented sum of 2n product terms ((A 1 B 1 + A 1 B 1) + (A 2 B 2 + A 2 B 2) + + (A n B n + A n B n )) Logic expression for (A!=B) is complement of the ones above Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

30 Comparators in HDLs Given relational expression (A<B), where A and B are bit vectors each with n elements, HDL compiler first builds n equations of the form L i = (A i (B i + L i 1 )) + (A i B i L i 1 ) for i = 1 to n, and L 0 = 0 This is an iterative definition of less-than function, starting with LSB Logic equation for (A<B) is the equation for L n After creating n equations, HDL compiler collapses them into a single equation for L n involving only A and B In case of a compiler that is targeting a PLD, final step is to derive a minimal sum-of-products expression from L n equation Collapsing an iterative circuit into a two-level sum-of-products realization creates an exponential expansion of product terms Requires 2 n 1 product terms for an n-bit comparator Results for > comparators are identical Logic expressions for >= and <= are complements of expressions for < and > Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

31 Comparators in Verilog Verilog has built-in comparison operators: >, >=, <, <=, ==,!= These operators can be applied to bit vectors Bit vectors are interpreted as unsigned numbers with the MSB on left, regardless of how they are numbered Verilog-2001 also supports signed arithmetic Verilog matches up operands of different lengths, by adding zeros on left Equality and inequality checkers are small and fast Built from n XOR or XNOR gates and an n-input AND or OR gate Checking for greater-than or less-than The number of product terms needed for an n-bit comparator grows exponentially, on order of 2 n, when comparator is realized as a two-level sum of products A two-level sum-of-products realization is possible only for small values of n (4 or less) For larger values of n, compiler may synthesize a set of smaller comparator modules, along the lines of 74x85 and 74x682 parts, whose outputs may be cascaded or combined to create larger comparison result Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

32 Comparators in Verilog DO NO DO NO DO NO The cascading inputs are defined so th 74x85 DO NO ALTBIN ALTBOUT AEQBIN AEQBOUT AGTBIN AGTBOUT A0 B0 DO NO A1 B1 A2 B2 A3 DO B3 NO are much more likely to be used in practical Standard MSI Comparators Comparator applications are common eno have been developed commercially. The 74 logic symbol shown in Figure It Table 5: Verilog module with functionality similar to 74x85 magnitude comparator. (AGTBOUT) and a less-than output (ALTB (AEQBOUT). The 85 also has cascading in for combining multiple 85s to create compa the cascading inputs and the outputs are arra normal operation exactly one input and one less-significant bits are connected to the inp Copyright 1999 by John F. Wakerly Module of Tab. 5 does not perform an explicit check for A<B, to avoid synthesizing another comparator If we missed this optimization and included A<B check, it is necessary also to include a final else statement (Tab. 6) Without final else clause, compiler will infer a latch to hold previous value of each cascading output if none of logic paths through always block assigned a value to that output Moslem Amiri, Václav Přenosil Design of Digital Systems II November, /

33 Comparators in Verilog Table 6: Verilog comparator module with three explicit comparisons. DO EQI NO DO NO DO NO DO NO The cascading inputs are defined so th 74x85 DO NO ALTBIN ALTBOUT AEQBIN AEQBOUT AGTBIN AGTBOUT A0 B0 DO NO A1 B1 A2 B2 A3 DO B3 NO at a time, using modules like the 74x85 4-bit are much more likely to be used in practical Standard MSI Comparators Comparator applications are common eno have been developed commercially. The 74 logic symbol shown in Figure It (AGTBOUT) and a less-than output (ALTB (AEQBOUT). The 85 also has cascading in for combining multiple 85s to create compa the cascading inputs and the outputs are arra normal operation exactly one input and one less-significant bits are connected to the inp Copyright 1999 by John F. Wakerly Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

34 Comparators in Verilog EQI Table 7: Verilog comparator module with cascading from more to less significant stages. DO X YNO (a) DO NO DO NO DO NO DO NO The cascading inputs are defined so th 74x85 DO NO ALTBIN ALTBOUT AEQBIN AEQBOUT AGTBIN AGTBOUT A0 B0 DO NO A1 B1 A2 B2 A3 DO B3 NO at a time, using modules like the 74x85 4-bit are much more likely to be used in practical Standard MSI Comparators Comparator applications are common eno have been developed commercially. The 74 logic symbol shown in Figure It (AGTBOUT) and a less-than output (ALTB (AEQBOUT). The 85 also has cascading in for combining multiple 85s to create compa the cascading inputs and the outputs are arra normal operation exactly one input and one less-significant bits are connected to the inp With a series of if-else statements, compiler synthesizescopyright priority 1999 logic by John F. Wakerly It checks the first condition, and only then the second, and so on We can use a case statement instead Moslem Amiri, Václav Přenosil Design of Digital Systems II November, /

35 Comparators in Verilog Table 8: Verilog comparator module using a case statement. DO EQI NO DO NO DO NO DO NO The cascading inputs are defined so th 74x85 DO NO ALTBIN ALTBOUT AEQBIN AEQBOUT AGTBIN AGTBOUT A0 B0 DO NO A1 B1 A2 B2 A3 DO B3 NO at a time, using modules like the 74x85 4-bit are much more likely to be used in practical Standard MSI Comparators Comparator applications are common eno have been developed commercially. The 74 logic symbol shown in Figure It (AGTBOUT) and a less-than output (ALTB (AEQBOUT). The 85 also has cascading in for combining multiple 85s to create compa the cascading inputs and the outputs are arra normal operation exactly one input and one less-significant bits are connected to the inp Copyright 1999 by John F. Wakerly Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

36 Comparators in Verilog Table 9: Verilog comparator module using continuous assignments. DO NO DO NO The cascading inputs are defined so th 74x85 DO NO ALTBIN ALTBOUT AEQBIN AEQBOUT AGTBIN AGTBOUT A0 B0 DO NO A1 B1 A2 B2 A3 DO B3 NO have been developed commercially. The 74 logic symbol shown in Figure It (AGTBOUT) and a less-than output (ALTB (AEQBOUT). The 85 also has cascading in for combining multiple 85s to create compa the cascading inputs and the outputs are arra normal operation exactly one input and one less-significant bits are connected to the inp Copyright 1999 by John F. Wakerly Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

37 Adders, Subtractors, and ALUs The same addition rules and therefore the same adders are used for both unsigned and two s-complement numbers An adder can perform subtraction as addition of minuend and complemented subtrahend But we can also build subtractor circuits that perform subtraction directly ALUs perform addition, subtraction, or any of several other operations according to an operation code supplied to device Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

38 Adders, Subtractors, and ALUs: Half Adders & Full Adders A half adder adds two 1-bit operands X and Y, producing a 2-bit sum HS = X Y = X Y + X Y CO = X Y (HS = half sum, and CO = carry-out) To add operands with more than one bit, we must provide for carries between bit positions Building block for this operation is called a full adder S = X Y CIN = X Y CIN + X Y CIN + X Y CIN + X Y CIN COUT = X Y + X CIN + Y CIN Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

39 Figure 5-85(a). The corresponding logic symbol is shown in (b). Sometimes the symbol is drawn as shown in (c), so that cascaded full adders can be drawn more neatly, as in the next subsection. DO NOT COP DO NOT COP DO NOT COP Adders, Subtractors, and ALUs: Half Adders & Full Adders X Y CIN (a) S COUT (b) (c) X Y CIN full adder X COUT S S COUT Y CIN Fig Full leve (b) l (c) a sym casc Figure Copyright 14: Full adder: 1999 by (a) John gate-level F. Wakerly circuit diagram; (b) logic Copying symbol; Prohibited (c) alternate logic symbol suitable for cascading. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

40 NOT COPY * NOT Subtractors COPY A binary subtraction operation analogous to binary addition was also specified A ripple in Table adder 2-3 on ispagea cascade 28. A full ofsubtractor n full-adder handles stages, one bit each of the of binary whichsubtrac- tion algorithm, one bit, having to addinput twobits n-bit X (minuend), binary words Y (subtrahend), and BIN (borrow handles NOT COPY x 3 y 3 x 2 y 2 x 1 y 1 x 0 y 0 X Y X Y X Y X Y c COUT CIN COUT CIN COUT CIN COUT CIN NOT 3 c COPY 0 S S S S s 3 s 2 s 1 s 0 Figure 15: A 4-bit ripple adder. Adders, Subtractors, and ALUs: Ripple Adders c 4 c 2 c 1 Copyright 1999 by John F. Wakerly c 0 is normally set to 0 Copying Prohibited Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

41 Adders, Subtractors, and ALUs: Ripple Adders A ripple adder is slow In worst case, a carry must propagate from least significant full adder to most significant one E.g., adding and Total worst-case delay t ADD = t XYCout + (n 2) t CinCout + t CinS t XYCout : delay from X or Y to COUT in least significant stage t CinCout : delay from CIN to COUT in middle stages t CinS : delay from CIN to S in most significant stage Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

42 Adders, Subtractors, and ALUs: Subtractors Binary subtraction is performed similar to binary addition, but using borrows (b in and b out ) between steps, and producing a difference bit d When subtracting y from x x y + b in b out = 0 x < y + b in b out = 1 d = x y b in + 2b out Table 10: Binary subtraction table. b in x y b out d Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

43 Adders, Subtractors, and ALUs: Subtractors Logic equations for a full subtractor D = X Y BIN BOUT = X Y + X BIN + Y BIN Manipulating logic equations above BOUT = X Y + X BIN + Y BIN BOUT = (X + Y ) (X + BIN ) (Y + BIN ) = X Y + X BIN + Y BIN D = X Y BIN = X Y BIN Comparing with equations for a full adder, we can build a full subtractor from a full adder Any n-bit adder circuit can be made to function as a subtractor by complementing subtrahend and treating carry-in and carry-out signals as borrows with opposite active level Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

44 Adders, Subtractors, and ALUs: Subtractors 394 Chapter 5 Combinational Logic Design Practices (a) (d) 1 2 X Y 74x COUT CIN S x n 1 y n 1 BOUT X Y X Y 74x999 b_l 74x n b_l n BOUT BIN BOUT BIN D d n (b) BIN * Carry Lookahead Adders X x n 2 y n 2 D Y X Y 74x BOUT BIN 74x04 74x04 74x D 4 d n (c) 1 2 X Y b_l 74x999 n 2 b_l b_l 0 BOUT BIN 1 D 4 x 0 y Figure 16: Subtractor design using adders: (a) full adder; (b) full subtractor; (c) interpreting 74x999 as a full subtractor; (d) ripple subtractor. Figure 5-87 Designing subtractors using adders: (a) full adder; (b) full subtractor; (c) interpreting the device in (a) as a full subtractor; (d) ripple subtractor. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70 D d

45 Adders, Subtractors, and ALUs: Carry-Lookahead Adders A faster adder than ripple can be built by obtaining each sum output s i = x i y i c i with just two levels of logic This can be accomplished by expanding c i in terms of x 0 x i 1, y 0 y i 1, and c 0 More complexity is introduced by expanding XORs Section *5.10 A We can keep XORs and design c i logic using ideas of carry lookahead DO NOT C x i hs i y i c i si x i 1 x 0 y i 1 y 0 c 0 DO NOT C Carry Lookahead Logic Figure 5 Structure o stage of a lookahead Figure Corresponding 17: Structureto ofthese one stage definitions, of a carry-lookahead we can write adder. logic equations Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

46 Adders, Subtractors, and ALUs: Carry-Lookahead Adders Adder stage i is said to generate a carry if it produces a c i+1 = 1 independent of inputs on x 0 x i 1, y 0 y i 1, and c 0 This happens when both of addend bits of that stage are 1 g i = x i y i Adder stage i is said to propagate carries if it produces a c i+1 = 1 in presence of an input combination of x 0 x i 1, y 0 y i 1, and c 0 that causes a c i = 1 This happens when at least one of addend bits of that stage is 1 p i = x i + y i Carry output of a stage can be written as c i+1 = g i + p i c i Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

47 Adders, Subtractors, and ALUs: Carry-Lookahead Adders To eliminate carry ripple, we recursively expand c i term for each stage and multiply out to obtain a two-level AND-OR expression c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) = g 1 + p 1 g 0 + p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g 1 + p 1 g 0 + p 1 p 0 c 0 ) = g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 (g 2 + p 2 g 1 + p 2 p 1 g 0 + p 2 p 1 p 0 c 0 ) = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 + p 3 p 2 p 1 p 0 c 0 Hence, Carry Lookahead Logic in Fig. 17 has three levels of delay; one for generate and propagate signals, and two for SOPs shown Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

48 Adders, Subtractors, and DO ALUs: MSI Adders NOT 74x283 The 74x283 is a 4-bit binary a few levels of logic, using th 74x83 symbol for the 74x283. The 74x283 uses carry-lookahead technique has nonstandard locations fo DO NOT The logic diagram for t 74x283 ences from the general ca 7 preceding subsection. First o C0 5 4 Y; no big deal. Second, it prod A0 S0 6 B0 and carry-propagate (p DO NOT i ) sig 3 1 A1 S1 noninverting ones. Third, it t 2 B1 manipulate the half-sum equ A2 S2 15 hs i = B A3 S3 = 11 DO B3 NOT 9 = C4 = Figure 18: Traditional logicfigure symbol for 5-89 the 74x283 4-bit binary adder. = Traditional logic symbol for the 74x283 4-bit binary adder. Thus, an AND gate with an in create each half-sum bit. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70 =

49 Adders, Subtractors, and ALUs: MSI Adders 74x283 It produces g i and p i, since inverting gates are faster Manipulating half-sum equation hs i = x i y i = x i y i + x i y i = x i y i + x i x i + x i y i + y i y i = (x i + y i ) (x i + y i ) = (x i + y i ) (x i y i ) = p i g i Thus, an AND gate with an inverted input is used instead of an XOR gate to create each half-sum bit Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

50 Adders, Subtractors, and ALUs: MSI Adders 74x283 It creates carry signals using an INVERT-OR-AND structure ( AND-OR-INVERT), which has same delay as a single inverting gate c i+1 = g i + p i c i = p i g i + p i c i = p i (g i + c i ) (p i is always 1 when g i is 1) c 1 = p 0 (g 0 + c 0 ) c 2 = p 1 (g 1 + c 1 ) = p 1 (g 1 + p 0 (g 0 + c 0 )) = p 1 (g 1 + p 0 ) (g 1 + g 0 + c 0 ) c 3 = p 2 (g 2 + c 2 ) = p 2 (g 2 + p 1 (g 1 + p 0 ) (g 1 + g 0 + c 0 )) = p 2 (g 2 + p 1 ) (g 2 + g 1 + p 0 ) (g 2 + g 1 + g 0 + c 0 ) c 4 = p 3 (g 3 + c 3 ) = p 3 (g 3 + p 2 (g 2 + p 1 ) (g 2 + g 1 + p 0 ) (g 2 + g 1 + g 0 + c 0 )) = p 3 (g 3 + p 2 ) (g 3 + g 2 + p 1 ) (g 3 + g 2 + g 1 + p 0 ) (g 3 + g 2 + g 1 + g 0 + c 0 ) Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

51 Adders, Subtractors, and ALUs: MSI Adders Section *5.10 Adders, Subtractors, and ALUs 397 (9) C4 (11) g B3 3 (12) hs 3 A3 (10) S3 p DO 3 NOT COPY c 3 (15) g B2 DO 2 (14) hs (13) NOT COPY 2 A2 S2 p 2 c 2 (2) g B1 (3) A1 (1) S1 DO 1 hs NOT COPY 1 p 1 c 1 DO (6) g NOT COPY B0 0 (5) hs 0 A0 (4) c 0 S0 p 0 c (7) 0 C0 Copyright 1999 by John F. Wakerly Copying Prohibited Figure 19: Logic diagram for the 74x283 4-bit binary adder. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

52 Adders, Subtractors, and ALUs: MSI Adders Propagation delay from C0 input to C4 output of 283 is very short, same as two inverting gates As a result, fast group-ripple adders with more than four bits can be made by cascading carry outputs and inputs of 283s Total propagation delay from C0 to C16 in Fig. 20 is same as that of eight inverting gates Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

53 Adders, Subtractors, and ALUs: MSI Adders X[15:0] Y[15:0] C0 carry outputs and inputs of 283s, as shown in Figure 5-91 for a 16-bit adder. The total propagation delay from C0 to C16 in this circuit is about the same as that of eight inverting gates. X0 Y0 X1 Y1 X2 Y2 X3 Y3 X4 Y4 X5 Y5 X6 Y6 X7 Y7 7 5 C0 A0 6 B0 3 A1 2 B1 14 A2 15 B2 12 A3 11 B3 C4 7 C0 5 A0 6 B0 3 A1 2 B1 14 A2 15 B2 12 A3 11 B3 74x283 74x283 S0 S1 S2 S3 C4 S0 S1 S2 S3 C4 Copyright 1999 by John F. Wakerly U U2 C8 S0 S1 S2 S3 S4 S5 S6 S7 X8 Y8 X9 Y9 X10 Y10 X11 Y11 X12 Y12 X13 Y13 X14 Y14 X15 Y C0 A0 6 B0 3 A1 2 B1 14 A2 15 B2 12 A3 11 B3 C12 7 C0 5 A0 6 B0 3 A1 2 B1 14 A2 15 B2 12 A3 11 B3 74x283 74x283 Figure 20: A 16-bit group-ripple adder. S0 S1 S2 S3 C4 S0 S1 S2 S3 C U U4 S8 S9 S10 S11 S12 S13 S14 S15 C16 S[15:0] Copying Prohibited Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

54 Adders, Subtractors, and ALUs: MSI ALUs An arithmetic and logic unit (ALU) is a combinational circuit that can perform any of a number of different arithmetic and logical operations on a pair of b-bit operands The operation to be performed is specified by a set of function-select inputs Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

55 Table 5-51 Functions performed by the 74x181 4-bit ALU. Inputs Function S3 DO S2 S1 S0 NOT M = 0 (arithmetic) COPY M = 1 (logic) 74x181 any of the 16 different combinational logic functions on two variables may be Adders, Subtractors, and ALUs: MSI ALUs selected. Table 11: Functions performed by the 74x181 4-bit ALU. Figure 5-92 Logic symbol for the 74x181 4-bit ALU F = A minus 1 plus CIN F = A S F = A B minus 1 plus CIN F = A + B S1 G 4 15 S2 P F = A B minus 1 plus CIN F = A + B 3 S3 Inputs Function S3 S2 S1 S0 M = 0 (arithmetic) M = 1 (logic) F DO = A minus 1 plus CINOT F = A COPY F = 1111 plus CIN F = 1111 M A=B F = A plus (A + B ) plus F = A B CIN 2 9 A0 F F = A B plus (A + B ) plus CIN F = B 1 B F = A minus B minus 1 plus CIN F = A B A1 F F = A + B plus CIN F = A B minus 1 plus CIN F = A + B F = A + B B F = A B minus 1 plus CIN F = A + B F = 1111 plus CIN F = F DO = A plus (A + B ) plus NOT CIN F = A B COPY A2 F F = A plus (A + B) plus CIN F = A B 20 B F = A plus B plus CIN F = A B A3 F F = A B plus (A + B) plus CIN F = B B F = A B plus (A + B ) plus CIN F = B COUT F = A + B plus CIN F = A + B F 1 = A1minus0B minus 0 1 plus F = CIN A plus A F plus = CIN A B F = F 1 = A 1+ B plus 0 CIN 1 F = A B plus F A = plus A + B F = A plus (A + B) plus CIN F = A CIN F = A B 1 B DO 1 1 0NOT F = A B plus A plus CIN COPY F = A B F = A plus B plus CIN F = A B F = A B 1 1 F = A plus CIN F = A plus (A + B) plus CIN F = B Copyright F = A B plus by John CIN F. Wakerly F = A + B Copying Prohibited F = A plus A plus CIN F = F = A B plus A plus CIN F = A B F = A B plus A plus CIN F = A B F = A plus CIN F = A Figure 21: Logic symbol for the 74x181 4-bit ALU. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

56 O NOT COPY Adders, Subtractors, and ALUs: MSI ALUs O NOT COPY O NOT COPY O NOT COPY 93 ls for 4-bit x381; useful functions, as detailed in Table The only difference between the 3 and 382 is that one provides group-carry lookahead outputs (which we expla next), while the other provides ripple carry and overflow outputs. (a) 74x381 (b) 74x382 5 S0 6 S G S P CIN 3 A0 F B0 A1 F1 9 2 B1 19 A2 F B2 A3 B3 F S0 S1 S2 OVR CIN COUT 14 3 A0 F B0 A1 F1 9 2 B1 19 A2 F B2 A3 B3 F3 12 Figure Copyright 22: Logic 1999 symbols by John forf. 4-bit Wakerly ALUs: (a) 74x381; (b) 74x382. Copying Prohibite Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

57 Adders, Subtractors, and ALUs: MSI ALUs Table 12: Functions performed by the 74x381 and 74x382 4-bit ALUs. Inputs S2 S1 S0 Function F = F = B minus A minus 1 plus CIN F = A minus B minus 1 plus CIN F = A plus B plus CIN F = A B F = A + B F = A B F = 1111 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

58 Adders, Subtractors, and ALUs: MSI ALUs 381 provides group-carry-lookahead outputs while 382 provides ripple carry and overflow outputs Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

59 Adders, Subtractors, and ALUs: Group-Carry Lookahead 181 and 381 provide group-carry-lookahead outputs that allow multiple ALUs to be cascaded without rippling carries between 4-bit groups Like 74x283, ALUs use carry lookahead to produce carries internally However, they also provide G L and P L outputs that are carry-lookahead signals for entire 4-bit group G L output is asserted if ALU produces a carry-out whether or not there is a carry-in G L = (g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 ) P L output is asserted if ALU produces a carry-out if there is a carry-in P L = (p 3 p 2 p 1 p 0 ) Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

60 Adders, Subtractors, and ALUs: Group-Carry Lookahead COPY When ALUs are cascaded, group-carry-lookahead outputs may be combined in just two levels of logic to produce carry input to each lookahead carry circuit ALU A lookahead carry circuit 74x182 performs this operation COPY 74x C0 3 using four 381s and a G C1 P0 COPY 1 G C2 P1 14 G C3 P G3 G COPY 6 7 P3 P Figure 23: Logic symbol Figure for the x182 lookahead carry circuit. Logic symbol for the 74x182 lookahead kahead outputs may be ry input to each ALU. A -94, performs this operae least significant ALU opagate outputs of ALUs s C1 C3 for ALUs 1 3. ing out the basic carry following equations: Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

61 Adders, Subtractors, and ALUs: Group-Carry Lookahead 402 Chapter 5 Combinational Logic Design Practices 74x C0 3 G C4 P0 C1 1 G C8 P1 C2 14 G C12 P2 C G3 G GALL_L 6 7 P3 P PALL_L U5 C0 DO S[2:0] NOT COPY A[15:0] B[15:0] 74x381 74x381 S0 5 S0 5 S0 S0 S1 6 S1 6 DO NOT S1 COPY S1 S G0_L S G2_L S2 G S2 G P0_L P2_L CIN P CIN P A0 3 A8 3 A0 8 F0 A0 8 F8 B0 4 F0 B8 4 F0 B0 B0 A1 1 A9 1 A1 9 F1 A1 9 F9 B1 2 F1 B9 2 F1 DO NOT B1 COPY B1 A2 19 A10 19 A2 11 F2 A2 11 F10 B2 18 F2 B10 18 F2 B2 B2 A3 17 A11 17 A3 12 F3 A3 12 F11 B3 16 F3 B11 16 F3 DO NOT B3 U1 COPY B3 U3 ALU0 ALU2 74x381 74x381 S0 5 S0 5 S0 S0 S1 6 S1 6 S1 S1 S G1_L S G3_L S2 G S2 G DO 15 NOT 14 P1_L COPY P3_L CIN P CIN P A4 3 A12 3 A0 8 F4 A0 8 F12 B4 4 F0 B12 4 F0 B0 B0 A5 1 A13 1 A1 9 F5 A1 9 F13 B5 2 F1 B13 2 F1 B1 B1 A6 19 A14 19 DO NOT A2 11 F6 COPY A2 11 F14 B6 18 F2 B14 18 F2 B2 B2 A7 17 A15 17 A3 12 F7 A3 12 F15 B7 16 F3 B15 16 F3 B3 B3 U2 U4 ALU1 ALU3 F[15:0] Figure 24: A 16-bit Copyright 1999 ALU by John using F. Wakerly group-carry Copying lookahead. Prohibited Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

62 Adders, Subtractors, and ALUs: Group-Carry Lookahead 182 s carry equations 182 realizes each of these equations with one level of delay an INVERT-OR-AND gate c i+1 = g i + p i c i = (g i + p i ) (g i + c i ) C1 = (G0 + P0) (G0 + C0) C2 = (G1 + P1) (G1 + G0 + P0) (G1 + G0 + C0) C3 = (G2 + P2) (G2 + G1 + P1) (G2 + G1 + G0 + P0) (G2 + G1 + G0 + C0) Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

63 Adders, Subtractors, and ALUs: Group-Carry Lookahead When more than four ALUs are cascaded, they may be partitioned into supergroups, each with its own 182 E.g., a 64-bit adder would have four supergroups, each containing four ALUs and a 182 G L and P L outputs of each 182 can be combined in a next-level 182, since they indicate whether the supergroup generates or propagates carries G L = ((G3 + P3) (G3 + G2 + P2) (G3 + G2 + G1 + P1) (G3 + G2 + G1 + G0)) P L = (P0 P1 P2 P3) Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

64 Adders, Subtractors, and ALUs: Adders in Verilog Verilog has built-in addition (+) and subtraction ( ) operators for bit vectors Bit vectors are considered to be unsigned or two s-complement signed numbers Actual addition or subtraction operation is exactly the same for either interpretation of bit vectors Since exactly the same logic circuit is synthesized for either interpretation, Verilog compiler does not need to know how we are interpreting bit vectors Only handling of carry, borrow, and overflow conditions differs by interpretation, and that is done separately from addition or subtraction itself Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

65 Adders, Subtractors, and ALUs: Adders in Verilog Table 13: Verilog program with addition of both signed and unsigned numbers. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

66 Adders, Subtractors, and ALUs: Adders in Verilog Figure 25: Two ways to synthesize a selectable addition: (a) two adders and a selectable sum; (b) one adder with selectable inputs. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

67 Adders, Subtractors, and ALUs: Adders in Verilog Addition and subtraction are expensive in terms of number of gates required Most Verilog compilers attempt to reuse adder blocks whenever possible Tab. 14 is a Verilog module that includes two different additions Fig. 25(a) shows a circuit that might be synthesized However, many compilers are smart enough to use approach (b) An n-bit 2-input multiplexer is smaller than an n-bit adder Table 14: Verilog module that allows adder sharing. Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

68 Adders, Subtractors, and ALUs: Adders in Verilog Table 15: Alternate version of Tab. 14, using a continuous-assignment statement. A typical compiler should synthesize the same circuit for either module of Tab. 14 or 15 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

69 different. Refer to a 181 data sheet for more de Table 16: An 8-bit 74x381-like ALUḌO NOT C Two other MSI ALUs, the 74x381 and 74x382 encode their select inputs more compactly, and useful functions, as detailed in Table The and 382 is that one provides group-carry look DO next), NOT while the other provides ripple Ccarry and (a) 74x381 (b) Figure Logic symbols for 4-bit S0 S0 6 6 ALUs: (a) 74x381; S1 13 S1 (b) DO 74x382. NOT 7 G S S2 15 P 15 CIN C A0 F0 A0 4 4 B0 B A1 F1 A1 DO NOT 2 B1 C2 B A2 F2 A B2 B A3 F3 A B3 B3 74x381 Adders, Subtractors, and ALUs: Adders in Verilog Copyright 1999 by John F. Wakerly Inputs S2 S1 S0 Function F = F = B minus A minus 1 plus CIN F = A minus B minus 1 plus CIN F = A plus B plus CIN F = A B F = A + B F = A B F = 1111 Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70

70 References John F. Wakerly, Digital Design: Principles and Practices (4th Edition), Prentice Hall, Moslem Amiri, Václav Přenosil Design of Digital Systems II November, / 70