Shift Invert Coding (SINV) for Low Power VLSI

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Shift Invert oding (SINV) for Low Power VLSI Jayapreetha Natesan* and Damu Radhakrishnan State University of New York Department of Electrical and omputer Engineering New Paltz, NY, U.S. email: natesa76@newpaltz.

1 Shift Invert oding (SINV) for Low Power VLSI Jayapreetha Natesan* and Damu Radhakrishnan State University of New York Department of Electrical and omputer Engineering New Paltz, NY, U.S. bstract Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a MOS circuit is to reduce the number of on the bus and Bus Invert oding is a widely popular technique for that. In this paper we introduce a new way of coding called the ShiftInv oding that is superior to the bus invert coding technique. Our simulation results show a considerable reduction on the number of over and above that obtained with bus invert coding. Further, the proposed technique requires only 2 extra bits for the low power coding, regardless of the bit-width of the bus and does not assume anything about the nature of the data.. Introduction With ever increasing complexity of VLSI circuits and an increased focus on mobile computing, low power design techniques have become a must for all aspects of digital design. Over the past few years, a number of coding schemes have been proposed for reducing the on a bus. For data buses, one popular coding scheme is the bus invert coding technique []. This is a suitable technique for uncorrelated data patterns. probability based mapping technique is proposed by Ramprasad et.al [2] for patterns with non-uniform probability densities. For instruction address buses, Gray code [3], T code [4], the Beach code [5] and inc-xor [2] code have been proposed. Other variants of the bus invert coding include a partial bus coding technique [7] and the decomposition approach [6]. Both these techniques have an area overhead to determine the suitable partition of the data bus. In addition, the decomposition approach [6] can require up to p- extra lines on the bus where p is the number of partitions of the original data bus. The partial bus invert coding [7] has the limitation that in-spite of the additional hardware, it might not utilize the *uthor currently with IBM, NY bus invert coding for a subset of the bus lines, there by producing sub-optimal results. Further, the partial bus invert coding requires that one has the information apriori of the sequence of the memory address patterns on the bus. In this work, we propose a simple yet efficient improvement to the Bus Invert oding technique. The proposed technique does not have any additional area overhead in determining the transition correlations and transition probabilities. It does not need any prior knowledge of the address patterns. The data on the bus can be uncorrelated and completely random, just as was the case with the original bus invert coding. The number of extra bus lines needed by this method is always 2, regardless of the bit-width of the bus. This paper is organized as follows. We first propose the terminology used in this paper in Section 2. The basics of Bus Invert oding appear in Section 3 followed by details of the proposed technique ShiftInv oding in Section 4. Section 5 details a hardware implementation for the proposed technique. The simulation results for a number of test cases are presented in Section 6 followed by conclusions and suggestions for future work in Section Terminology The following terminology is used in this paper. Let D = d w-, d w-2 d represent a binary data string of width w. The data string at any time instant k can be represented as, D k = d w- k, d w-2 k, d k. Let B k be the data transmitted on the bus at time k. Note that the bit width w of the bus (i.e., the encoded data that gets transmitted on the bus) could be greater than w depending on the coding scheme used. For instance, in default Bus Invert oding [], w = w +. For variations of Bus Invert oding, w can be greater than w+. In any coding scheme based on bus inversion, the value of the i th bit, b i on the bus will be either the data value d i or -d i. Thus, for all i, <= i <w, b i = d i, uninverted bit OR b i = - d i, inverted bit.

2 3. Bus Invert oding The basic idea behind Bus Invert oding [] originated by noting that a lot of power is wasted during data transmission in off-chip bus lines. This is due to the switching of the high capacitance lines, Therefore power could be saved by minimizing the number of occurring on these bus lines. Let N be the number of between the data D k+ at time k+ and the value on the bus B k, i.e., N represents the total number of bit-positions in which the new data and the existing value on the bus differ. Let D k+(inv) be the inverted (INV) data. i.e., for all i, <= i <w, d i = -d i. Let N INV be the number of between D k+(inv) and B k. The Bus Invert oding technique chooses either D k+ or D k+(inv) to be transmitted on the bus. If N <= N INV, then D k+ is transmitted on the bus; otherwise, the inverted data D k+(inv) is sent on the bus. Recently, a number of techniques have been proposed for bus encoding. Most of these techniques either center on the original bus-invert coding scheme or assume some special data conditions. In this paper, we do not assume any special conditions for the data on the bus. We assume the data to be completely random. We propose a technique that further enhances the default Bus Invert oding scheme. 4. Shifting oding The main idea in the proposed technique is to optionally shift the data bits by one bit position (either left-shift or right-shift) if the shifting reduces the number of bus. We define the left- shift operation on a w-bit data as follows. d (LS) i = d i-, d (LS) = d w -. <= i < w, i.e., we perform a circular left-shift. This will guarantee that we do not lose any information from the original data. The right-shift operation is defined similar to the left-shift, as follows. d (RS) i = d i+, d (RS) w - = d. <= i <w -, Example 4. onsider the following example. (ignore the extra bits used in the encoding scheme for a moment) Let B k = (assume a 8-bit bus), and, the new data at time k+, D k+ = ; therefore, the inverted data D k+(inv) = For this example, the number of N between B k and D k+ is 5. In the case of Bus Invert oding, we would try to see whether it is beneficial (i.e., whether the number of to and to are reduced) to send D k+(inv) over the bus. The number of N INV between B k and D k+(inv) is 3. Since N INV < N, in the Bus Invert oding technique, D k+(inv) will be sent over the bus at time k+. Now, let us see what happens when we left-shift the data D k+ once, as defined above. We denote the left-shifted data at time k+ as D k+(ls). We see that, D k+(ls) =. omparing to, B k =, the number of N LS between B k and D k+(ls) is just, which is better than the 3 that one gets from the inverted data D k+(inv). Thus, in this case, it is clear that by sending the left-shifted data, we can reduce the number of even further than the reduction obtained from sending the inverted data. The rationale behind using the shift operation is simple. By shifting the data at time k+, it is possible that the bit values could match in more places with the existing data on the bus at time k than if the data bits were either inverted or left unchanged. The matching of bits in more places implies fewer, thereby giving a better solution. The above example illustrates how a left-shift operation is better than inversion. Similarly, one can construct examples to show how a right-shift operation on the data reduces the number of. Thus, we conclude that one can further reduce the number of either by performing a leftshift or a right-shift operation.

3 It is obvious that shifting left or right will not always reduce the number of. Depending on the values of B k and D k+, it is possible that either the inverted data D k+(inv) or may be even the unmodified/original data D k+ gives the least when sent on the bus. For each new data that needs to be sent over the bus, we evaluate the N, N INV, N LS and N RS between B k and D k+, D k+(inv), D k+(ls), and D k+(rs) respectively. We then choose the encoding that results in the least number of. The steps of the proposed technique can be outlined as below. Procedure ShiftInv() { Input : D k+, B k Output: B K+(SHIFT_INV) } N num_(d k+, B k ) N INV num_(d k+(inv), B k ) N LS num_(d k+(ls), B k ) N RS num_(d k+(rs), B k ) B K+ one of (D k+, D k+(inv), D k+(ls), D k+(rs) ) depending on min(n,n INV,N LS, N RS ) The procedure num_(d,b) returns the number of bit-positions in which the passed in vectors D and B differ. Note that the data that gets sent over the bus, B k+ can be one of D k+, D k+(inv), D k+(ls), D k+(rs). Thus, we need to tag the bus with 2 additional bits that indicate the coding that was used. This will be used to decode the bus value appropriately at the receiving end. Thus, in ShiftInv coding, the width of the bus w = w + 2, where w is the width of the data vector and we use 2 additional bits as compared to additional bit in default Bus Invert oding[]. 5. Hardware Model Figure shows one way of hardware realization for the proposed ShiftInv coding. The inputs to the encoder are D k+ and B k where k denotes the time instance k. For illustration purposes, we show a block-diagram of ShiftInv coding for an 8-bit data. Thus, the bit width of D k+ is 8 and the bit width of B k is since it includes the two control signals ( ) used to indicate the mode of encoding (explained below). The blocks named Pass Through, Left_Shift, Right_Shift and Invert indicate the 4 encoding schemes used in our proposed technique. Each of these blocks has XOR gates. The basic functionality of an XOR gate is to produce an output of whenever the inputs differ thus the XOR gate basically captures the transition between B k and D k+. Pass- Through LK D D k+ D - D Invert D 6 D D Left-Shift O M P R T O R B k Right-Shift Figure. Hardware Model for SHIFTINV oding for 8-bit Data The block Pass Through compares the un-encoded (default) data bits D k+ with the existing value on the bus, B k. The blocks Left-Shift and Right-Shift respectively compare the circular left-shifted and right-shifted data bits with the bus contents B k. Note that the left-shift and right-shift blocks do not require any additional hardware. They can be realized by a mere re-adjustment of the data bits D k+. The block termed Invert is used to get the of the bit inverted original input bits. The inverter shown to the left of the Invert block is an 8-bit inverter. Each of the XOR blocks take 2 -bit inputs and generate one -bit output. One of the 2 -bit inputs is the signal B k on the bus at time instant k. s mentioned earlier, the signal Bk includes the 2 control bits ( ) used to indicate the scheme used at time instant k. The other input to the XOR blocks is the 8-bit data signal D k+ - in some encoded form (depending on the encoding scheme). Note that the bit width of D k+ is only 8, and the other 2 bits would come based on the encoding scheme used at instant k+. Table shows a bit representation to indicate the coding scheme used. For example, if the input data is left-shifted before we send it over the bus, the two control bits will be assigned the value. Likewise, the other bit assignments can be obtained from the table. B D Table. Bit representation for SHIFTINV coding Default (no encoding) Left-Shift Right-Shift Invert B D M U X LK BUS B k+

4 The output bits of each of the XOR ed -bit output are then added using a counter structure -termed in Figure. The block is the hardware version of procedure num_() that is used in procedure ShiftInv() in section 4. The total number of s in the XOR output indicates the number of positions in which the two input vectors differ. The block takes bits as input and generates a 4-bit output that indicates the total number of s in the input. The block can be realized as shown in Figure 2. The will generate an output that can be anywhere in the range [..]. This implies that :4 DDER- will generate a 4-bit output. These 4- bits indicate the total number of on the bus for each type of encoding. Note that in this example, the data bus is assumed to be 8-bits wide and we used an DDER- block that took input bits and generated a 4- bit output. In general, for a w-bit data, we will need a (w+2)- bit DDER- block that generates a [log 2 (w + 2)] bit output. Referring to Figure, the outputs from the four :4 DDER- blocks are sent to a 4-way 4-bit comparator which finds the mode that has the least number of. The comparator then generates the two control bits that indicate the mode chosen for decoding at time instant k+. The encoded data that has the least number of and the control bits are then sent over the bus as B k+. 6. Simulation Results We implemented the proposed ShiftInv coding technique in ++ code. s mentioned earlier, no assumptions on the nature of data on the bus were made. ompletely random values for the data bus D k were generated. The bit-width and the time for simulation were passed as inputs to the ++ program. We also simulated the Bus Invert oding using the same randomly generated data so as to compare the performance of ShiftInv oding with respect to the Bus Invert oding. Table 2 summarizes the results for buses whose widths are a power of 2. For each bit-width pattern, simulation cycles were performed. Bit-width Table 2. Simulation Results for buses with width 2 n (n = 3,4,5,6,7) (default no coding) DEF (BusInv BI Transitions (ShiftInv SINV H It can be seen that in all cases, the ShiftInv coding reduces the average number of bus per simulation cycle considerably from the default (unencoded) scheme. Further more when compared with Bus Invert oding, the ShiftInv coding is clearly the winner. The additional savings is achieved by using just one extra line as compared with default Bus Invert oding achieved by using just one extra line as compared with default Bus Invert oding. H Figure 2. circuit

5 Table 3. Simulation Results for buses with arbitrary width Bit width (default no coding) DEF Table 3. shows the simulation results for buses whose widths are not a power of 2. It is interesting to see that the transition reductions are greater for the buses with arbitrary bus widths than buses whose widths are a power of 2. We believe that the additional savings suggest that the shift operations are inherently well suited for encoding buses with arbitrary widths, which is generally the case for data buses, especially for the on-chip data buses. We can see from the tables as the bus-width increases, the ShiftInv coding results in a larger reduction in the average number of. Thus, as applications go towards 64-bits and beyond, the ShiftInv coding scheme will be more useful than the traditional Bus Invert oding. It should also be noted that the number of extra lines for the ShiftInv coding remains at 2 irrespective of the width of the data bus. We claim that the reduction in the power savings obtained by ShiftInv oding can more than offset this small increase in the hardware requirements. 7. onclusion and Results (BusInv BI Transitions (ShiftInv SINV We presented a new method for bus encoding using left-shift and right-shift operations. This technique is a simple yet efficient scheme that enhances the Bus Invert oding technique. On completely random data, the simulation results suggest that the proposed ShiftInv coding reduces the average number of over and above that given by the wellknown Bus Invert oding technique. The proposed coding scheme does not have too much area overhead and it does not assume any correlation between the data values. Further, the proposed technique uses only 2 extra lines regardless of the width of the data bus. The ShiftInv coding scheme is also better suited for buses with arbitrary widths. In future, we plan to investigate the merits of this technique by generating other coding schemes resulting from a combination of the shift and invert operations. lso, we plan to investigate special purpose applications for which one may get even more savings using ShiftInv oding. s we are in the deep sub-micron era, the inter-wire parasitic capacitance is a dominant factor for the energy dissipation in circuits [8]. In future we plan to look at the energy minimization based ShiftInv coding that will reduce the total bus energy and not just the number of bus. From the experimental data in Table 2 and Table 3, we see that the savings are more for smaller bus-widths and less for larger bus-widths. This is an expected behavior since the proposed ShiftInv coding is an extension of the Bus Invert oding and the Bus Invert oding method [] does not perform well for larger bus widths. s part of our future work, we plan to explore the possibility of applying the Shift techniques to other types of coding such as the source-coding framework [2]. 8. References [] M. R. Stan and W. P. Burleson, Bus-Invert coding for lowpower I/O, IEEE Trans. on VLSI, March 995, vol. 3, pp [2] S. Ramprasad, N. R. Shanbag, and I. N. Hajj, coding framework for low power address and data busses, IEEE Trans. on VLSI Systems, June 999, vol. 7, pp [3]. L. Su,. Y. Tsui, and. M. Despain, Saving power in the control path of embedded processors, IEEE Design and Test of omputers, 994, vol.., no. 4, pp [4] L. Benini, G. De Micheli, E. Macii, D. Sciuto, and. Silvano, symptotic zero-transition activity encoding for address buses in low-power microprocessor-based systems, Great Lakes VLSI Symposium, Urbana IL, March 997, pp [5] L. Benini, G. De Micheli, E. Macii, M. Poncino, and S. Quer, System-level power optimization of special purpose applications: The beach solution, Proc. Int. Symp. Low Power Electronics Design, ugust 997, pp [6] S. Hong, U. Narayanan, K.S. hung, and T. Kim, Bus-Invert oding for Low-Power I/O Decomposition pproach, Proc. 43 rd IEEE Midwest Symp. ircuits and Systems, ugust 2. [7] Y. Shin, S.I. hae and K. hoi, Partial Bus-Invert oding for Power Optimization of pplication-specific Systems, IEEE Trans. on VLSI Systems, pril 2, vol. 9, pp [8] P. P. Sotiriadis and. handrakasan, Bus energy minimization by transition pattern coding (TP) in deep submicron technologies, Proc. 2 IEEE/M Int. onf. omputer-ided Design, November 2, pp

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