Low Power PLAs. Reginaldo Tavares, Michel Berkelaar, Jochen Jess. Information and Communication Systems Section, Eindhoven University of Technology,

Transcription

1 Low Power PLAs Reginaldo Tavares, Michel Berkelaar, Jochen Jess Information and Communication Systems Section, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, The Netherlands 1 Introduction Several applications that use integrated circuits (ICs) need lower power dissipation. Because of this, designers have looked for power down strategies in order to reduce the power dissipated by ICs. In this paper we propose a technique to design static programmable logic arrays (PLAs) with lower power dissipation. PLAs were intensively used in the past, but because of the CMOS technologies and the new design methodologies, they were replaced by multi level circuits [1][4]. Although the number of PLA designs has decreased, they still are being used in circuit design as we can see, for example, in [5]. PLAs are a direct two level logic circuit implementation. Two level logic optimization algorithms are available, for example, the program Espresso is considered the standard two level minimizer [2]. PLAs can be easily implemented, the area and delay can be well predictable, they can have very regular layout, even when a sparse Boolean functions is implemented. All of these features are important for deep submicron designs. However, CMOS is the current mainstream design methodology, partly because of its lower power consumption. A method to reduce the power dissipated by PLAs is presented in [3]. This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However, [3] concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power dissipated by static PLAs. The circuit technique that we present tries to decrease the static power dissipation. The idea is to introduce a small modification on the structure of the circuit without adding large modifications on the structure of conventional PLA circuits. 2 PLA Circuit A PLA circuit is a combination of two different planes, the INPUT and OUTPUT planes. The planes are also called AND OR planes respectively. The AND plane implements all product terms of the function. The OR plane combines all products of the respective output function. For high speed, the AND OR planes can be replaced by an equivalent NOR NOR logic structure. Appropriate inverters at the input and output nodes are necessary to complete this transformation. Figure 1 shows the block diagram of a PLA. 1

2 AND PLANE OR PLANE inputs outputs Figure 1 PLA block diagram PLAs can be designed in three different basic circuit structures: static, dynamic and hybrid [4]. The static version is based on pseudo NMOS NOR gates. This is the most common PLA design. This PLA is simple and can have a small size. However, the static power dissipation of the pseudo NMOS NOR gates is the most important contribution to the total power dissipated. Figure 2 shows a pseudo NMOS PLA implementation of the functions: out1 = in1 in2 in3 and out2 = in1 in2 in3 + in4 in5. out2 in5 in4 out1 in3 in2 in1 Figure 2 Pseudo NMOS PLA 2

3 Figure 3 shows a dynamic PLA implementation. The static power dissipation in dynamic PLAs can be cut down, but the circuit is more complex due to the control signals necessary to precharge and discharge all OR nodes in both planes. More transistors per product terms and outputs are necessary to discharge the OR nodes. It increases area and the number of capacitances switched for each new value of the clock signal. The clock signal is attached to input and output latches. precharge OR precharge AND out2 in5 in4 discharge OR discharge AND precharge OR precharge AND out1 in3 in2 discharge OR in1 discharge AND Figure 3 Dynamic PLA The hybrid PLA shown in figure 4 is implemented by both the pseudo NMOS and dynamic structures. These PLAs use a single clock to precharge both planes. However, parasitic capacitances are switched for each new value of the clock signal. The power dissipated due to capacitances attached to the clock signal is a significant contribution of the total power dissipated. For low power purposes, many capacitances switch at new clock cycle in dynamic and hybrid PLAs design. On the other hand, the static power dissipation of the pseudo NMOS PLAs is undesirable. 3

4 clk out2 clk in5 in4 clk out1 clk in3 in2 in1 2.1 Pseudo NMOS NOR Gates Figure 4 Hybrid dynamic pseudo NMOS PLA A pseudo NMOS NOR gate has n NMOS transistors connected to n inputs and only a single pull up transistor. In CMOS technologies the pull up is implemented by a PMOS transistor. The pull up is always turned on. If all inputs are 0, the NOR gate evaluates to 1. If at least one input is 1 the gate evaluates to 0. A pseudo NMOS NOR gate, in general, is smaller and can be faster than an equivalent CMOS NOR gate. Unfortunately, it dissipates static power. Figure 5a shows a 3 input pseudo NMOS NOR gate. The static power dissipation of a pseudo NMOS NOR gate can be decreased if the pull up transistor is turned off when the gate evaluates to 0. In this case, the pull up transistor has to be controlled. One way to control the pull up transistor is to attach to its gate terminal a logic input. Figure 5b shows the pseudo NMOS NOR gate modified. This modified gate has been used in power down and speed strategies as we can see in [6]. 4

5 a b c out a b c out a) Pseudo NMOS NOR gate b) Modified pseudo NMOS NOR gate Figure 5 Pseudo NMOS and the modified pseudo NMOS NOR gate The modified pseudo NMOS NOR gate differs slightly from the pseudo NMOS NOR gate. If the input attached to the gate of the pull up transistor is high, no current can flow between Vdd and Ground sources. The current cannot flow for all possible input vectors where this input is also high. But if the input connected to the pull up transistor makes a transition from high to low level, the pull up will conduct again. If there is another input high, a current can flow between Vdd and Ground sources. Table 1 is the truth table of a 3 input NOR gate. The Columns p NMOS and Mp NMOS show for which inputs vector there is a short circuit current for the pseudo and the modified pseudo NMOS NOR gates respectively. We can see from table 1 that the modified pseudo NMOS gate does not avoid the short circuit current in all cases. However, the overall static power dissipation can be decreased, and it is dependent on the input vector. The modified pseudo NMOS NOR gate can have less static power dissipation than an equivalent pseudo NMOS and less input capacitance than an equivalent CMOS NOR gate. Table 1 Short circuit current per input vector a b c out p NMOS Mp NMOS x x x x x x x x x x Any Boolean function can be implemented by pseudo NMOS NOR gates. In fact, they have been much used to implement static PLAs. But, in order to improve the power efficiency of the static PLAs, the modified pseudo NMOS NOR gate could be used to reduce the static power dissipation. 5

6 3 Modified PLA Design The modified pseudo NMOS NOR gate does not change significantly the structure of the PLA circuit. Figure 6 shows a PLA implementation with the modified pseudo NMOS NOR gate. out2 in5 in4 out1 in3 in2 in1 Figure 6 Static PLA with modified pseudo NMOS NOR gate Each product term of the AND plane is implemented by a pseudo NMOS NOR gate. A logic input has to be attached to the pull up transistor in order to control the static power dissipation. The static power dissipation, in each product, is dependent on the state of the logic input that controls the pull up transistor Unlike the conventional static PLAs, the number of product terms that dissipate static power can be decreased per input vector. Then some power is saved. The total static power dissipated will depend on the number of NOR gates switched off per input vector. The same approach has to be used for the OR plane considering that the inputs are the products of the AND plane. An ordinary input of the product term could be chosen to control the pull up transistor. But the best choice is the input that keeps the pull up off. Of course, there are functions where the same input could be chosen in order to control all pull ups of the AND plane. However, if the transition activity is not favorable, it cannot avoid static power dissipation. 6

7 Instead of choosing an ordinary input to control the pull up transistor for each product, a new input signal could be created in order to force the power down mode over the PLA. In this case, the PLA can be implemented like a hybrid PLA, as shown in figure 4. The clock line of the hybrid PLA must be replaced by the power down signal. When the power down mode is on, all pull ups of the AND plane will be off, and no static power is dissipated. Although this approach can keep the static behavior of the same circuit, it requires that the environment creates a new control variable independent of the logic function implemented. 3.1 Results Spice simulations were done in order to measure the power dissipated by both static PLAs. The PLAs were implemented in a 0.6 m transistor technology and Vdd source of 5V. The set of input vectors implemented all possible combinations. The frequency for which the input vectors were changed was 160MHz. The simulations only took into account transistors network. Resistances and capacitances from the connections were not considered. Although the simulations do not consider connections, it is reasonable to assume that the areas of the PLAs are the same, and, therefore, the power dissipated due to the influence of connection is comparable. Table 2 shows the functions that we implemented as pseudo NMOS and modified pseudo NMOS PLAs. The functions have different sizes in terms of inputs, outputs and products. The small number of inputs was chosen in order to allow feasible Spice simulations. All functions were minimized by Espresso. Table 2 Simulated functions Functions Inputs Outputs Products C Fa cm42a cm138a decod z4ml f51m symml alu We can see from figure 7 that the modified pseudo NMOS PLAs have better results in terms of average power dissipated for the entire set of simulations. The average power dissipated decreases between 32 and 61%. The inputs that control the pull ups were taken randomly, and their transition activity was not observed. We observed that the PLAs had almost the same speed performance, and the differences are not significative. 7

8 watts conventional PLA modified PLA 0 C17 Fa cm42a cm138a decod z4ml f51m 9symml alu2 Figure 7 Average power dissipated 4 Conclusions Modified pseudo NMOS NOR gates improve the power efficiency of static PLAs. In fact, modified pseudo NMOS NOR gates are very suitable for static PLAs. Modified pseudo NMOS gates are power down data dependent. Static PLAs can use it for power down mode strategies. In conventional static PLA all product terms and outputs have static power dissipation, while in the modified PLA, a number of the product terms and outputs can be switched off depending on the input vector. This approach saves some static power dissipation. A strategy to minimize the PLAs that takes into account the transition activities of the inputs in both planes can probably improve the results. References [1] Gary D.Hachtel and Fabio Somenzi. Logic Synthesis and Verification Algorithms. Kluwer Academic Publishers [2] Giovanni De Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill International Editions [3] Sasan Iman. Logic Synthesis for Low Power VLSI Designs. University of Southern California, PhD. Thesis [4] Neil H.E.West and Kamran Eshraghian. Principles of CMOS VLSI Design. Addison Wesley Publishing Company

9 [5] Don Draper, et.al. Circuit Techniques in a 266 MHz MMX Enable Processor. IEEE Journal of Solid State Circuits Vol.32, No.11, November, p [6] David Greenhill, et.alii. A 330Mhz 4 Way Superscalar Microprocessor. IEEE International Solid State Circuits Conference Digest of Technical Papers p