ESE 570 Cadence Lab Assignment 1: Logic Simulation in Verilog-XL

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1 ESE 570 Cadence Lab Assignment 1: Logic Simulation in Verilog-XL Exercises Part A i. CMOS inverter Schematic Description Yang Lu, Department of Material Science and Engineering Symbol Description

2 Functional Description //Verilog HDL for "ESE570", "inv" "functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module inv ( out, in ); input in; output out; not (strong1, strong0) #1 (out,in); endmodule `endcelldefine

3 Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. Initial begin in = 1'b0; #25 in = 1'b1; #35 in = 1'b0; #75 in = 1'b1; #100 $finish; End

4 ii. 2-input NOR gate Schematic Description Symbol Description

5 Functional Description //Verilog HDL for "ESE570", "NOR" "functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module NOR ( out, in1, in2 ); input in2; input in1; output out; nor (strong1, strong0) #1 (out, in1, in2);

6 endmodule `endcelldefine Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin in1 = 1'b0; in2 = 1'b0; #25 in1 = 1'b1; in2 = 1'b0; #25 in1 = 1'b1; in2 = 1'b1; #50 in1 = 1'b0; in2 = 1'b1; #100 $finish; end

7 iii. 2-input NAND Schematic Description Symbol Description

8 Functional Description //Verilog HDL for "ESE570", "Nand" "functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module My_Nand ( out, in1, in2 ); input in2; input in1; output out; nand (strong1, strong0) #1 (out, in1, in2); endmodule `endcelldefine

9 Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin in1 = 1'b0; in2 = 1'b0; #25 in1 = 1'b1; in2 = 1'b0; #25 in1 = 1'b1; in2 = 1'b1; #50 in1 = 1'b0; in2 = 1'b1; #100 $finish; end

10 Exercises Part B i. Two-Phase Clock Schematic Description Functional Description //Verilog HDL for "ESE570", "TwoPhaseCLk" "Functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module TwoPhaseCLk ( clk, clkp, clkin ); output clk; input clkin; output clkp; wire o, clk, clkp; not (strong1, strong0) #1 (o, clkin);

11 nor #1 (clkp, clkin, clk); nor #1 (clk, clkp, o); endmodule `endcelldefine Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin clkin = 1'b0; //to make clkin frequency =25MHz, half period should be 1/2*25MHz=20ns

12 #50 $finish; end

13 ii. Dynamic D flip-flop Schematic Description Functional Description //Verilog HDL for "ESE570", "DynFF" "Functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module DynFF (q, qp, clk, clkp, d, clkin); input d, clkin; output q, qp, clk, clkp; wire o, clkp, clkpp; trireg (medium) #(1,1,200) interm1, interm3; not (strong1, strong0) #1 (o, clkin); nor (strong1, strong0) #1 (clkp, clkin, clk);

14 nor (strong1, strong0) #1 (clk, clkp, o); not (strong1, strong0) (clkp, clk); not (strong1, strong0) (clkpp, clkp); //define the two-phase clock cmos (interm1, d, clk, clkp); not (strong1, strong0) (qp, interm1); cmos (interm3, qp, clkp, clkpp); not (strong1, strong0) (q, interm3); endmodul `endcelldefine Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin clkin = 1'b0; d = 1'b0; d =1'b1;

15 d = 1'b0; #50 $finish; end With Capacitance (trireg included):

16 Without Capacitance (trireg removed):

17 iii. Static D flip-flop Schematic Description Functional Description //Verilog HDL for "ESE570", "SFF" "functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module SFF (qs, qm, clk, clkp, d, clkin ); input d, clkin; output qs, qm, clk, clkp; wire o, clkp, clkpp; wire m1, m2, m3, m4; not (strong1, strong0) (o, clkin); nor (strong1, strong0) (clkp, clkin, clk); nor (strong1, strong0) (clk, clkp, o); not (strong1, strong0) (clkp, clk); not (strong1, strong0) (clkpp, clkp);//define the two-phase clk

18 cmos (m1, d, clk, clkp); not (m2, m1); not (qm, m2); cmos (m1, qm, clkp, clkpp); cmos (m3, qm, clkp, clkpp); not (m4, m3); not (qs, m4); cmos (m3, qs, clk, clkp); endmodule `endcelldefine Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin clkin = 1'b0; d = 1'b0;

19 d =1'b1; d = 1'b0; #50 $finish; end

20 iv. Static D flip-flop with Reset Schematic Description Functional Description //Verilog HDL for "ESE570", "SFF_Reset" "Functional" `resetall `celldefine `delay_mode_path `timescale 1ns/10ps module SFF_Reset (qs, qm, clk, clkp, d, clkin, R ); input d, clkin, R; output qs,qm,clk,clkp; wire o, clkp, clkpp; wire m1, m2, m3, interm1, interm2, m4; not (strong1, strong0) (o, clkin); nor (strong1, strong0) (clkp, clkin, clk); nor (strong1, strong0) (clk, clkp, o); not (strong1, strong0) (clkp, clk); not (strong1, strong0) (clkpp, clkp); cmos (m1, d, clk, clkp); not (m2, m1);

21 not (qm, m2); cmos (m1, qm, clkp, clkpp); cmos (m3, qm, clkp, clkpp); nand (interm1, R, m3); not (interm2, interm1); not (m4, interm2); not (qs, m4); cmos (m3, qs, clk, clkp); endmodule `endcelldefine Verilog-XL Simulation // Verilog stimulus file. // Please do not create a module in this file. // Default verilog stimulus. initial begin R = 1'b1; clkin = 1'b0; d = 1'b0;

22 d =1'b1; R=1'b0; R=1'b1; d = 1'b0; R=1'b0; #50 $finish; end

23 Cadence Questions a. Your project partner has a Cadence library called lab1 in ~yourpartner/cadence. You need to access his/her library from your Cadence library browser. What should you do? What must your partner do? What commands must you and your partner use to execute this need? Copy his/her library to ~myname/cadence with different name (not ESE 570). b. What is a technology file and how does it relate to a library? In this course, we will use AMI 0.60u C5N (3M,2P,high-res) technology for our designs. After naming the library, you should attach it to a tech file by selecting "Attach to existing tech library" option in the windows. Or clicking on the middle button by placing the mouse on the library name in the library manager window. There is an option for "Attach Tech Library". Once you choose that option, click on AMI 0.6u C5N(3M,2P,high-res) as your process. c. How do you modify the properties of a transistor? Select the transistor you want to modify and press q or in the edit menu, select Edit properties d. How do you label a wire in Cadence? Press l or in add menu select wire name or click the wire name button at the left corner. e. Let s assume that Cadence has crashed while you were working on a design (a real possibility!). Now when you try to edit your design, Cadence will not let you - providing the error message that the design is locked. How do you resolve this dilemma? Copy the design out to a new cellview and restart the program.

Cadence Tutorial 6. Verilog-XL Simulation for Dynamic Logic. EE577b Fall 98

Cadence Tutorial 6. Verilog-XL Simulation for Dynamic Logic. EE577b Fall 98 Cadence Tutorial 6 Verilog-XL Simulation for Dynamic Logic EE577b Fall 98 In this tutorial, I am going to demonstrate how to design and simulate the domino style dynamic logic. 1. Tutorial Setup No previous