Embedded System Tools Reference Manual

Transcription

1 Embedded System Tools Reference Manual Embedded Development Kit EDK 7.1i UG111 (v4.0) February 15, 2005 R

2 2005 Xilin, Inc. All Rights Reserved. XILINX, the Xilin logo, and other designated brands included herein are trademarks of Xilin, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: Xilin is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilin makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilin epressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

3 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005 The following table shows the revision history for this document. Version Revision 06/24/ Initial Xilin EDK (Embedded Processor Development Kit) release. 08/13/ EDK (v3.1) release. 09/02/ EDK 6.1 release. 01/30/ EDK 6.2i release 03/12/04 Updated for service pack release. 03/19/ Updated for service pack release. 08/20/ EDK 6.3i release. 02/15/ EDK 7.1i release. UG111 (v4.0) February 15, Embedded System Tools Reference Manual

4 Embedded System Tools Reference Manual UG111 (v4.0) February 15,

5 Preface About This Guide Guide Contents Welcome to the Embedded Development Kit (EDK). This kit is designed to provide designers with a rich set of design tools and a wide selection of standard peripherals required to build embedded processor systems using MicroBlaze, the industry s fastest soft processor solution, and the new and unique feature in Virte -II Pro, the IBM PowerPC CPU. This guide provides information about the Embedded System Tools (EST) included in EDK. These tools, consisting of processor platform tailoring utilities, software application development tool, a full featured debug tool chain and device drivers and libraries, allow the developer to fully eploit the power of MicroBlaze and Virte-II Pro. This guide contains the following chapters: Chapter 1, Embedded System Tools Architecture Chapter 2, Xilin Platform Studio (XPS) Chapter 3, Base System Builder Chapter 4, Create and Import Peripheral Wizard Chapter 5, Platform Generator Chapter 6, Simulation Model Generator Chapter 7, Library Generator Chapter 8, Virtual Platform Generator Chapter 9, Platform Specification Utility Chapter 10, Format Revision Tool Chapter 11, Bitstream Initializer Chapter 12, Programming Flash Memory Chapter 13, GNU Compiler Tools Chapter 14, GNU Debugger Chapter 15, Xilin Microprocessor Debugger (XMD) Chapter 16, Xilin EDK Cygwin Shell Embedded System Tools Reference Manual 5 UG111 (v4.0) February 15,

6 Preface: About This Guide Additional Resources For additional information, go to The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource EDK Home EDK Eamples Tutorials Answer Browser Application Notes Data Sheets Problem Solvers Tech Tips GNU Manuals Description/URL Embedded Development Kit home page, FAQ and tips. A set of complete EDK eamples. Tutorials covering Xilin design flows, from design entry to verification and debugging Database of Xilin solution records Descriptions of device-specific design techniques and approaches ategory=application+notes Device-specific information on Xilin device characteristics, including readback, boundary scan, configuration, length count, and debugging Interactive tools that allow you to troubleshoot your design issues Latest news, design tips, and patch information for the Xilin design environment The entire set of GNU manuals Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

7 Conventions R Conventions This document uses the following conventions. An eample illustrates each convention. Typographical The following typographical conventions are used in this document: Convention Meaning or Use Eample Courier font Courier bold Helvetica bold Italic font Square brackets [ ] Braces { } Vertical bar Vertical ellipsis... Horizontal ellipsis... Messages, prompts, and program files that the system displays Literal commands that you enter in a syntactical statement Commands that you select from a menu Keyboard shortcuts Variables in a synta statement for which you must supply values References to other manuals Emphasis in tet An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required. A list of items from which you must choose one or more Separates items in a list of choices Repetitive material that has been omitted Repetitive material that has been omitted speed grade: ngdbuild design_name File o Open Ctrl+C ngdbuild design_name See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name lowpwr ={on off} lowpwr ={on off} IOB #1: Name = QOUT IOB #2: Name = CLKIN... allow block block_name loc1 loc2... locn; Embedded System Tools Reference Manual 7 UG111 (v4.0) February 15,

8 Preface: About This Guide Online Document The following conventions are used in this document: Convention Meaning or Use Eample Blue tet Red tet Blue, underlined tet Cross-reference link to a location in the current document Cross-reference link to a location in another document Hyperlink to a website (URL) See the section Additional Resources for details. Refer to Title Formats in Chapter 1 for details. See Figure 2-5 in the Virte-II Handbook. Go to for the latest speed files. 8 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

9 Table of Contents Preface: About This Guide Guide Contents Additional Resources Conventions Typographical Online Document Chapter 1: Embedded System Tools Architecture Tool Architecture Overview Tool Flows Hardware Platform Creation Verification Platform Creation Software Platform Creation Software Application Creation and Verification Useful Tools Xilin Platform Studio Base System Builder Create/Import IP Wizard Platform Generator Simulation Model Generator Library Generator Bitstream Initializer Format Revision Tool GNU Compiler Tools MicroBlaze PowerPC Compiling with Optimization Setting the Stack Size Software Debugging Dumping an Object/Eecutable File Verifying Tools Setup Tools Directory Path For Solaris or Linu For PC Xilin Alliance Software Chapter 2: Xilin Platform Studio (XPS) Processes Supported Tools Supported Features Project Management Creating a New Project Opening an Eisting Project Getting Help Embedded System Tools Reference Manual 9 UG111 (v4.0) February 15,

10 XPS Interface Editor Workspace System Tab Applications Tab Transcript Window Platform Management Add/Edit Cores Dialog Bo Add SW Application Project Simulation Models View MPD View MLD View MDD View Core Modifications View PDF Doc View Core License Status S/W Settings Software Platform Processor and Driver Parameters Library and O/S Parameters Software Application Management Adding Files Deleting Files from Project Editing Files Mark Application for Downloading to BRAMs Application to be Compiled Outside of the XPS Environment Bootloop Software Applications XMDStub Software Applications Compiler Options Generating Linker Scripts Flow Tool Settings and Required Files Compiler Options Project Options Required Files Tool Invocation Software Flow Hardware Flow Merging Hardware and Software Flows and Downloading ISE Project Navigator Interface Debug and Simulation PBD Editor PBD Editor Interface PBD Editor Workspace System Tabs Creating the Hardware Block Diagram Adding a Component Instance to the System Naming an Instance Setting Component Instance Parameters Setting Symbol Properties Connecting a Component Bus Pin to a Bus Connecting Ports Viewing and Editing System Ports Viewing and Editing All of the Ports in the System Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

11 Viewing and Editing Interrupts Editing the Block Diagram Selecting Objects Viewing Object Information Zooming in the Workspace Drawing Non-Electrical Objects XPS No Window Mode Available Commands Creating a New Empty Project Creating a New Project With Given MHS Opening an Eisting Project Reading an MSS File Saving Files and Your Project Setting Project Options Eecuting Flow Commands Reloading an MHS File Adding a Software Application Deleting a Software Application Adding a Program File To a Software Application Deleting a Program File From a Software Application Setting Options on a Software Application Settings on Special Software Applications Closing a Project and Eiting XPS Limitations and Workarounds MSS Changes XMP Changes Chapter 3: Base System Builder BSB Flow Invoking BSB Selecting a Starting Point Create a New Design Load an Eisting BSB File Selecting a Target Development Board Select an Eisting Board Create a System for a Custom Board Selecting a Processor Configuring Processor and System Settings Selecting Eternal Memories and I/O Devices Adding Internal Peripherals Configuring Software Settings Memory Test Peripheral Test Generating the System and Address Map Output Files Eiting BSB Limitations Chapter 4: Create and Import Peripheral Wizard Invoking the Wizard Creating New Peripherals Embedded System Tools Reference Manual 11 UG111 (v4.0) February 15,

12 Information About Creating New Peripherals Identifying the Physical Location of Your Peripheral Storing the New Peripheral in an EDK User Repository Storing the New Peripheral in an XPS Project Identifying Module and Version Naming Conventions for Peripherals Selecting the Bus Interface OPB/PLB Bus Interfaces FSL Bus Interfaces Generating the Files Representing Your Design Importing an Eisting Peripheral Identifying the Physical Location of Your Peripheral Identifying Module and Version Select Source File Types HDL Source Files HDL Analysis Information Bus Interfaces Identifying Bus Interface Ports and Parameters Interrupt Signals Advanced Attributes on Ports and Parameters Port Attributes Parameter Attributes Netlist Files Documentation Files Completing Peripheral Import Organization of Generated Files Restrictions Create Peripheral Mode Import Peripheral Mode Chapter 5: Platform Generator Tool Requirements Tool Usage Tool Options Load Path Output Files HDL Directory Implementation Directory Synthesis Directory About Memory Generation BMM Policy BMM Flow Reserved MHS Parameters Synthesis Netlist Cache Current Limitations Chapter 6: Simulation Model Generator Simgen Overview Simulation Basics Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

13 Behavioral Simulation Structural Simulation Timing Simulation Simulation Libraries Xilin Libraries UNISIM Library SIMPRIM Library XilinCoreLib Library EDK Library COMPEDKLIB Utility Tool Usage COMPEDKLIB Command Line Eamples Use Case I: Launching the GUI to Compile the Xilin and EDK Simulation Libraries. 106 Use Case II: Compiling HDL Sources in the Built-In Repositories in the EDK Use Case III: Compiling HDL Sources in Your Own Repository Other Details Simulation Models Behavioral Models Structural Models Timing Models Single and Mied Language Models Simgen Synta Requirements Options Output Files Memory Initialization VHDL Verilog Simulating Your Design Current Limitations Chapter 7: Library Generator Overview Tool Usage Tool Options Load Paths UNIX System Load Paths PC System Load Paths Additional Directories Search Priority Mechanism Output Files include Directory lib Directory libsrc Directory code Directory Libraries and Drivers Generation Basic Philosophy MDD/MLD and Tcl MSS Parameters Embedded System Tools Reference Manual 13 UG111 (v4.0) February 15,

14 Drivers Libraries OS Interrupts and Interrupt Controller Importance of Instantiation Interrupt Controller Driver Customization MicroBlaze PowerPC XMDStub Peripherals (MicroBlaze Specific) STDIN and STDOUT Peripherals Chapter 8: Virtual Platform Generator Overview Tool Usage and Options Output Files Available Models Current Restrictions Chapter 9: Platform Specification Utility Tool Options Overview of the MPD Creation Process Detailed Use Models for Automatic MPD Creation Peripherals with a Single Bus Interface Signal Naming Conventions Invoking PsfUtility Peripherals with Multiple Bus Interfaces Non-Eclusive Bus Interfaces Eclusive Bus Interfaces Peripherals with TRANSPARENT Bus Interfaces BRAM PORTS DRC Checks in PsfUtility HDL Source Errors Bus Interface Checks HDL Peripheral Definitions Bus Interface Naming Conventions Naming Conventions for VHDL Generics Reserved Parameters Signal Naming Conventions Global Ports LMB - Clock and Reset OPB - Clock and Reset PLB - Clock and Reset Slave DCR Ports DCR Slave Outputs DCR Slave Inputs Slave LMB Ports LMB Slave Outputs LMB Slave Inputs Master OPB Ports Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

15 OPB Master Outputs OPB Master Inputs Slave OPB Ports OPB Slave Outputs OPB Slave Inputs Master/Slave OPB Ports OPB Master/Slave Outputs OPB Master/Slave Inputs Master PLB Ports PLB Master Outputs PLB Master Inputs Slave PLB Ports PLB Slave Outputs PLB Slave Inputs Chapter 10: Format Revision Tool Tool Usage Limitations Chapter 11: Bitstream Initializer Overview Tool Usage Tool Options Chapter 12: Programming Flash Memory Overview Prerequisites Supported Flash Hardware Using the Program Flash Memory Dialog Bo File to Program Auto Convert File Download Mode Processor Instance Flash Memory Properties Instance Name Program At Offset Scratch Pad Memory Properties Instance Name Create Flash Bootloader SW Application Project Program Flash Customizing Flash Programming Handling Flash Parts with Conflicting Sector Layouts Using Flash Memory Customizing the Bootloader Converting ELF to SREC Embedded System Tools Reference Manual 15 UG111 (v4.0) February 15,

16 Chapter 13: GNU Compiler Tools GNU Compiler Framework Compiler Usage and Options Usage Quick Reference Compiler Options g gstabs On v save-temps o filename Wp,option, -Wa,option, and -Wl,option help Library Search Options Header File Search Option Linker Options defsym _STACK_SIZE=value defsym _HEAP_SIZE=value Linker Scripts Search Paths Solaris Search Paths On Windows Cygwin Shell File Etensions File Types and Etensions Libraries Compiler Interface Input Files Output Files MicroBlaze GNU Compiler Quick Reference MicroBlaze Compiler ml-soft-mul mno-l-soft-mul ml-soft-div mno-l-soft-div ml-stack-check ml-barrel-shift ml-gp-opt l-mode-eecutable l-mode-mdstub l-mode-ilkernel ml-pattern-compare mhard-float MicroBlaze Assembler MicroBlaze Linker defsym _TEXT_START_ADDR=value rela N Initialization Files crt0.o crt1.o Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

17 crt4.o Compiler Libraries Command Line Arguments Interrupt Handlers _interrupt_handler attribute _save_volatiles attribute PowerPC GNU Compiler Compiler Options mhard-float msoft-float Linker Options defsym _START_ADDR=value Initialization Files Chapter 14: GNU Debugger Overview Tool Usage Tool Options Debug Flow using GDB MicroBlaze GDB Targets Simulator Target Hardware Target Virtual Platform Target Compiling for Debugging on MicroBlaze Targets PowerPC Targets Console Mode GDB Command Reference Chapter 15: Xilin Microprocessor Debugger (XMD) XMD Usage XMD Command Reference Connect Command Options PowerPC Target PowerPC Hardware Connection PowerPC Target Requirements Eample Debug Sessions PowerPC Simulator Target Running PowerPC ISS Eample Debug Session for PowerPC ISS Target MicroBlaze Processor Target MicroBlaze MDM Hardware Target MicroBlaze MDM Target Requirements Eample Debug Sessions MicroBlaze Stub Hardware Target MicroBlaze Stub-JTAG Target Options MicroBlaze Stub-Serial Target Options Stub Target Requirements MicroBlaze Simulator Target Simulator Target Requirements MDM Peripheral Target Embedded System Tools Reference Manual 17 UG111 (v4.0) February 15,

18 MDM Target Requirements Virtual Platform MicroBlaze Target Configure Debug Session XMD Internal Tcl Commands Program Initialization Options Register/Memory Options Program Control Options Program Trace/Profile Options Miscellaneous Commands XMD TCP Socket Interface Sending Commands to XMD Return Types Chapter 16: Xilin EDK Cygwin Shell Summary The EDK-Installed Cygwin Shell Requirements for Using an Eisting Cygwin Environment Advanced Options Usage The -override and -undo Options Appendi A: GNU Utilities General Purpose Code for MicroBlaze and PowerPC cpp gcov Code Specific to MicroBlaze and PowerPC mb-addr2line mb-ar mb-as mb-c mb-c++filt mb-g mb-gasp mb-gcc mb-gdb mb-gprof mb-ld mb-nm mb-objcopy mb-objdump mb-ranlib mb-readelf mb-size mb-strings mb-strip Glossary Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

19 Chapter 1 Embedded System Tools Architecture This chapter describes the Embedded System Tools (EST) architecture and flows for the Xilin embedded processors: PowerPC 405 and MicroBlaze. The chapter contains the following sections: Tool Architecture Overview Tool Flows Useful Tools Verifying Tools Setup Tool Architecture Overview Figure 1-1 depicts the embedded software tool architecture. Multiple tools based on a common framework allow you to design the complete embedded system. The system design consists of the creation of the hardware and software components of the embedded processor system, and optionally a verification or simulation component, as described below: The hardware component consists of an automatically generated hardware platform that can be optionally etended to include other hardware functionality that you specify. The software component of the design consists of the software platform generated by the tools, along with your user-designed application software. The verification component consists of automatically generated simulation models targeted to a specific simulator, based on the hardware and software components. BSB Wizard HW Spec Ed. HW Plat. Gen Sim Spec Ed. Sim Plat. Gen. Simulators ISE - HW Impl. XPS SW Spec Ed. SW Plat. Gen. SW Source Ed. SW. Compilers SW Debugger XMD Bitinit X10230 Figure 1-1: Embedded Software Tool Architecture Embedded System Tools Reference Manual 19 UG111 (v4.0) February 15,

20 Chapter 1: Embedded System Tools Architecture Tool Flows A typical embedded system design project involves the following phases: 1. Hardware platform creation 2. Hardware platform verification using simulation 3. Software platform creation 4. Software application creation 5. Software verification using debugging Xilin provides tools to assist in all the above design phases. These tools work with other third-party tools such as simulators and tet editors that can be used by the designers. Hardware Platform Creation Xilin Platform Studio (XPS) provides the Base System Builder Wizard for creating the hardware platform (see Chapter 3, Base System Builder, for more information about the wizard). Details of hardware platform creation are depicted in Figure 1-2. HW Spec Ed. XPS, WIZARDS MHS File HW Plat. Gen Platgen MHS File EDIF, NGC, VHD,V,BMM XPS X10088 Figure 1-2: Hardware Platform Creation The hardware platform is defined by the Microprocessor Hardware Specification (MHS) file. Refer to the Microprocessor Hardware Specification (MHS) chapter in the Platform Specification Format Reference Manual for more information. The hardware platform consists of one or more processors and peripherals connected to the processor busses. Several useful peripherals are usually supplied by Xilin, along with the EDK tools. You can define your own peripherals and include them in the MHS by following the guidelines in the Platform Specification Format Reference Manual. The MHS file is a simple tet file that you can create with any tet editor. XPS provides graphical means to create the MHS file. The MHS file defines the system architecture, peripherals, and embedded processors. It also defines the connectivity of the system, the address map of each peripheral in the system, and configurable options for each peripheral. You can also specify multiple processor instances connected to one or more peripherals through one or more buses and bridges in the MHS Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

21 Tool Flows R The Platform Generator tool (Platgen) creates the hardware platform using the MHS file as input. Platgen creates netlist files in various formats such as NGC and EDIF, support files for downstream tools, and top level HDL wrappers to allow you to add other components to the automatically generated hardware platform. See Chapter 5, Platform Generator, for more information. Note: After running Platgen, FPGA implementation tools, which are part of ISE, are run automatically to complete the implementation of the hardware. See ISE documentation for more info on the ISE tools. At the end of the ISE flow, a bitstream generates to configure the FPGA. This bitstream includes initialization information for BRAM memories on the FPGA chip. If your code or data is required to be placed on these memories at startup time, the Bitinit tool is used to update the bitstream with code/data information obtained from your eecutable files, which are generated at the end of the Software Application Creation and Verification flow. Verification Platform Creation The verification platform is based on the hardware platform. The Simgen tool processes the MHS file to create simulation files, such as VHDL, Verilog, or various compiled models, along with some command files for specific simulators supported by the tool. Refer to Chapter 6, Simulation Model Generator for more information. As in the hardware platform, you can edit these simulation files to add other components to the automatically generated verification platform. The entire process of generating the verification platform is depicted in Figure 1-3. If the software application that runs on the hardware platform is available in eecutable format, it can initialize memories in the verification platform. Details of this process are provided in later chapters. Sim Spec Ed. XPS GUI MHS File Sim Plat. Gen Simgen MHS,.elf.vhd,.v for sim XPS X10089 Figure 1-3: Verification Platform Software Platform Creation The software platform is defined by the Microprocessor Software Specification (MSS) file. Refer to the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual for more information. The MSS file defines driver and library customization parameters for peripherals, processor customization parameters, standard input/output devices, interrupt handler routines, and other related software features. The MSS file is a simple tet file that you can create using any tet editor. The XPS tool provides a graphical user interface for creating the MSS file. Refer to Chapter 2, Xilin Platform Studio (XPS) for more information. Embedded System Tools Reference Manual 21 UG111 (v4.0) February 15,

22 Chapter 1: Embedded System Tools Architecture The MSS file is an input to the Library Generator tool (Libgen) for customization of drivers, libraries, and interrupt handlers. See Chapter 7, Library Generator for more information. The entire process of creating the software platform is shown in Figure 1-4. SW Spec Ed. Emacs, XPS MSS Editor MSS File SW Plat. Gen libgen MSS, MHS, lib/*.c, lib/*.h libc.a, libxil.a XPS X9881 Figure 1-4: Software Platform Software Application Creation and Verification The software application is the code that runs on the hardware and software platforms. The source code for the application is written in a high level language such as C or C++, or in assembly language. XPS provides a source editor for creating these files, but you can use any other tet editor. Once you create the source files, you compiled and link them to generate eecutable files in the Eecutable and Link Format (ELF) format. GNU compiler tools for PowerPC and MicroBlaze are used by default, but you can use other compiler tools that support the specific processors used in the hardware platform. XMD and the GNU Debugger (GDB) work together to debug the software application. Refer to Chapter 13, GNU Compiler Tools for more information. XMD provides an instruction set simulator, and optionally connects to a working hardware platform to allow GDB to run the application. This entire process is depicted in Figure 1-5. Refer to Chapter 15, Xilin Microprocessor Debugger (XMD), for more information on XMD, and Chapter 14, GNU Debugger, for more information on GDB. The Eclipse development environment is provided as an alternative to XPS for software application development. Eclipse has its own built-in source code editor and invokes the same compiler and debugger tools as XPS Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

23 Useful Tools R SW Source Ed. Emacs, XPS Source Editor.c and.h files SW Compilers Mb-gcc, ppc-gcc.c and.h files libc.a, libxil.a.elf file XPS SW Debuggers Mb-gdb, ppc-gdb.c and.h files.elf file XMD X9882 Figure 1-5: Software Application Creation and Verification Useful Tools Xilin Platform Studio The Xilin Platform Studio (XPS) tool provides an interface for creating MHS and MSS files for the hardware and software flow. XPS also provides source file editor capability and project and process management capability. XPS is used for managing the complete tool flow, that is, both hardware and software implementation flows. Refer to Chapter 2, Xilin Platform Studio (XPS) for more information. Base System Builder The Base System Builder (BSB) wizard is a software tool that help you quickly build a working system targeted at a specific development board. XPS invokes BSB when you create a new system. See Chapter 3, Base System Builder, for more information. Create/Import IP Wizard The Create/Import Peripheral Wizard helps you create your own peripherals and import them into EDK compliant repositories or XPS projects. This wizard uses the PsfUtility tool to create the necessary Platform Specification files. Refer to Chapter 4, Create and Import Peripheral Wizard, for more information on the wizard, and see Chapter 9, Platform Specification Utility, for more information of PsfUtility. Embedded System Tools Reference Manual 23 UG111 (v4.0) February 15,

24 Chapter 1: Embedded System Tools Architecture Platform Generator The embedded processor system in the form of hardware netlists (HDL and EDIF files) is customized and generated by Platgen. Refer to Chapter 5, Platform Generator, for more information. Simulation Model Generator Library Generator The Simulation Platform Generation tool (Simgen) generates and configures various simulation models for the hardware. It takes an MHS file as input. Refer to Chapter 6, Simulation Model Generator for details. XPS calls Libgen for configuring the software flow. Libgen configures libraries, device drivers, file systems and interrupt handlers for the embedded processor system. The input to Libgen is an MSS file. Refer to Chapter 7, Library Generator, for more information. For more information on Libraries and Device Drivers refer to the Xilin Microkernel (XMK) chapter in the EDK OS and Libraries Reference Manual and the Device Driver Programmer Guide chapter in the Processor IP Reference Guide. Bitstream Initializer The Bitstream Initializer tool initializes the instruction memory of processors on the FPGA. The instruction memory of processors is stored in BlockRAMs in the FPGA. This utility reads an MHS file and invokes the Data2MEM utility provided in ISE to initialize the FPGA BlockRAMs. See Chapter 11, Bitstream Initializer, for more information. Format Revision Tool The Format Revision Tool, revup, updates an eisting EDK 6. project to an EDK 7.1 project. If you open a project from 6. in XPS 7.1, then it automatically updates the project to the new release. See Chapter 10, Format Revision Tool, for more information. GNU Compiler Tools XPS calls GNU compiler tools for compiling and linking application eecutables for each processor in the system. Given a set of C source files, a Microprocessor eecutable is created as described in the following sections, for MicroBlaze and PowerPC, respectively. MicroBlaze mb-gcc file1.c file2.c This command compiles and links the files into an eecutable file that runs on the MicroBlaze processor. The output eecutable is in a.out. You can use the -o flag to specify a different file name for the output file Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

25 Useful Tools R In order to initialize memories in the hardware bitstream with this eecutable, the file name should have an ELF etension. For further information on compiler options, type mb-gcc -help at the command line. Refer to Chapter 13, GNU Compiler Tools, for more information. PowerPC powerpc-eabi-gcc file1.c file2.c This command compiles and links the files into an eecutable file that runs on the PowerPC processor. The output eecutable is in a.out. You can use the -o flag to specify a different file name for the output file. In order to initialize memories in the hardware bitstream with this eecutable, the file name should have an ELF etension. For further information on compiler options, type powerpc-eabi-gcc --help at the command line. See Chapter 13, GNU Compiler Tools, for more information. Compiling with Optimization Once you are satisfied that your program is correct, recompile your program with optimization turned on. This reduces the size of your eecutable, and reduces the number of cycles it needs to eecute. to recompile your program, type the following: mb-gcc -O3 file1.c file2.c Setting the Stack Size By default, the EDK tools build the eecutable with a default stack size of 0100 (256) bytes. You can set the stack size at compile time by typing: mb-gcc file1.c file2.c -Wl,defsym -Wl,_STACK_SIZE=0400 This command sets the stack size to 0400 (1024) bytes. Software Debugging You can debug your program in software using an instruction set simulator or virtual platform, or on a board which has a Xilin FPGA loaded with your hardware bitstream. See Chapter 15, Xilin Microprocessor Debugger (XMD), for more information. Dumping an Object/Eecutable File The mb-objdump utility lets you see the contents of an object (.o) or eecutable (.out) file. To see your symbol table, the size of your file, and the names/sizes of the sections in the file, type the following: mb-objdump - a.out To see a listing of the (assembly) code in your object or eecutable file, type the following: mb-objdump -d a.out To get a list of other options, type the following command: mb-objdump --help Embedded System Tools Reference Manual 25 UG111 (v4.0) February 15,

26 Chapter 1: Embedded System Tools Architecture Verifying Tools Setup You must set the environment variable XILINX_EDK at the level of the hierarchy where the directories doc, hw, and bin reside. Tools Directory Path Ensure that the GNU tools are in your path. For Solaris or Linu Check the eecutable search path. Your path must include the following: For PC ${XILINX_EDK}/gnu/microblaze/sol/bin ${XILINX_EDK}/gnu/powerpc-eabi/sol/bin ${XILINX_EDK}/bin/sol Check the eecutable search path. Your path must include the following: %XILINX_EDK%\gnu\microblaze\nt\bin %XILINX_EDK%\gnu\powerpc-eabi\nt\bin %XILINX_EDK%\bin\nt Xilin Alliance Software The system should be set up to use the Xilin Development System. Verify that the system is properly configured. Consult release notes and installation notes included in the Xilin ISE software package for more information. The EDK 7.1i release requires Xilin ISE 7.1i Tools Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

27 Chapter 2 Xilin Platform Studio (XPS) This chapter describes the XPS Integrated Design Environment (IDE) for the Xilin Embedded Processors, MicroBlaze and PowerPC. XPS provides an integrated environment for creating the software and hardware specification flows for an embedded processor system. It also provides an editor and a project management interface to create and edit source code. XPS offers customization of tool flow configuration options and provides a graphical system editor for connection of processors, peripherals and buses. XPS is available on Windows, Solaris, and Linu platforms. There is also a batch mode invocation of XPS available. This chapter contains the following sections. Processes Supported Tools Supported Project Management XPS Interface Platform Management Software Application Management Flow Tool Settings and Required Files Tool Invocation Debug and Simulation PBD Editor Processes Supported XPS No Window Mode XPS supports the creation of the Microprocessor Hardware Specification (MHS) and Microprocessor Software Specification (MSS) files needed for embedded tools flow. For more information about these files, refer to the Microprocessor Hardware Specification (MHS) and Microprocessor Software Specification (MSS) chapters in the Platform Specification Format Reference Manual. Embedded System Tools Reference Manual 27 UG111 (v4.0) February 15,

28 Chapter 2: Xilin Platform Studio (XPS) The Microprocessor Verification Specification (MVS) file used in EDK 3.2 has been discontinued and that information is stored in XPS project files. XPS also aids you in creating an MHS file through a dialog-based editor and bus connection matri, or through a graphical block diagram editor, referred to as the Platform Block Diagram editor. It supports customization of software libraries, drivers, and interrupt handlers, and compilation of programs. XPS provides source management of C source files and header files for applications. You can also choose the simulation mode for the complete system. You can begin a project by either importing an eisting MHS file or by starting with an empty MHS file and then adding cores to it. XPS performs process management and dependency checking between the hardware, software and simulation tool flows by calling the tools in the correct order using a makefile mechanism. Figure 2-1 provides a detailed view of processes supported by XPS. MHS File XMP File Project Management User Program Sources Program Sources Management MSS Engine Process Management Make File Platgen Libgen Implementation Tools Compiler Data2MEM X10125 Figure 2-1: XPS Process 28 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

29 Tools Supported R Tools Supported Features Table 2-1 describes the tools that are supported in XPS. Table 2-1: XPS has the following features: Ability to add cores, edit core parameters, and make bus and signal connections to generate an MHS file Generation and modification of the MSS file Support for all of the tools described in Table 2-1. Library Generator (Libgen) Tools Supported in XPS Tool Function Reference/Notes GNU Compiler Tools Platform Generator (Platgen) Simulation Model Generator (Simgen) Virtual Platform Generator (VPgen) Makefile Graphical Block Diagram View and Editor. Multiple User Software Applications support Project management Customizes software libraries, drivers and interrupt handlers. Preprocess, compile, assemble, and link programs. Allows you to customize various options. Runs Platgen with the options and the MHS file. Generates the hardware simulation model and the compilation script file for the complete system. Generates a binary eecutable for the hardware system. Generates a makefile, which provides targets to run various hardware and software flow tools. Process and tool flow dependency management Chapter 7, Library Generator Chapter 13, GNU Compiler Tools Chapter 5, Platform Generator Chapter 6, Simulation Model Generator Chapter 8, Virtual Platform Generator Uses gmake on Uni platforms System ACE Generates a SystemACE file. Not supported on Solaris XMD Project Navigator Eport and Import Opens an XMD terminal for on-board debug. Eport and import design to Project Navigator for synthesis and implementation of design. Chapter 15, Xilin Microprocessor Debugger (XMD) Flow is an alternative to the Xflow mechanism in XPS Embedded System Tools Reference Manual 29 UG111 (v4.0) February 15,

30 Chapter 2: Xilin Platform Studio (XPS) Project Management Project information is saved in a Xilin Microprocessor Project (XMP) file. An XMP file consists of the location of the MHS file, the MSS file, and the C source and header files that must be compiled into an eecutable for a processor. The project also includes the FPGA architecture family and the device type for which the hardware tool flow must be run. Creating a New Project You can create a new project using either of the following tools: Base System Builder (BSB). You can use this wizard to create a basic system. To create a project using the BSB, select File o New Project o Base System Builder from the XPS main window. The Base System Builder Wizard opens. For more information about the BSB, refer to Chapter 3, Base System Builder. Platform Studio. You can create a new project in the XPS Create New Project window. To do this, select File o New Project o Platform Studio from the XPS main window. The Create New Project dialog bo opens. You can also access this tool by clicking the New Project toolbar button. When creating a new project, you must specify the location of the XMP file. The name of the XMP file is used as the project name, and the directory where the XMP file resides is considered to be the project directory. All tools are invoked from the project directory. All relative paths are assumed to be relative to the project directory. You can also specify an MHS file to be used for the project if the project is created using XPS. If the specified MHS file does not eist in the project directory or does not have same name as the project name, XPS copies it into the project directory with same base name as the project name. XPS always modifies the local copy of the MHS and never refers to the original MHS. You must set the target architecture before running any tool. However, choosing the device size, the package, and the speed grade can be deferred until implementation of the design. You can set or change these options in the Project Options dialog bo by selecting Options o Project Options in the XPS main window. You must specify all Search Path directories before loading the project if: The MHS uses a peripheral which is not present either in the Xilin EDK installation area or in pcores directory of the XPS project directory. The MSS uses a driver which is not present either in the Xilin EDK installation area or in the drivers directory of the XPS project directory. The concept of a Search Path directory and its subdirectory structure is eplained in detail in Chapter 5, Platform Generator, and Chapter 7, Library Generator. This corresponds to the -lp option of the tools. All of the tools automatically look into the pcores and drivers directories in the project directory and that the project directory itself should not be specified as the search path. You can specify multiple directories can be specified as part of a search path by specifying a semicolon-separated list of directories. Opening an Eisting Project To open an eisting XPS project, select File o Open Project or click the Open Project toolbar button, and then specify the eisting XMP file corresponding to that project. You can create, add, and delete new source files and header files. XPS does not allow multiple projects to be open simultaneously. You must close an open project before you can open another project Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

31 XPS Interface R XPS Interface Getting Help The Help menu in XPS provides access to several types of XPS help documentation: EDK Help Contents opens the EDK online help. EDK Online Documentation opens the EDK home page. EDK Eamples links to the EDK eamples web page. Many eample designs are updated in this web site for you to download and use. The XPS interface contains the following sections: Editor Workspace System Tab Applications Tab Transcript Window Editor Workspace The main editor workspace appears on the right side of the XPS main window. The workspace opens a Platform Block Diagram (PBD) file and allows graphical editing of the system. The main workspace also functions as a C source and header file editor of XPS. You can view and edit any number of tet or HTML files simultaneously in the XPS main window. You can open the PBD file by double-clicking on the PBD file in the system tree view or by selecting Project o View Schematic. The PBD editor is described in more detail in PBD Editor on page 44. System Tab The System tab is one tab that appears on the left side of the XPS window. This tab shows the system in a tree format. There are four sub-trees in this view: The System BSP tree shows system components (various cores) by their instance names. Each core can have its own sub-tree which displays information corresponding to that instance, such as base address and high address. Source and header files corresponding to a processor are listed in the sub-tree for that processor instance. The Project Files tree shows the MHS, MSS, PBD, UCF, and other files corresponding to the project. You can double-click on any file name to open it in the XPS main window. You must create some of these files in order to implement the design. The Project Options tree shows the current value set for various project options. You can double-click or right-click on any of the fields shown in this tree to open the Set Project Options dialog bo. The Reference Files tree shows log files and report files generated during tool eecutions. These files are seen only if they eist on disk. The tree also show a design summary file that is generated as a result of invoking Generate Design Report. Embedded System Tools Reference Manual 31 UG111 (v4.0) February 15,

32 Chapter 2: Xilin Platform Studio (XPS) Applications Tab The Applications tab shows all of your software application projects. You can create a number of projects that are associated with the processors in your design. A project consists of a unique project name and a set of source and header files that you can create to design your application. The source files can be built into eecutable files, one per application project, that can be downloaded onto the FPGA. If you have multiple applications but the current design is only going to require a subset of those applications, you should mark the other applications as Inactive. The XPS engine will ignore all Inactive applications. This enables you to preserve software applications and does not force you to delete those applications. You can specify each active application project with a set of compiler options. Right-click the application projects tree view to open a contet menu. The menu items can be invoked to set compiler options, view files, open files, associate different processors with the project, and so on. Each project can also be marked for initialize BRAMs. If your application resides completely in BRAM memory and you want to download its ELF file as part of the bitstream, then those applications must be marked to initialize BRAMs. XPS uses data2mem to update the bitstream with those ELF files. For every processor in the design, an application project called <processor instance>_bootloop is created by default. This is a predefined bootloop that can be downloaded to the BRAMs so that the processor is in a valid state on wakeup. To open the source file with more comments eplaining the importance of the bootloop, right-click on the bootloop name and select View Source. For more information, refer to Software Application Management on page 35. Transcript Window Platform Management The transcript window is located at the bottom of the XPS main window. This window acts as a console for output, warning, and error messages from XPS and other tools invoked by XPS. Error, warning, and output messages are separated in tabbed windows. Click the Error and Warning links to open answer records for that particular error or warning. You can also right-click or double-click on an error that has a filename and line number associated with it and navigate to that file in the editor. To change the system specification, software settings, and simulation options, XPS supports the following features and processes: Add/Edit Cores Dialog Bo Add SW Application Project Simulation Models View MPD View MLD View MDD View Core Modifications View PDF Doc View Core License Status S/W Settings 32 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

33 Platform Management R Add/Edit Cores Dialog Bo To open the Add/Edit Cores dialog bo, select Project o Add/Edit Cores (dialog). The Add/Edit Cores dialog bo lists all of the cores which you can instantiate in your design. You can select multiple cores to add to the design by holding down the Shift or Ctrl keys. You can also use the tabbed pages to add and connect buses, connect BRAMs to BRAM controllers, add ports, and connect using net names and set parameters on cores. Refer to the Microprocessor Peripheral Description (MPD) and Microprocessor Hardware Specification (MHS) chapters of the Platform Specification Format Reference Manual for parameter information. Add SW Application Project To add a software application project to the system, select Project o Add SW Application Project. The Add SW Application Project dialog bo allows you to create a new software application project. XPS supports multiple software application projects. Refer to Software Application Management on page 35 for more information. Simulation Models View MPD View MLD View MDD To set the simulation model for your system, right-click on System BSP in the System tab and point to Simulation Models. Select the type of simulation: Behavioral, Structural, or Timing. The currently selected model displays a check mark net to it. This information is stored in XMP file. For more information about simulation models, refer to Simulation Models on page 107. To view the Microprocessor Peripheral Definition (MPD) file for a core, right-click on the core name and select View MPD. The MPD file for that core opens in the main window. If the MPD file is already open, the focus changes to that file. MPD files open in read-only mode and cannot be edited. To view the Microprocessor Library Definition (MLD) file for a library or operating system (OS), right-click on the library or OS name and select View MLD. The MLD file for that library or OS opens in the main window. If the MLD file is already open, the focus changes to that file. MLD files open in read-only mode and cannot be edited. To view the Microprocessor Driver Description (MDD) file for a driver assigned to a core instance, right-click on the instance name and select View MDD. The MDD file for that instance opens in the main window. If the MDD file is already open, the focus changes to that file. MDD files open in read-only mode and cannot be edited. Embedded System Tools Reference Manual 33 UG111 (v4.0) February 15,

34 Chapter 2: Xilin Platform Studio (XPS) View Core Modifications View PDF Doc To view the core modifications for a core instance, right-click on the instance name and select View Core Modifications. The change log for the core opens, with changes from previous versions of the core. To view the PDF document for a core instance, right-click on the instance name and select View PDF Doc. The PDF document opens in a new window, displaying the datasheet for that particular version of the core. View Core License Status S/W Settings To view the core license status of an instance, right-click on the instance name and select View Core License Status. You can view the core license status for purchased cores only; this option is disabled if the core does not need to be purchased. A dialog bo opens displaying the relevant license information for that particular core. To configure software platform options for all peripherals, right-click any peripheral instance name and select S/W Settings. The Software Platform Settings dialog bo opens with three tabs: Software Platform, Processor and Driver Parameters, and Library and O/S Parameters. You use this window to specify all of the software platform related options in your design. The following sections describe each tab in detail. Software Platform The Software Platform tab shows three tables: Drivers, Libraries, and Kernel and Operating Systems. The Drivers table displays peripherals used in the design. You use this table to assign drivers for these peripherals. Drivers might already be assigned by default, but you can change the default drivers. The Libraries table shows all of the libraries that are included in EDK. To include a library in the design, click to place a checkmark in the Use column. In the Kernel and Operating Systems table, you select an operating system (OS) for the processor system in the design. The default OS selection is standalone. For more information, refer to the Microprocessor Software Specification (MSS) chapter of the Platform Specification Format Reference Manual. Processor and Driver Parameters The Processor and Driver Parameters tab shows two tables, Processor Parameters and Driver Parameters. You can use these tables to specify values for the parameters associated with the processors or peripheral drivers in the design. The driver table also displays an interrupt handler parameter if the peripheral using the driver is connected to an interrupt port. You can specify the name of the interrupt handling routine for any peripheral interrupt signal. If the peripheral has no interrupt port or if those interrupt ports are not connected to any signal in the MHS file, then this parameter does not appear. Refer to the Microprocessor Driver Definition (MDD) chapter of the Platform Specification Format Reference Manual for more information Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

35 Software Application Management R Library and O/S Parameters The Library and OS Parameters tab displays a list of all configurable library and Kernel/OS parameters for all the libraries and OS s in the design. Refer to the Microprocessor Library Definition (MLD) chapter of the Platform Specification Format Reference Manual for more information. Software Application Management The MSS file specifies the software platform for the embedded system design. This includes the OS, drivers for IPs, and other libraries. You can run multiple applications on a single software platform. XPS allows you to specify multiple application projects. An application project is a logical collection of source files and header files and a linker script. You create and manage applications on the Applications tab. Each application is associated with a processor instance that eecutes the application. You must specify a unique name for each application project. An application project has a list of C source and header files associated with it. You can also specify compiler options for each application. All of the source files for a processor are compiled using the compiler specified for that processor in the software platform settings for that processor. XPS has an integrated editor for viewing and editing C source and header files in your program. You can mark any application Active or Inactive by right-clicking the application name. Active applications are only considered for actions such as building, debugging, and downloading to the board. Xilin recommends using the Eclipse-based Software Development Kit (SDK) bundled with EDK for large software applications. SDK provides a convenient integrated environment for building, debugging, and downloading software applications. Adding Files You can add files to an active software application by right-clicking on the Sources or Headers item in the application project. Add multiple files by pressing the Ctrl key and using the arrow keys or the mouse to select files in the file selection dialog bo. XPS adds files to Sources or Headers subtree based on the file etension. All directories where the header files are present are automatically added to the Include Search Path compiler option. Deleting Files from Project You can delete any file from a software application by selecting the file in the Project View window and then right-clicking on the item and selecting Delete File. The file does not get physically deleted from the disk; it is just removed from the list of files to be compiled when generating the eecutable for that application. Editing Files Double-clicking on the source or header file in the Project View window opens the file for editing. The editor supports basic editing functions such as cut, paste, copy, and search and replace. The editor highlights basic source code synta. It also supports file management and printing functions such as saving, printing, and print previews. Embedded System Tools Reference Manual 35 UG111 (v4.0) February 15,

36 Chapter 2: Xilin Platform Studio (XPS) Mark Application for Downloading to BRAMs Active software application Eecutable Linked Format (ELF) files that reside in an FPGA s BRAM memory must be marked for downloading into BRAMs. You can do this by rightclicking the software application and selecting Mark for Download. Similarly, you can deselect the application for downloading to BRAMs. If an application is marked for BRAMs, XPS passes these applications to the data2mem utility, which initializes the bitstream with BRAM information from the ELF files. XPS also passes these ELF files to Simgen to create appropriately initialized simulation models. By default, a software application is assumed to be using BRAMs. By marking an application for download to BRAMs, no process gets invoked, but a flag is set up to indicate that the application must be downloaded at the proper moment in the flow. Application to be Compiled Outside of the XPS Environment You might want to compile your application outside of the XPS environment, such as in VWorks or Eclipse, but want XPS to be aware of the ELF file. In such case, create an application project and specify the ELF file created outside XPS, but do not add any C- source files associated with it. This indicates to XPS that you have an associated ELF file, but that you do not want to compile it within XPS. Any changes that might require you to recompile your application, such as a change in an MHS or MSS file, must be managed individually. Bootloop Software Applications For each processor, XPS adds a special bootloop software application. These applications have a precompiled ELF associated with them. You can find the pre-compiled ELF and the source file, linker script, and make file used to compile the ELF in the EDK installation directory. These applications are displayed at the top of the Software Applications tree. You cannot modify sources and compiler options for these applications; you can only select to download this application into BRAMs. The bootloop application is a simple single-instruction application. The instruction branches to itself, creating an infinite loop. This is useful in cases where the processor has started eecuting but the actual application has not been downloaded to eternal memory. The bootloop prevents the processor from eecuting arbitrary instructions. This application resides at the start address location of the processor. For MicroBlaze the start address is , and for PowerPC it is 0FFFFFFFC. XMDStub Software Applications For every MicroBlaze processor in design, an application called <processor_instance>_mdstub is created by XPS. The ELF file associated with this processor is created as part of the library generation at the location of <proc_instance>/code/mdstub.elf. You can decide whether to download this application or not. Typically, if any of your applications are in XMDSTUB mode, then you should download mdstub.elf for that processor onto BRAM memory. Compiler Options The Compiler Option dialog bo opens when you double-click the name of any active software application or when you select the Set Compiler Option menu option for that software application in the Applications tab of the Software Projects tree. This dialog bo contains the following four tabs Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

37 Software Application Management R Environment The Environment tab displays the compiler being used for compiling this application. You can change which compiler is used in the Software Platform Settings dialog bo. For a MicroBlaze application, you can specify what mode the application should be compiled into, XMDSTUB or EXECUTABLE. On the Environment tab, you can provide Program Start Address, Stack Size, and Heap Size for the gcc-based compilers, mb-gcc, and powerpc-eabi-gcc. Do not use these options with dcc; they should be specified in the linker script for dcc. These options are ignored if you are using a custom linker script rather than the default one. Optimization The Optimization tab allows you to specify various compiler options. The degree of optimization can be specified to be 1, 2, or 3. You can specify whether to perform Global pointer optimizations. Also, if you included the ilprofile library in the Software PlatForm Settings dialog bo, then you also choose whether to enable profiling for this application or not. You also choose the debug options: whether the code should be generated without debug symbol, with symbols for debugging (-g), or with symbols for assembly (-gstabs). Directories The Directories tab allows you to specify various search directories for the Compiler (-B), for Libraries (-L), and for Include (-I) files. You can specify what libraries, if any, should be used by the linker in the Libs to Link (-l) field. The libil.a library is automatically picked up by gcc- based compilers. For dcc, XPS automatically adds il as a library to link in the makefile compiler options. You specify any Linker script, sometimes called map file, to use. Again, the gcc-based compilers pick up the default linker script from the EDK installation area if this option is not specified. You can also specify the name of the Output ELF file to be generated by the compiler. If these paths are not absolute, they must be relative to the project directory. Advanced In the Advanced tab, you specify various options which the compiler should pass to the Preprocessor (-Wp), the Assembler (-Wa), and the Linker (-Wl). Each option is discussed in detail in Chapter 13, GNU Compiler Tools. You do not need to type in the specific flags, as XPS automatically introduces the correct flag for each option. However, if you type the flags, then XPS does not introduce them. If there are more than one options in a field, they should be separated by spaces. For compiling program sources, if you want to specify any Compiler Options in addition to those specified in other tabs, you can specify them in the Program Sources Compiler Options edit bo. Embedded System Tools Reference Manual 37 UG111 (v4.0) February 15,

38 Chapter 2: Xilin Platform Studio (XPS) Table 2-2 shows the options that are displayed in the tabs of the Compiler Options dialog bo. Table 2-2: Processor Options Option Value Type Description Compiler Options Optimization Level Choose the level of compiler optimization. Equivalent to -O option in gcc. Global Pointer Optimization For more information on the options, refer to Chapter 13, GNU Compiler Tools. Generating Linker Scripts The Generate Linker Script dialog bo opens when you select the Generate Linker Script menu option for that software application in the Applications tab of the Software Projects tree. This dialog bo has the following configuration information. Sections View Compiler Option This option enables global pointer optimization in the compiler. This option is only for MicroBlaze. Debug Compiler Option The -g option to generate debug symbols. Search Paths Directories Compiler, Library, and Include paths. Equivalent to -B, -L and -I option to gcc. Libraries to Link Linker Option The libraries to link against while building the ELF file (-l option) Output File File path and name Sets the name of the eecutable file. Equivalent to -o option of gcc. Program Start Address He Value Specifies the start address of the tet segment of the eecutable for MicroBlaze and the program start address for PPC. Stack Size He Value Specifies the stack size in bytes for the program. Heap Size He Value Specifies the heap size in bytes for the program. Pass Options Compiler Options Options can also be passed to the compiler, assembler and linker. The options have to be space separated. The Sections view displays the list of sections associated with the software application. If an ELF file is present for the software application, then the section view is populated from the ELF file settings. Each section has the size and memory assignment information. If the ELF file is not present, then the default sections for the processor that are associated with the software application are listed. Each section listed can be mapped to any specific memory Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

39 Flow Tool Settings and Required Files R Memory View The Memory view displays the list of all memories associated with the processor instance of the software application. Memory information includes the instance name used in the MHS file, the start address of the memory, and the size of the memory. The view is readonly; therefore, you cannot edit any of the fields. Heap and Stack View The Heap and Stack view displays the heap and stack information associated with the software application. If an ELF file is present for the software application, then the heap and stack view is populated from the ELF file settings. If the ELF file is not present, then the default value for each of stack and heap are assigned. The stack and heap can each be configured for size and memory assignment. ELF File Information The ELF file used in pre-populating both the Sections view and the Heap and Stack view is shown here. The ELF file is the eecutable associated with the software application. Output Linker Script The Output Linker script file name is the name of the file specified for linker script in the Set Compiler Option menu. If a valid linker script file eists, then it is copied in as <original_linker_script_file.bak> before generating the linker script in the file <original_linker_script_file>. Add/Delete Sections Besides the list of the sections listed in the Sections View, you can add new sections. Click Add Section to create an etra row in the Sections view. You can configure the name of the section and the memory assignment. To delete a newly added section, select the section s row and then click Delete Section. The newly added section is removed. You cannot delete the default sections retrieved either from the ELF file or assigned based on the target processor instance. Generate Once all of the settings are configured, click Generate to generate the linker script. If there are any errors in the settings, relevant error messages display in the transcript console at the bottom of XPS. Once a valid linker script is generated, the software application must be built in order for the settings to be preserved. A generated ELF file retrieves the settings on the net run of Linker Script Generator. Flow Tool Settings and Required Files XPS supports tool flows as displayed in Table 2-1 on page 29. The Main menu has an Options submenu. You can set various project and tool options, as described below for each menu item. Compiler Options The Compiler Options menu opens the same dialog bo as when you double-click on a software application name. If there is a single application in your system, it automatically opens the dialog bo corresponding to the application; otherwise, you will be asked which software application you want the options to be set for. You can set various compiler options in the Processor dialog bo that opens. Embedded System Tools Reference Manual 39 UG111 (v4.0) February 15,

40 Chapter 2: Xilin Platform Studio (XPS) Project Options Select Options o Project Options to open a dialog bo in which you can specify various project options. You can open this dialog bo by clicking the Project Options toolbar button or by double-clicking any item in the Project Options tree in the Project View window. There are three tabs in this dialog bo. Device and Repository Use this tab to change the target device for the project. There are four different items: Architecture, Device Size, Package, and Speed Grade. You can specify the Search Path directories here. However, if this option is changed, you must close the project immediately. If this option is changed here, the changes are effective only after the project is closed and loaded again. This option corresponds to the -lp option of various batch tools. Refer to Chapter 7, Library Generator and Chapter 5, Platform Generator for more information. You can specify your own Makefile for XPS. Before EDK 6.2, XPS generated only a single makefile called <projname>.make. Currently, the XPS makefile is split into two parts: The main makefile: <projname>.make The include makefile: <projname>_incl.make. The <projname>_incl.make file contains all options and settings defined in the form of macros. The main makefile <projname>.make contains all the targets and commands for the complete flow. The main makefile includes the <projname>_incl.make using the following make directive: include system_incl.make This makes all of the macros defined in <projname>_incl.make visible in <projname>.make. XPS always writes out both the makefiles. However, you can choose not to use the <projname>.make file for your flow. Instead, you can specify your own makefile. The makefile specified must be named differently from the two makefiles generated by XPS. You are epected to include the <projname>_incl.make in your own makefile as well. This way, any changes you make to any options and settings in XPS are reflected in your own makefile. Typically, you would generate the <projname>.make file once and then copy and modify it for your own purposes. You must update your makefile whenever you make a significant change in your design. The following changes affect makefile structure: Adding, deleting, or renaming a processor Adding, deleting, or renaming a software application Changing the choice of implementation tool between ISE (ProjNav) and XPS (Xflow) The ACE file generation command might be changed if you change the number of processors in your design or if you add or delete opb_mdm ip for MicroBlaze designs. The XILINX_EDK_DIR macro defined in system_incl.make file changes across Uni (Solaris/Linu) and Windows platforms Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

41 Tool Invocation R Tool Invocation Hierarchy and Flow Use this tab to specify the design hierarchy: whether the processor design being done in XPS is the top level module or if it is just a sub-module in the entire hierarchy. If this design is a sub-module, the Top Instance edit bo allows you to specify the instance name used to instantiate this module in the top-level design. This corresponds to the -iobuf and -ti options in Platgen. In EDK 6.1 and above, XPS only supports modular (hierarchical) design mode. The Flat mode is not supported. You can choose whether to run the Xilin Synthesis Tool (XST). You can also specify the flow to use for running the Xilin implementation tools. The available options are XPS (Xflow) and ISE (Project Navigator) flow. If the design is a submodule, you must use the ISE flow. Refer to ISE Project Navigator Interface on page 43 for details on how to add design components and files to a ProjNav project using XPS. HDL and Simulation This tab allows you to specify the HDL (VHDL or Verilog) to be used by Platgen and Simgen. You can also specify the location of various simulation libraries. For details on simulation libraries, refer to Chapter 6, Simulation Model Generator. You can specify the simulation tool of your choice. Currently, EDK supports ModelSim and NCsim. You can also specify the current simulation mode that you want to use. These options are saved into the XMP file. Required Files If Xflow is chosen to run the implementation tools, XPS epects a certain directory structure in the project directory. For each project, you must provide the User Constraints File (UCF). This file resides in the data directory in the project directory and has the name <mhs_name>.ucf. You must also provide an impact script file. This file resides in the etc directory and is called download.cmd. If these files do not eist, XPS prompts you to provide these files and will not run XFlow. To run Xilin Implementation tools, XPS uses two more files, bitgen.ut and fast_runtime.opt from the etc directory. However, if the two files are not present, XPS copies the default version of these two files into that directory from the EDK installation directory. To change options for Xilin implementation tools, you can modify the two files. When a new project is created, if the data and etc directories do not eist, XPS creates these empty directories in the project directory. After all options for the compiler and library generator are set, you can invoke the tools by selecting from the Run submenu in the Main menu. The main toolbar also contains buttons to invoke each tool. There are two different flows in the EDK platform building flow: the hardware flow and the software flow. Embedded System Tools Reference Manual 41 UG111 (v4.0) February 15,

42 Chapter 2: Xilin Platform Studio (XPS) Software Flow The software flow involves building up the software part of the embedded system. 1. Click the Generate Libraries toolbar button. This button opens the library building tool, Libgen, with the correct MSS file as input. 2. Click the Build All User Applications toolbar button. This button opens the compiler for each software application that must be compiled within XPS. It builds the eecutable files for each processor. If Libgen has not run, this button opens it. 3. Select Tools o Generate Linker Script. A dialog bo opens allowing you to generate a custom linker script for any software application. Refer to Generating Linker Scripts on page Click the Launch Platform Studio SDK toolbar button. The Eclipse based SDK bundled with the EDK opens. This platform allows you to create, compile, debug, and download software applications in an integrated environment. Hardware Flow The hardware flow involves building the hardware part of the embedded system. 1. Click the Generate Netlist toolbar button. The platform building tool, Platgen, opens with the correct MHS file and produces the netlist files in NGC format. 2. If you are using XPS for implementation tools, click the Generate Bitstream toolbar button. XPS calls Xflow with the fast_runtime.opt and bitgen.ut files residing in the etc. directory in the project directory. XFlow calls the Xilin ISE Implementation tools. If you are using ProjNav for the implementation flow, this button is greyed out. 3. Select Tools o Eport to ProjNav to add the XPS files into a ProjNav project. 4. Run the complete flow in ProjNav, and then select Tools o Import from the ProjNav menu to import the bitstream and BMM files back into the flow. 5. Select Tools o Create/Import Peripheral. The Create/Import Peripheral Wizard opens. Refer to Chapter 4, Create and Import Peripheral Wizard, for more information. 6. Select Tools o Configure Coprocessor. The Coprocessor Wizard opens. Use the Coprocessor Wizard to attach Fast Simple Link (FSL) based coprocessors to MicroBlaze and PowerPC (on Virte -4 devices). To create a new coprocessor, use the Create and Import Peripheral Wizard and select FSL bus interface. For more information, refer to Chapter 4, Create and Import Peripheral Wizard Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

43 Tool Invocation R Merging Hardware and Software Flows and Downloading 1. Click the Update Bitstream toolbar button. The bitinit tool opens. This is the stage where the hardware and the software flows come together. Hardware and software flow tools are also invoked if sources are out of date. At the end of this stage, a download.bit file is generated, which contains information regarding both the software and the hardware part of the design. 2. Select Tools o Generate SystemACE File. A SystemACE file generates. This option is available only when you have a single processor in your system. This option is available only on Windows and Linu platforms in this release. There is no toolbar button for this option. 3. Select Tools o Program Flash Memory. The Flash Writer dialog bo opens to help you program flash memory in the hardware system. An EMC peripheral is required for this action. 4. Click the Download Bitstream toolbar button. The download.bit file downloads onto the target board using the Xilin impact tool in batch mode. XPS uses the file etc/download.cmd to download the bitstream. 5. Select Tools o Generate Design Report. The design report generator tool opens to create a design summary in an easily readable HTML format. The HTML report contains design specifics such as device, cores used, bus and port connectivity, and IP configurations. The HTML report generated is visible in the main XPS window. XPS generates a makefile in the project directory and calls the corresponding target. The dependencies between various tools being run is taken care of by the Makefile. When Libgen is run, an MSS file is created for the software specification. When you eit the application, a prompt opens, asking you to save the current project. ISE Project Navigator Interface If ISE (ProjNav) is chosen for implementation flow in the Project Options dialog bo, then you must specify the ProjNav project (NPL) file. ProjNav runs implementation tools in the directory where this ProjNav project file is created. The default NPL file location is <proj_dir>/projnav/<proj_name>.npl. Xilin recommends that you not use the implementation directory for ProjNav flow since XPS clean mechanism deletes this directory. To run the ProjNav flow, you can create a new ProjNav project file or specify one that already eists. Select Tools o Eport ProjNav Project to add the required VHDL and BMM files to the ProjNav project. This also sets the ProjNav option Macro Search Path to <proj_dir>/implementation so that implementation tools can locate NGC files generated by Platgen or XST. Select Tools o Import from ProjNav for the option to import a bitstream and a BMM file back into the XPS Project. The bit file should be the one generated by Bitgen at the end of implementation tools. The BMM file should also be the one generated by Bitgen, which has BRAM placement information. XPS copies the bit and bmm files into the implementation directory as <mhsbasename>.bit and <mhsbasename>_bd.bmm, respectively. Embedded System Tools Reference Manual 43 UG111 (v4.0) February 15,

44 Chapter 2: Xilin Platform Studio (XPS) Debug and Simulation PBD Editor You can debug the software part of the design either by simulation or by running it on the hardware itself. XPS provides support for invoking the corresponding tools to perform the job. Xilin Microprocessor Debug (XMD): Run the XMD tool to debug the application software. The XMD toolbar button opens an XMD shell in the project directory. Software Debugger: The Debug toolbar button invokes the software debugger corresponding to the compiler being used for the processor. If there are more than one processor in the design, XPS prompts you to choose the processor whose program sources you want to debug. Hardware Simulation Model Generator (Simgen): Invoke Simgen to generate various simulation models for the components instantiated in the MHS file. Depending on the simulation model to be used (Behavioral, Structural or Timing), XPS calls Simgen with appropriate options to generate the simulation models and initialize memory. Then XPS compiles those models for ModelTech s ModelSim simulator and starts the simulator with the compiled files. Generate Virtual Platform: This menu item generates the Virtual Platform, which is a cycle-level simulation model of the hardware platform. Refer to Chapter 8, Virtual Platform Generator, for more information. The PBD Editor allows you to read, create, modify, and save a description of an FPGA Platform that references Hardware (HW) components. The HW components comprise, in part, microprocessors, buses and bus arbiters, and peripheral devices. The PBD Editor block diagram supplies the hardware platform information written into the MHS file. To open the PBD Editor, select Project o View Block Diagram. PBD Editor Interface The PBD Editor interface is comprised of the PBD Editor Workspace and the System Tabs. PBD Editor Workspace The PBD Editor workspace is the upper right window in XPS. The workspace contains a block diagram describing the system hardware. System Tabs The system tabs are in the upper left of the XPS window. Two of the tabs in the window are used in the PBD Editor operation: The Options tab changes according to the tool that you are using and allows you to set options related to the tool, such as how the Add Bus Connection tool should operate. The Components tab allows you to select a component such as a CPU, Bus Infrastructure component, or peripheral to instantiate into your system. The components are Xilin cores Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

45 PBD Editor R Creating the Hardware Block Diagram Use the following procedures to create the hardware platform in the PBD Editor. Adding a Component Instance to the System Component instances are Xilin cores (IP) instantiated in the hardware design. You can add the following components to the system. CPUs Bus components Peripherals To add a component instance to the system: 1. Select the project_name.pbd tab in the workspace to display the system block diagram. 2. Select Add o Component or click the Add Component toolbar button. 3. In the Components tab, use the Categories and Components lists to specify which component you want to add. The component that you select moves with your mouse cursor. Note: To make the component selection easier, type the first few letters of the component in the Component Name Filter field. The Components list bo shows only the components that begin with those letters. A regular epression can also be used to filter components. For eample, typing.*uart will list all components with uart in the name. The. stands for a character and the * means zero or more. 4. Click where you want the component instance to appear in the workspace. Component instance notes: The PBD Editor assigns the new component instance the default name corename_number. The number is incremented each time another instance is added. To rename a component instance, see the following section, Naming an Instance. If a bus pin on the component symbol touches a bus, and if the pin is compatible with the bus type, the symbol pin is connected to the bus when the component instance is placed in the block diagram. Naming an Instance When you add a component to the system, the PBD Editor assigns the new component instance the default name corename_number, and the number is incremented each time another instance is added. You can leave the machine-generated names as is. However, it is usually easier to debug the design using your own names. To rename an instance: 1. Double-click the instance in the workspace. 2. In the Object Properties dialog bo, type a name in the Instance Name field. Embedded System Tools Reference Manual 45 UG111 (v4.0) February 15,

46 Chapter 2: Xilin Platform Studio (XPS) Setting Component Instance Parameters You set parameters to customize the instantiated IP for your design. You can set parameters for CPUs, bus components, or peripherals. The properties you set depend on the type of component and the IP (core) from which the component was instantiated. IP parameters are described in the data sheets for the cores instantiated in the design. You can find data sheets on the Xilin IP Center page at To set parameters for a customizable component instance: 1. Double-click the component in the workspace. The Object Properties dialog bo opens. 2. Click Parameters in the tree view on the left side of the dialog bo. 3. Override a value displayed in the Default Parameter Values table as follows: a. Select the parameter in the Default Parameter Values table. b. Click Add. The parameter is added to the Eplicit Parameter Values table. c. Change the value of the parameter in the Eplicit Parameter Values table. d. Click Apply. The value entered in the Eplicit Parameter Values table overrides the value displayed in the Default Parameter Values table. Setting Symbol Properties Symbol properties determine the appearance of an instance s block in the workspace. You can modify the size of the symbol drawing or the location of the bus pins on the symbol. Some components, such as the MicroBlaze processor, have a large number of bus interfaces, only a few of which can be used in the block diagram. You can hide the bus interface pins that are not in use, reducing the size of the symbol and making the diagram easier to read. To set symbol properties: 1. Double-click the component in the workspace. The Object Properties dialog bo opens. 2. Click Symbol in the tree view on the left side of the dialog bo. 3. Change the size of the symbol by doing the following (optional): a. Select values in the Min Width and Min Height fields. b. Click Add. 4. Change the orientation (top, bottom, left, or right) of a symbol pin by doing the following (optional): a. Select the pin in the Available Pins table. b. Click Add. c. At the top of the Pins on Symbol area, select the orientation you want: Top, Bottom, Left, or Right. d. Click Apply. The symbol in the workspace updates to reflect the change Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

47 PBD Editor R Connecting a Component Bus Pin to a Bus When you connect a component bus pin to a compatible bus, connection lines are drawn from the pin to show the bus connection. All of the signals represented by the bus pin are connected to the bus. To connect a component bus pin to a bus: 1. Select Add o Bus Connection or click the Add Bus Connection toolbar button. 2. Select the bus pin on the component instance that you want to connect to the bus. To select the pin, move the cursor near the end of the pin until four squares appear to help you locate the eact point. When the cursor is in the correct position to select the pin, a bo appears with information about the component instance and the type of pin that you are selecting. 3. Click anywhere on the bus to which you will connect the pin. If the type of bus is compatible with the type of pin, connection lines appear, showing the bus connection. Connecting Ports You can create nets to connect ports on component instances. To create a net, you assign the same net name to all of the ports that you want to connect. Port connections cannot be seen as nets drawn on the block diagram. All of the nets shown on the block diagram are bus connections. To connect ports on two component instances: Note: This procedure describes how to connect a port on one component instance to a port on another component instance. Using a similar procedure, you can connect ports on more than two component instances, connect multiple ports at the same time, or create system ports. 1. Double-click one of the component instances you want to connect. The Object Properties dialog bo opens. 2. Click Ports in the tree view on the left side of the dialog bo. 3. In the Show Ports drop-down list, select the type of ports to show in the ports list: With No Default Nets, With Default Nets, All Ports, or New Filter. 4. If you select With Default Nets, the ports need not be connected; they are automatically connected by Platgen. You must connect these ports only when the connection is not desired. 5. In the Show Ports list, select the a port to which you will assign a net. 6. Click Add. The selected port is added to the Eplicit Port Assignments list. 7. In the Eplicit Port Assignments list, modify the fields describing properties such as Polarity and Range, and assign a name to the net connected to the port in the Net Name field. 8. Perform Steps 1 through 7 for each additional component instance. If you assign the same Net Name to a port on each component instance, the ports connect automatically. Embedded System Tools Reference Manual 47 UG111 (v4.0) February 15,

48 Chapter 2: Xilin Platform Studio (XPS) Viewing and Editing System Ports You can view and edit the all of the system ports, designated Eternal, in a single dialog bo. Using this dialog bo, you can also add power and ground ports to the system. To view and edit system ports: 1. Double-click an area in the workspace that does not contain any objects. 2. Do the following to add power or ground system ports to the design: a. Click Add. The Add Eternal Port dialog bo opens. b. Type a name in the Port Name field and select GND (net_gnd) or VCC (net_vcc). c. Click OK. 3. Edit the entries in the System Level Port Assignments table as desired. Some notes about the table: i Fields that you can edit are displayed in white; read-only fields are displayed in gray. i If you click the heading of a column, the entries in the column display in alphabetical order. If you click the column heading again, the entries in the column display in reverse alphabetical order. i You can remove a system port by selecting it and clicking Remove. 4. When you have finished your edits, click OK. Viewing and Editing All of the Ports in the System You can view and edit all of the ports in the system (internal and eternal) in a single dialog bo. Using this dialog bo, you can also print a port list or eport the ports as a Comma Separated Value (CSV) file formatted for the PBD Editor or for the Xilin Pinout and Area Constraints Editor (PACE) tool. To view and edit all of the ports in the system: 1. Select Add o Ports or click the Add Ports toolbar button. 2. If you want to print the System and Component Ports table, click Print. 3. If you want to eport the ports to a CSV file, do the following: a. Select the ports to eport. b. Click Eport. c. In the Eport Ports dialog bo, type or select the CSV File name, select an Output Format, and specify whether you want to eport All Ports or Selected Ports. d. Click OK Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

49 PBD Editor R 4. Edit the entries in the System and Component Ports table as desired. Some notes about the table: i Fields that the you can edit are displayed in white; read-only fields are displayed in gray. i If you click the heading of a column, the entries in the column display in alphabetical order. If you click the column heading again, the entries in the column display in reverse alphabetical order. 5. When you have finished your edits, click OK. Viewing and Editing Interrupts You can view and edit the interrupts driving a component. Not all components have interrupt ports, and most components that use interrupts have only one interrupt port. An interrupt can be driven by more than one net. If an interrupt is driven by multiple nets, you must specify the priority of each net driving the interrupt. To edit the interrupts driving a component instance: 1. Double-click the component in the workspace. The Object Properties dialog bo opens. 2. Click Interrupts in the tree view on the left side of the dialog bo. 3. From the Interrupt Port drop-down list, select the interrupt that you want to configure. 4. In the Possible Interrupt Nets list, select the nets that will drive the internet. To select multiple nets, click the first net name, then hold down the Ctrl key and click the additional net names. Note: If the interrupt port is a scalar port with a blank range, then you can select only one net to drive the interrupt. An interrupt controller must be used in such a case to manage the interrupts, and the controller s output port should be used as the single input to the component with the scaler interrupt port. 5. Click Add to move the nets to the Interrupt Drivers bo. 6. In the Interrupt Drivers bo, use the Move Up and Move Down buttons to list the nets in priority order. Nets higher in the list will be serviced before nets lower in the list. 7. Click OK. Embedded System Tools Reference Manual 49 UG111 (v4.0) February 15,

50 Chapter 2: Xilin Platform Studio (XPS) Editing the Block Diagram Selecting Objects To select objects in the workspace: 1. Select Edit o Select Object(s), or click the Select toolbar button. The Options tab displays the Select Options. 2. Set the following options: i Click Select the entire bus or Select the line segment to specify whether the bus or just the line is selected when you click a bus line. i Click Keep the connections to other objects or Break the connections to other objects to specify whether or not connections to other objects are retained when you move an object. i Click Are enclosed by the area or Intersect the area to specify which objects to select when you drag a bounding bo around an area. Are enclosed by the area selects only those objects that are completely enclosed in the bounding bo. 3. Click the object to select it. The PBD Editor also has the following etended selections: If you hold down the Shift key while you select an object, it is added to the current selections. If you hold down the Ctrl key while you select an object, its status is toggled. That is, it will be selected if it was not selected, or deselected if it was selected. Edit o Select All selects all objects on the current sheet. Edit o Unselect All unselects all objects on the current sheet. Viewing Object Information To view information about an object in the workspace, place the cursor over the object. A bo appears, supplying information about the object, such as name, IP name, and bus pin type. Zooming in the Workspace You can use menu commands to zoom the display in the workspace. Table 2-3: Zooming Behavior Zoom in Zooming Commands Menu Command Select View o Zoom o In, or click the Zoom In toolbar button. Toolbar Button Zoom out Select View o Zoom o Out, or click the Zoom Out toolbar button Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

51 PBD Editor R Table 2-3: Zooming Behavior Zoom to display the entire schematic or symbol in the workspace Zoom to an area you select Zoom to display selected objects at the highest magnification Zooming Commands (Continued) Drawing Non-Electrical Objects Menu Command Select View o Zoom o Full View, or click the Zoom Full View toolbar button. Select View o Zoom o To Bo, or click the Zoom To Bo toolbar button. Zoom in or out as follows: To zoom in, draw a bounding bo around the zoom-in area from the top left corner of the area to the bottom right corner. To zoom out, draw a bounding bo from the bottom right corner to the top left corner. 1. Select the objects you want to center in the workspace. 2. Select View o Zoom o To Selected, or click the Zoom To Selected toolbar button. Toolbar Button Non-Electrical Objects are graphic only and have no electrical meaning in the block diagram. In the PBD Editor, you can draw arcs, circles, lines, rectangles, and tet. Table 2-4: Object Toolbar Buttons Object Toolbar Button Arc Circle Line Rectangle Tet Embedded System Tools Reference Manual 51 UG111 (v4.0) February 15,

52 Chapter 2: Xilin Platform Studio (XPS) XPS No Window Mode To draw a non-electrical object: 1. From the Add menu, select the object that you want to draw, or click the toolbar button for the object. Object toolbar buttons are displayed in Table If any options appear in the Options tab for the object you selected, set the object s options. 3. Click anywhere in the diagram to start drawing the object. 4. Drag the cursor until the object is the appropriate size. 5. If necessary, move the cursor to adjust the object. For eample, when you draw an arc, you can move the cursor until the arc appears as you want it to display. You can draw as many objects as you want until you select another command. You can invoke the XPS no window mode by typing the command ps -nw at the command prompt. It provides functionality to generate MSS file, and makefiles, and run the complete XPS flow in batch mode. You can also create an XMP project file or load an XMP project file created by the XPS GUI. When invoking the batch mode for XPS, you can specify a Tcl script along with the -scr option. XPS sources the Tcl script and then provides a command prompt. You can also provide an eisting XMP file as input to XPS. XPS loads the project before presenting the command prompt. XPS batch provides the ability to query the EDK design database. New Tcl commands were added for this purpose. Available Commands XPS-Batch provides you a Tcl shell interface. You can use the commands in Table 2-5. Table 2-5: XPS-Batch Commands Command load [mhs mp new mss ] <filename> save [mss mp make proj ] set option <value> Description Loads the MHS or XMP file and opens or creates an XPS project. Updates the project with MSS file. Input <filename> is optional when loading MSS. You can create an empty project with suboption new. Saves the corresponding file. Option proj saves all files. Sets the value of a field (corresponding to option) to the given value. Refer to Setting Project Options on page 54. get option run option Displays the current value of the field (corresponding to option). Refer to Setting Project Options on page 54. Runs the makefile with the appropriate target. Refer to Eecuting Flow Commands on page Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

53 XPS No Window Mode R Table 2-5: XPS-Batch Commands (Continued) Command add_swapp <name> <procinst> del_swapp <name> add_swapp_progfil e <name> <filename> del_swapp_progfil e <name> <filename> set_swapp_prop_va lue <name> option <value> get_swapp_prop_va lue <name> option get_handle [mhs mss merged_mhs merged_mss] eit Description Adds a new software application with given name and associated with given processor instance. Deletes the given software application from the project. Adds the given program file to the given software application. Deletes the given program file from the given software application. Sets the value of a particular property of the given software application. Refer to Setting Options on a Software Application on page 57 for a list of options. Gets the value of a particular property of the given software application. Refer to Setting Options on a Software Application on page 57 for a list of options. Gets the handle to the MHS or MSS design, or to the merged MHS or MSS file. Closes the project and eits XPS. Creating a New Empty Project To create a new project with no components, use the command load new <basename>.mp XPS creates a project with an empty MHS file and also creates the corresponding MSS file. All of the files have same basename as the XMP file. If XPS finds an eisting project in the directory with same basename, then the XMP file is overwritten. However, if an MHS or MSS file with same name is found, then they are read in as part of the new project. Creating a New Project With Given MHS To create a new project, use the command load mhs <basename>.mhs XPS reads in the MHS file and creates the new project. The project name is the same as the MHS basename. All of the files generated have the same name as MHS. After reading in the MHS file, XPS also assigns various default drivers to each of the peripheral instances, if a driver is known and available to XPS. Embedded System Tools Reference Manual 53 UG111 (v4.0) February 15,

54 Chapter 2: Xilin Platform Studio (XPS) Opening an Eisting Project If you already have an XMP project file, you can load that file using the command load mp <basename>.mp XPS reads in the XMP file and loads the project. The project name will be same as the XMP basename. XPS takes the name of MSS file from the XMP file, if specified. Otherwise, it assumes that these files are based on the XMP file name. If the XMP file does not refer to an MSS file, but the file eists in the project directory, XPS reads that MSS file. If the file does not eist, then XPS creates a new MSS file. Reading an MSS File To read an MSS file, use the command load mss <filename> If you do not specify <filename>, it is assumed to be the file associated with this project. Loading an MSS file overrides any earlier settings. For eample, if you specify a new driver for a peripheral instance in the MSS file, the old driver for that peripheral is overridden. Saving Files and Your Project To save MSS files, XMP files, and makefiles for your project, use the command save [mss mp make proj] Command save proj saves all of the files. Setting Project Options You can set various project options and other fields in XPS using the set command. You can also display the current value of those fields by using get commands. The get command also returns the result as a Tcl string result which can be saved into a Tcl variable. The various options taken by the two commands are shown in Table 2-6. set option [value] get option Table 2-6: Options for set and get Commands Option Name Description arch dev package speedgrade searchpath [dirs] hier [top sub] topinst [instname] hdl [vhdl verilog] Set the target device architecture. Set the target part name. Set the package of the target device. Set the speedgrade of the target device. Set the Search Path as a semicolon-separated list of directories. Set the design hierarchy. Set the name by which the processor design is instantiated (if submodule). Set the HDL language to be used Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

55 XPS No Window Mode R Table 2-6: sim_model [structural behav ioral timing] simulator [mti ncsim none] sim lib sim_edk_lib pnproj [nplfile] addtonpl synproj [st none] intstyle Set the current simulation mode. Set the simulator for which you want simulation scripts generated. Set the simulation library paths. For details, refer to Chapter 6, Simulation Model Generator. Set the ProjNav Project file where designs will be eported. If the NPL file eists, specify whether XPS should add to that file or overwrite it. Set the synthesis tool to be st or none. Set the instyle value. usercmd1 Set the user command 1. usercmd2 Set the user command 2. pn_import_bit_fil e pn_import_bmm_fil e reload_pbde main_mhs_editor user_make_file ucf_file Options for set and get Commands (Continued) Set the bit file to be imported from ProjNav. Set the BMM file to be imported from ProjNav. Set the GUI option to reload PBDE or recreate it every time. Set the GUI option about main_mhs_editor. Specify a path to your make file. This file should not be same as the makefile generated by XPS Specify a path to the UCF file to be used for implementation tools. Eecuting Flow Commands You can run various flow tools using the run command with appropriate options. XPS creates a makefile for the project and runs that makefile with the appropriate target. XPS generates the makefile everytime the run command is eecuted. Valid options for the run command are shown in Table 2-7. get option Embedded System Tools Reference Manual 55 UG111 (v4.0) February 15,

56 Chapter 2: Xilin Platform Studio (XPS) Table 2-7: Options for Command Run Option Name netlist bits libs bsp program init_bram ace simmodel sim vp download eporttopn importfromp n netlistclea n bitsclean hwclean libsclean programclea n swclean simclean vpclean clean resync assign_defa ult_drivers Generate the netlist Description Run Xilin Implementation tools flow and generate the bitstream Generate the software libraries Generate the VWorks BSP for the given ppc405 system Compile your program into ELF files Update the bitstream with BRAM initialization information Generate the SystemACE file after.bit file is updated with BRAM info Generate the simulation models without running the simulator Generate the simulation models and run the simulator Generate the virtual platform Download the bitstream onto the FPGA Eport the processor design to ProjNav Import.bit and.bmm files from ProjNav Delete the NGC/EDN netlist Delete the.bit,.ncd, and.bmm files in the implementation directory Delete the implementation directory Delete the software libraries Delete the ELF files Calls libsclean and programclean Delete the simulation directory Delete the virtualplatform directory Delete the all tool-generated files and directories Update any MHS file changes into the memory Assign default drivers to all peripherals in the MHS file and save to MSS file 56 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

57 XPS No Window Mode R Reloading an MHS File All EDK design files refer to MHS files. Any changes in MHS files have impact on other design files. If there are any changes in the MHS file after you loaded the design, use the command run resync This causes XPS to re-read MHS, MSS, and XMP files again. Adding a Software Application You can add new software application projects in an XPS batch using the add_swapp command. When adding a new software application, you must specify a name for that application and a processor instance on which that application runs. By default, XPS assumes that the ELF file related to a new software application is created at <swapp_name>/bin/<swapp_name>.elf. This can be changed once the application has been created. add_swapp <swapp_name> <proc_inst> Deleting a Software Application An already eisting software application can be deleted from project in the XPS batch using the del_swapp command. You must specify the name of the software application that you want to delete. del_swapp <swapp_name> Adding a Program File To a Software Application You can add any program file (C source or header files) to an eisting software application using the add_swapp_progfile command. The name of the swapp to which the file must be added and the location of the program file must be specified. XPS automatically adds it as a source or header based on the etension of the file. add_swapp_progfile <swapp_name> <filename> Deleting a Program File From a Software Application You can delete any program file (C source or header file) associated with an eisting software application using the del_swapp_progfile command. The name of the swapp and the program file location needs to be specified. del_swapp_progfile <swapp_name> <filename> Setting Options on a Software Application You can set various software application options and other fields in XPS using the set_swapp_prop_value command. You can also display the current value of those fields using the get_swapp_prop_value command. The get_swapp_prop_value command also returns the result as a Tcl string result. The various options taken by the two commands are shown in Table 2-8. set_swapp_prop_value <swapp_name> <option_name> [value] get_swapp_prop_value <swapp_name> <option_name> Embedded System Tools Reference Manual 57 UG111 (v4.0) February 15,

58 Chapter 2: Xilin Platform Studio (XPS) Table 2-8: Options for set_swapp_prop_value and get_swapp_prop_value Commands Option Name Description sources headers eecutable download procinst Displays a list of sources. For adding sources, use the add_swapp_progfile command. Displays a list of headers. For adding header files, use the add_swapp_progfile command. The path to the eecutable (ELF) file. Specify whether or not the ELF for this SwProj should be used for initializing BRAMs. Values are true or false. The processor instance associated with this software application. compileroptlevel Specify the compiler optimization level. Values can be from 0 to 3. globptropt debugsym searchcomp searchlibs searchincl lflags prepopt asmopt linkopt progstart stacksize heapsize linkerscript progccflags Specify whether to perform Global Pointer Optimization. Value can be true or false. The debug symbol setting. Value can be from none to two corresponding none, -g, and -gstabs options. The compiler search path option (-B). The library search path option (-L). The include search path option (-I). The libraries to link (-l). The options passed down to the preprocessor (-Wp). The options passed down to the assembler (-Wa). The options passed down to the linker (-Wl). The program start address. The stack size. The heap size. The linker script (-Wl, -T -Wl,<linker_script_file>) All other compiler options which cannot be set using the above options Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

59 XPS No Window Mode R Settings on Special Software Applications For every processor instance, there is a Bootloop application provided by default in XPS. For MicroBlaze instances, there is also an XMDStub application provided by XPS. The only setting available on these special software applications is to Mark for BRAM Initialization. You can use the set_swapp_prop_value. XPS no window mode will recognize <procinst>_bootloop and <procinst>_mdstub as special software application names. For eample, if the processor instance is mymblaze, then XPS recognizes mblaze_bootloop and mblaze_mdstub as software applications. You can set the init_bram option on this application. XPS% set mblaze_bootloop init_bram true XPS% set mblaze_mdstub init_bram false This assumes that there is no software application by the same name. If there eists an application with same name, then you will not be able to change the settings using the XPS Tcl interface. Therefore, in XPS no window mode, you should not create an application with name <procinst>_bootloop or <procinst>_mdstub. This limitation is valid only for XPS no window mode and does not apply if you are using the GUI interface. Closing a Project and Eiting XPS To close a project, use the eit command. This also saves the project and closes XPS. You can only work on a single project during a single eecution of the batch mode version of XPS. Limitations and Workarounds MSS Changes XPS-batch supports limited MSS editing. So, if you want to make any changes in the MSS file, you must hand edit the file, make the changes, and then run the load mss command to load the changes into XPS. You do not have to close the project. You can save the MSS file, edit it, and then just re-load it into the project with the load mss command. XMP Changes Xilin does not recommend that you change the XMP file by hand. XPS-batch supports changing of project options through commands. It also supports adding source and header files to a processor and setting any compiler options. Any other changes must be done from XPS. Embedded System Tools Reference Manual 59 UG111 (v4.0) February 15,

60 Chapter 2: Xilin Platform Studio (XPS) 60 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

61 Chapter 3 Base System Builder The Base System Builder (BSB) wizard helps you quickly build a working system targeted at a specific development board. Based on your board selection, the BSB offers you a number of options for creating a basic system on that board, including processor type, debug interface, cache configuration, memory type and size, and peripheral selection. For each option, functional default values are preselected in the wizard. If your target development is not available or not currently supported by the BSB, you can select the Custom Board option instead of selecting a target board. Using this option, you must specify the individual hardware devices that you epect to have on your custom board. To run the generated system on a custom board, you must enter the FPGA pin location constraints into the UCF file. BSB automatically inserts these constraints into the UCF file in the case where a supported target board is selected. When you eit the BSB, it creates a Microprocessor Hardware Specification (MHS) file and a Microprocessor Software Specification (MSS) file, and loads them into your XPS project. You can then further enhance the design in Xilin Platform Studio (XPS). The BSB also optionally generates one or more software projects. Each project contains a sample application and linker script that can be compiled and run on the hardware on the target development board. Each application is designed to illustrate system aliveness and perform simple and basic testing of some of the hardware. The contents of each test application might vary depending on the components in your system. XPS supports multiple software projects for every hardware system, each of which contains its own set of source files and linker script. This chapter contains the following sections: BSB Flow Limitations Embedded System Tools Reference Manual 61 UG111 (v4.0) February 15,

62 Chapter 3: Base System Builder BSB Flow Invoking BSB This section describes the steps that you will go through in the BSB wizard. The More Info button at the bottom of each page provides a detailed eplanation of the functions of that page. The steps of the BSB flow, listed here, are described in the following sections. 1. Invoking BSB 2. Selecting a Starting Point 3. Selecting a Target Development Board 4. Selecting a Processor 5. Configuring Processor and System Settings 6. Selecting Eternal Memories and I/O Devices 7. Adding Internal Peripherals 8. Configuring Software Settings 9. Generating the System and Address Map 10. Output Files 11. Eiting BSB You can run the BSB only when you create a new project in XPS. 1. Run the BSB by selecting File o New Project o Base System Builder. 2. In the Create New Project Using Base System Builder Wizard dialog bo, type or browse to the directory where you want to create a new project. Xilin recommends that you start with a clean directory, because any eisting project files, including the XMP, MHS, and MSS files, might be overwritten when your new project is created. Selecting a Starting Point There are two starting options in BSB: Create a new design or load an eisting BSB file. Create a New Design Select this option if you are using BSB for the first time or to create a new design in BSB. To create a new design, select the I would like to create a new design radio button Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

63 BSB Flow R Load an Eisting BSB File Select this option if you have previously used BSB to generate a BSB settings file. When you use BSB, it creates a BSB settings file upon eit and stores all of the selections that you made in that wizard session. When you load the file in a subsequent session, the BSB preloads all of the saved selections. You can generate an identical system by clicking Net through all of the wizard pages, or you can make changes to the BSB to generate a different system. A new BSB settings file is always created when you eit the BSB wizard, reflecting the final selections of your current session. This feature is useful if you want to create several projects with similar designs. Do not modify the BSB file. To load an eisting file, select the I would like to load an eisting.bsb settings file radio button. Note: The BSB settings file stores only BSB wizard selections and does not reflect any changes made to the system outside of BSB. For eample, adding or editing a core in XPS or manually editing the MHS file. Selecting a Target Development Board You begin your design by selecting a target development board. You can select an eisting board or create a custom board. Select an Eisting Board Board selection is indicated by the vendor name, board name, and revision number. A brief description of the currently selected board displays on this page, showing the Xilin FPGA device, memories, and IO devices available for that board. To select an eisting board, select the I would like to create a system for the following development board radio button. Then, select the vendor, name, and revision for the board using the appropriate drop-down lists. Create a System for a Custom Board If the target board is not available or not supported in the drop-down list on this page, you can select the Custom Board option. This option might require you to supply more information on subsequent wizard pages. To create a system for a custom board, select the I would like to create a system for a custom board radio button. Embedded System Tools Reference Manual 63 UG111 (v4.0) February 15,

64 Chapter 3: Base System Builder Selecting a Processor Currently, the Base System Builder supports two processors: MicroBlaze, a configurable soft processor implemented in FPGA logic, and the PowerPC 405 processor, a hardware device available only in some Xilin FPGA architectures. If PowerPC is unavailable in the FPGA device on your development board, this selection is disabled in the wizard. A brief description of the currently selected processor is displayed in Figure 3-1, along with an illustration of what a typical system using this processor might look like. If you selected the Custom Board option on the previous page, you must specify the actual FPGA device that you will use. If you selected a specific target board, the device information for the FPGA on that board is displayed but cannot be changed. Figure 3-1: Selecting a Processor Dialog Bo 64 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

65 BSB Flow R Configuring Processor and System Settings Based on which processor you selected on the previous page, you can configure some settings that are specific to the system and processor. System settings, displayed in Figure 3-2, include processor and bus clock frequencies. Allowable values might be restricted by the clock resources available on the target development board or the on-chip resources available in the FPGA device. If you are creating a custom board, you can specify the reference clock frequency available on the custom board as well as the polarity of the eternal reset switch. Processor-specific settings include debug interfaces, cache options, and configuration of any on-chip memory which communicate over a processor-specific bus. Figure 3-2: Configure Processor Dialog Bo Embedded System Tools Reference Manual 65 UG111 (v4.0) February 15,

66 Chapter 3: Base System Builder Selecting Eternal Memories and I/O Devices If you are using a specific target board, BSB determines what eternal memory and I/O devices are available on that board. Each device found is displayed in the wizard as a checkbo which if selected enables that device interface, as displayed in Figure 3-3. Figure 3-3: Configure IO Interfaces Dialog Bo If you are creating a custom board, you must specify all eternal memory and I/O devices for the custom board. The Add Device button opens the Add Device dialog bo, with which you can add a device. Any device added in this dialog bo is enabled. To remove devices, click the Remove button for that device. For all enabled eternal memories and I/O device interfaces either determined by the selected board or added in the Custom Board option, you select from a list of IP cores which can be used to control that memory or interface. BSB instantiates the selected core in the system, connects it to the appropriate bus, and automatically sets any parameters which are dictated by the on-board device that core is controlling. For ease of use, you cannot set most core parameter values in the BSB wizard. The BSB wizard is designed to select default parameter values which create a functional base system on a specific development board. If necessary, you can manually change the parameter values in the generated MHS file. If you are creating a custom board, Xilin recommends that you manually check the MHS file to ensure that the IP parameter is correctly set for the hardware devices on the custom board Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

67 BSB Flow R For each enabled device interface, BSB creates the necessary top-level system ports. If you are using a specific board, these ports are assigned to the correct FPGA pin locations in a generated UCF file. If you are creating a custom board, you must enter these pin locations manually into the UCF file before you can run this design on actual hardware. Depending on the number of devices on the board, the IO Devices Selection list might span across several wizard pages. Click Back to view or edit previous selections at any time while the wizard is active. If you are unsure about what IP core to use, click Data Sheet to view the data sheet of the currently selected core. Adding Internal Peripherals Internal peripherals are IP cores which do not communicate directly with any devices outside of the FPGA. Eamples of such peripherals are on-chip memory (BRAM) controllers and timers. To add internal peripherals, click Add Peripheral and select from a list of internal peripherals. To remove any selections added manually or by default, click Remove net to that device. Figure 3-4 displays a sample peripheral list in the Add Internal Peripherals dialog bo. Depending on the number of internal peripheral devices you add, the BSB might create additional wizard pages to display the current list. Click Back to remove or edit previous selections. The BSB instantiates all internal peripherals that are added to the system and connect them to the appropriate bus. It does not generate any top-level system ports for internal peripherals. Figure 3-4: Add Internal Peripherals Dialog Bo Embedded System Tools Reference Manual 67 UG111 (v4.0) February 15,

68 Chapter 3: Base System Builder Configuring Software Settings The BSB generates up to two sample applications for your hardware system. Each application includes one or more C source files and a linker script. The sample applications are intended to verify basic system aliveness and also provide an illustration of how to create a software project within an XPS project. The contents of each application might vary slightly depending on the components in the hardware system. If either of the applications cannot be generated for a specific system, such as if your system contains no memory, the checkbo for that application is disabled in the GUI. Memory Test The MemoryTest application includes a basic read/write access test to all writeable memories in the system that are not being used to hold a part of the application itself and do not reside on the reset vector address for the processor. If there are GPIOs in the system, the MemoryTest also includes function calls to read and write patterns to the GPIO devices. This application is designed to be small enough to run out of on-chip memory (BRAM) so that it can be included in the FPGA configuration bitstream and run upon power-up. If you select a standard output peripheral, then the generated application includes functional calls to print informational output to the selected device. Peripheral Test The PeripheralTest includes a basic self test for other non-memory peripherals in the system. A self test might not eist for all devices. If a self test is found in the driver for a device in the system, a function call to that self test is included in the PeripheralTest application. If no self tests are found for any of the peripherals in the system, the PeripheralTest checkbo is disabled in the GUI. The PeripheralTest is epected to be too large to fit in on-chip memory (BRAM) and must placed in eternal memory only. The PeripheralTest is not generated if there is no eternal memory in the system. If you select a standard output peripheral, the generated application includes function calls to print informational output to the selected device. For each selected application, a subsequent wizard page displays, allowing you to select the memory devices in which to place the instruction, data, and stack/heap sections of the application. Generating the System and Address Map Before generating the output files, the BSB displays a summary of the system you created, as shown in Figure 3-5. This page contains a table of IP cores which are instantiated in the system and the address map for these devices. The device addresses generated by BSB conform to addressing requirements of each IP core and cannot be modified in the BSB. You can manually change the address values in the generated MHS file. To avoid entering illegal address values, consult the data sheets for individual IP cores. Click Back to make changes to previous selections, or click Generate to complete the wizard and generate all output files Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

69 BSB Flow R Figure 3-5: System Created Dialog Bo Output Files The list of generated files are displayed on the final page of the BSB Wizard. These files include the following: system.mhs: MHS file consisting of component instantiations, parameterization, and connections. system.mss: MSS file consisting of default driver names for each hardware component, including processor, OS, and parameterization of drivers if necessary. data/system.ucf: Xilin User Constraints File containing constraints such as timing, FPGA pin locations, FPGA resource specification, and IO standards. When you create a custom board, this file is not complete. You must manually enter FPGA pin locations and other constraints as defined by the hardware on the custom board. etc/fast_runtime.opt: Options file containing default options that are used by the Xilin implementation tools if run from XPS. etc/download.cmd: Xilin download command file which can be used to run the download tool impact in batch mode. This file uses the impact identify command, which assumes that you have installed the necessary data files for all devices on the JTAG chain on the development board. You can modify this file if necessary. Refer to the impact documentation for more information. system.mp: XPS project file containing project options. Embedded System Tools Reference Manual 69 UG111 (v4.0) February 15,

70 Chapter 3: Base System Builder The following files are optional: TestApp_MemoryTest/src/TestApp_Memory.c: Sample application source file. TestApp_MemoryTest/src/TestApp_Memory_LinkScr: Linker script defining the memory locations in which to place each section of the application program. TestApp_PeripheralTest/src/*.c: Sample application source files. Testapp_PeripheralTest/src/TestApp_Peripheral_LinkScr: Linker script defining the memory locations in which to place each section of the application program. system.bsb: BSB specific settings file which can load into a subsequent BSB session to automatically load the same selections that were made in this wizard session. Limitations Eiting BSB When you eit the BSB, the The Net Step window opens. In this window, you can elect to do one of the following: Open the Add/Edit Cores dialog bo to add or edit hardware components Configure drivers and libraries Download the design to a board and test the design Edit the test application generated by the BSB Start using Platform Studio Note: Select the Remember my selection and don t show this again checkbo to always have the BSB do the selected action. The BSB sets some project parameters (in XMP format) and software parameters (in MSS format) that might be necessary for the system that was built. These parameters are saved when you save the XPS project. The BSB was designed to create a basic functional system quickly. Therefore, it does not allow you to create advanced systems or create very specific configurations. The following are known limitations of the BSB wizard: BSB does not support multi-processor systems. BSB does not allow you to specify or modify the address map. BSB does not check for specific hardware resources on the target FPGA device. You must consult the data sheet for the FPGA that you are using to ensure that it contains enough logic elements and other resources required by the system you are creating. Systems generated by BSB are not guaranteed to meet timing. Any system that is created by the BSB can be further enhanced either in XPS or by manually modifying the design files generated by BSB. Therefore, you can use the BSB as a starting point for building a comple design Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

71 Chapter 4 Create and Import Peripheral Wizard Invoking the Wizard The Xilin Embedded Design Kit (EDK) comes with a large number of commonly used peripherals. Many different kinds of systems can be created with these peripherals, but you might need to create your own custom peripheral to implement functionality not available in the EDK peripherals library. The Create and Import Peripheral Wizard helps you create your own peripherals and import them into EDK-compliant repositories or Xilin Platform Studio (XPS) projects. In the Create mode, the Create and Import Peripheral Wizard creates a number of files. Some of these files are templates that help you implement your peripheral without needing to have a detailed understanding of the bus protocols, naming conventions or the formats of special interface files required by the EDK. By referring to the eamples in the template file and using various auiliary design support files that are output by the wizard, you can quickly get started on designing your custom logic. In the Import mode, this tool helps you create the interface files and directory structures that are necessary to make your peripheral visible to the various tools in EDK. For this mode of operation, it is assumed that you have followed the naming conventions required by EDK. Once imported, your peripheral is available in the EDK peripherals library. These procedures are described in the following sections: Invoking the Wizard Creating New Peripherals Importing an Eisting Peripheral Organization of Generated Files Restrictions You can invoke the Create and Import Peripheral Wizard from XPS before you create or open an XPS project, or directly from the Windows Start menu. 1. In XPS, select Tools ocreate/import Peripheral to open the Create and Import Peripheral Wizard. You can view various CoreConnect and IPIF documentation by clicking the links that are listed in the welcome dialog bo. The Create/Import User Peripheral dialog bo appears. Embedded System Tools Reference Manual 71 UG111 (v4.0) February 15,

72 Chapter 4: Create and Import Peripheral Wizard 2. Do one of the following: Creating New Peripherals i i Select Create templates for a new peripheral. This opens the Create mode. For more information about using this mode, refer to Creating New Peripherals on page 72. Select Import eisting peripheral. This opens the Import mode. For more information about using this mode, refer to Importing an Eisting Peripheral on page 83. In the create mode, the Create and Import Peripheral Wizard helps you create a peripheral suitable for instantiation into systems designed using EDK. You answer a few simple questions and the tool outputs a number of Hardware Description Language (HDL) files that conform to the conventions and rules required by the EDK. You implement the body of one of the outputted HDL blocks. The interface to this block is generic, so you do not have to fully understand the intricacies of the bus protocol such as CoreConnect to implement your peripheral. Information About Creating New Peripherals The current limitations of the tool include the following: Supports On-chip Peripheral Bus (OPB), Processor Local Bus (PLB), and Fast Simple Link (FSL) bus interface peripheral creation only. The OPB/PLB peripheral (top design entity) template is in VHDL only. This is because the underlying library elements are implemented in VHDL. The stub user-logic module template, however, can be in either VHDL or Verilog to support a mied-language development mode. EDK-compliant peripherals have the following components. The Create and Import Peripheral Wizard guides you through customizing each of the following components: A Bus Interface A set of ports that the peripheral must have to connect to the targeted bus. The Intellectual Property Interface (IPIF) for OPB/PLB peripherals The bus interface connects to this component. Additionally, it provides functionality that most EDK compliant peripherals need, including address decoding, addressable registers, interrupt handling, read/write FIFOs, and Direct Memory Access (DMA). The IPIF is structurally parameterizable, so only the required logic is implemented. A component that implements the application-specific logic (user logic). For OPB/PLB peripherals, this is the logic that cannot be implemented in the IPIF. The user logic interfaces to the IPIF through a set of ports called the Intellectual Property Interconnect (IPIC). These ports are designed to simplify the implementation of the user logic. For FSL peripherals, this is any application-specific logic that interfaces to the fast simple link (FSL) bus protocol ports. For peripheral creation, you must do the following: Indicate the module name and destination, such as the XPS project or EDK repository in which the peripheral must be stored. Select the bus interface to which the peripheral is targeted Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

73 Creating New Peripherals R For OPB/PLB peripherals, select and configure IPIF services. These are common functionalities required by most peripherals. If selected they reduce the amount of HDL code you must write. For FSL peripherals, select and configure the FSL bus interface and driver function. Implement user logic in generated files. This requires the use of common HDL-based design flows. Implement peripheral driver files. This requires the use of common software-based design flows. Note: The VHDL and C driver template files output by the Create and Import Peripheral wizard are already complete and working designs. This tool writes out various sample code snippets in the userlogic module to demonstrate the features that you have selected and provides a sample self-test function along with the C driver template to test various hardware features via software.you can use the output template in the same way as any other EDK peripherals without changing any part of the template code. Referring to these code eamples helps you implement your custom functionality. Identifying the Physical Location of Your Peripheral EDK requires that all source (HDL or driver) and interface files representing your peripheral be stored in a predefined directory structure under an XPS project or EDK peripherals repository. The EDK repository is the more versatile storage mechanism because many XPS projects can access one EDK repository. This tool creates the correct directory structures and interface files. In the Repository or Project dialog bo, indicate whether you want an XPS project or EDK repository, and the physical location of the XPS project or EDK repository. An XPS project is a directory containing an XMP file. An EDK repository is a directory containing one or more EDK peripheral libraries. Select one of the following options for storing the new peripheral. Storing the New Peripheral in an EDK User Repository 1. Select To an EDK user repository. The Repository bo displays a default location. 2. To change the default location, click Browse. 3. In the Browse for Folder dialog bo, navigate to the repository in which you want to store the peripheral. In the directory you select, the peripheral directory is created in the directory edk_user_repository\myprocessoriplib\pcores. 4. Click OK. 5. Click Net on the Repository or Project dialog bo to continue to the net step, Identifying Module and Version, in which you specify the name and version of the peripheral. Storing the New Peripheral in an XPS Project 1. Select To an XPS project. 2. To select a project, click Browse. 3. In the Open dialog bo that opens, navigate to the project in which you want to store the peripheral. Embedded System Tools Reference Manual 73 UG111 (v4.0) February 15,

74 Chapter 4: Create and Import Peripheral Wizard In the directory you select, the peripheral directory is created in <XPS Project directory>\pcores. 4. Click Open. 5. Click Net on the Repository or Project dialog bo to continue to the net step, Identifying Module and Version. Identifying Module and Version In this dialog bo, you do the following: 1. In the Name bo, type the name of your top design entity. Typically, this is the name of the top module in the design hierarchy that makes up the peripheral. 2. Indicate the version identifier for your peripheral by setting the following values: i Major Revision Select the identifier for the major revision i i Minor Revision Select the identifier for the minor revision Hardware/Software Compatibility Revision Select the identifier for the hardware/software compatibility revision Naming Conventions for Peripherals EDK requires that the top module and other sub-modules (if necessary) for your peripheral are compiled into a logical library named after the top module and the version number. Table 4-1 and Table 4-2 describe the naming conventions for peripherals. Table 4-1: Naming conventions for peripherals using version identifiers Peripheral Name (eample) Major version 9 Minor Version 12 Software/hardware compatibility identifier Logical library name Table 4-2: Peripheral Name Logical library name It is very important that all the elements of this peripheral are compiled into the specified logical library or into some other logical library already available in the XPS project or in any of the currently accessible EDK repositories. This tool actually processes only the files that are compiled into the logical library indicated by the above eamples. Other files are assumed to be available in the XPS project, or in any of the currently accessible repositories, or if necessary, they are imported along with the peripheral under a separate directory structure when you run import mode. The library and use lines in your VHDL must, therefore, use this logical library name. Note: Do not use work for the chosen library name. spi46 The subsequent sections of this document deals with details of peripheral creation or peripheral import using this tool. g spi46_v9_12_g Naming conventions for peripherals not using version identifiers spi46 spi Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

75 Creating New Peripherals R Selecting the Bus Interface In this panel you indicate the bus interface supported by your peripheral. Select one of the following: On-chip Peripheral Bus (OPB) Processor Local Bus (PLB) Fast Simple Link (FSL) OPB/PLB Bus Interfaces If you selected OPB or PLB bus interface, the Create and Import Peripheral wizard provides dialog boes for you to do the following, as described in subsequent sections. Select IPIF Services Configure the IPIC Generate Peripheral Simulation Support (Optional) Generate Peripheral Implementation Support (Optional) FSL bus interfaces are described in FSL Bus Interfaces on page 81. Select IPIF Services All OPB/PLB user peripheral templates created with this tool incorporate a module called the Intellectual Property Interface (IPIF). There are two kinds of IPIFs: OPB and PLB. One side of this interface implements the OPB or PLB interface, and the other side implements the Intellectual Property Interconnect (IPIC) interface. The user peripheral implements the IPIC. The IPIC is bus agnostic, so it is possible to create user modules with an IPIC interface that can operate on either an OPB or PLB. Additionally, the IPIC is hardware friendly, and thus easier to work with. For additional information about IPIF features, refer to Table 4-3 on page 76. The IPIF provides some very basic services, such as slave attachment, address decoding, byte steering, and some optional services that might greatly simplify the task of creating your peripheral. Based on the services you select, the wizard automatically creates corresponding OPB or PLB peripheral templates with slave-only operation or master-slave combined operations. Selecting either the DMA service or user-logic master support service triggers the wizard to generate a master-slave combined template instead of slaveonly template. Embedded System Tools Reference Manual 75 UG111 (v4.0) February 15,

76 Chapter 4: Create and Import Peripheral Wizard These features are described below. Table 4-3: IPIF Services IPIF Feature S/W Reset and Module Information Register (RST/MIR) Burst and Cacheline Transaction Support DMA FIFO User Logic Interrupt Support User Logic S/W Register Support User Logic Master Support User Logic Address Range Support Description The peripheral has a special write-only address. When a specific word is written to this address, the IPIF generates a reset signal for the peripheral. The peripheral resets itself using this signal. This allows individual peripherals to be reset from the software application. The peripheral also has a read-only register that identifies the revision level of the peripheral. Burst and cache line transactions allow the bus master to issue a single request that results in multiple data values being transferred. Support of these transactions requires significant hardware resources. Presently, the fast burst mode is used. Cache line is available for the PLB peripherals only. The IPIF part of the peripheral has a built-in DMA service. Using the DMA service automatically enables the burst support to optimize data transactions. For more information, refer to Configure the DMA Module on page 77. The IPIF part of the peripheral has a built-in FIFO service. For more information, refer to Configure FIFOs on page 77. The peripheral has an interrupt collection mechanism that manages the interrupts generated by the user logic and the IPIF services and generates a single interrupt output line from the peripheral. The user logic component of the peripheral has registers addressable through software. Includes the IPIC master interface signals for user-logic master operations. It also includes the eample HDL of a simple master operation model. Generates enable signals for each address range. This feature is useful for peripherals that need to support multiple address ranges, such as multiple memory banks. The distinction between this and other cases is that the enable signals are generated for each address range of the address space supported by the peripheral, rather than for each addressable register in the user-logic module Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

77 Creating New Peripherals R Configure the DMA Module If you select the DMA option on the IPIF Services dialog bo, then you must configure the DMA module. DMA is available in the IPIF for peripherals that might need Direct Memory Access support, such as an ethernet interface. The DMA component sets up two channels, which can be used to transmit or receive, operating in Simple DMA mode. Configure FIFOs If you select the FIFO option on the IPIF Services dialog bo, then you must configure FIFOs. FIFOs are available in the IPIF for peripherals that might need data buffering support. Two FIFO types are provided: Read Packet FIFO and Write Packet FIFO In the IPIF Services dialog bo, you choose to include a Read and/or Write FIFO. You also configure the FIFO by indicating the data width of the FIFO in bits, and the number of entries it can store. You can also select other features, such as packet mode access and signals that indicate FIFO vacancy. Configure Interrupt Handling If you select the User Logic Interrupt Support option on the IPIF Services dialog bo, the peripheral has an interrupt collection mechanism that manages the interrupts generated by the user logic and the IPIF services and generates a single interrupt line out of the peripheral. An addressable, register-based mechanism for enabling and disabling the interrupts generated by the peripheral is provided, as are registers to determine the status and source of the interrupts. The interrupts generated by the user logic part of the peripheral are first processed by an IP Interrupt Source Controller (IP ISC). The interrupt signal out of this controller is then fed into a Device Interrupt Source Controller (Device ISC) in the IPIF where it is processed in conjunction with the interrupts generated from the other IPIF services. The IP ISC has a software addressable Interrupt Enable Register (IP IER) that can be used to enable and disable interrupts from the software application. Both the IP ISC and Device ISC are implemented in the IPIF component of the peripheral. In the Interrupt Service dialog bo, you must indicate the number of interrupts generated by the user logic and the capture mode of these interrupts. The following interrupt capture modes are supported. INTR_PASS_THRU The interrupt from the user logic has no additional capture processing applied to it. It is immediately sent to the IP ISC interrupt enable logic (IP IER) and then to the Device ISC. INTR_PASS_THRU_INV The input interrupt from the user logic is logically inverted but has no additional capture processing applied to it. The inverted interrupt level is passed through the IP IER and sent to the Device ISC interrupt enable logic. This mode is mainly used to capture active-low interrupts. INTR_REG_EVENT The IP ISC Status Register samples the IP Interrupt input at the rising edge of each bus clock pulse. If a logic high is sampled, the bit of the IP Interrupt Status Register corresponding to the input interrupt position stays high until the Interrupt Service Routine (ISR) clears the interrupt. INTR_REG_EVENT_INV This capture mode is the same as the INTR_REG_EVENT mode, ecept that the IP Interrupt is logically inverted before it enters the sample and holds the logic of the IP interrupt status register. Embedded System Tools Reference Manual 77 UG111 (v4.0) February 15,

78 Chapter 4: Create and Import Peripheral Wizard INTR_POS_EDGE_DETECT The IP ISC Status Register samples the interrupt input at the rising edge of each bus clock pulse. A one bus clock delayed sample is also maintained. The new sample and the delayed sample are compared. If the new sample is logic high and the old sample is logic low, indicating a rising edge event, then the IP Interrupt Status Register latches and holds a logic 1 for the interrupt bit position. Once latched, the bit of the IP Interrupt Status Register corresponding to the input interrupt position stays high until the ISR clears the interrupt. INTR_NEG_EDGE_DETECT The IP ISC Status Register samples the interrupt input at the rising edge of each bus clock pulse. A one bus clock delayed sample is also maintained. The new sample and the delayed sample are compared. If the new sample is logic low and the old sample is logic high, indicating a falling edge event, then the IP Interrupt Status Register latches and holds a logic 1 for the interrupt bit position. Once latched, the bit of the IP Interrupt Status Register corresponding to the input interrupt position stays high until the ISR clears the interrupt. You must also indicate whether you want to include the interrupts generated outside of the user-logic block (in the other IPIF services). To include these interrupts, select the Use Device ISC (interrupt source controller) check bo. You can also choose to use the priority encoder service offered by the IPIF. If you do not choose the device interrupt service controller, then only the interrupts generated by the user logic are recognized and processed through a user-logic specific interrupt service controller. Figure 4-1 displays a general indication of the implementation of the interrupt services in the IPIF. Including DMA service automatically enables the Device ISC implicitly even if you have no user logic interrupts. This allows the software application to detect completion of DMA transactions via interrupt mode instead of polling mode. Figure 4-1: The Interrupt Service in the IPIF 78 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

79 Creating New Peripherals R The Device ISC Priority Encoder service of the IPIF is a function that loops on the device ISC pending register, keeping track of the ordinal position of the highest priority interrupt source. The priority is from LSB to MSB, meaning bit 31 of the pending register has the highest priority, while bit 0 has the lowest priority. For eample, if bits 29, 26, and 25 of pending register are 1, then the interrupt ID register has value 2 since bit 29 has the higher priority. This service is meant to be used by the software application. When this service is enabled, the software application can set up a vector table to map different ISRs for each interrupt bit of the pending register, and use the Device ISC Interrupt ID register to map the identifier of the actual interrupt. This is more efficient than using code, such as ifelsif-else, to implement priority interrupt handling. Note: In the Create and Import Peripheral wizard and its associated documentation, the peripheral is sometimes referred to as a device. This refers to the peripheral only, and not its FPGA. Additionally, it is important to understand that the interrupts discussed here are processed by the IPIF, rather than directly by the interrupt controller processing the interrupts sent to the processor. The types of interrupts that can be processed by the interrupt controller in the processor system are described in Interrupt Signals on page 87. Configure Software Accessible Registers If you selected the User Logic S/W Register Support option in the IPIF Services dialog bo, the Create Peripheral Wizard adds software accessible registers in the generated user logic template. It also includes eample HDL code to read and write these registers by byte, half-word, word, or double-word (for PLB). This HDL indicates how these registers are read and written. This is among the most useful features of the tool. You can easily use these registers to feed data into and from other hardware. In the IPIF Services dialog bo, you indicate the number and size (byte, half-word, word, or double) of these registers. We recommend the size of these registers be the same as the data-width of the bus to which it is connected: 32 bits for OPB peripherals and 64 bits for PLB peripherals. This allows for a smaller implementation of the IPIF by optimizing out the implementation of the byte-steering logic. To set the number and size of the registers, select the values from the appropriate dropdown lists. Configure Address Ranges If you select the User Logic Address Range Support option in the IPIF Services dialog bo, you must configure address ranges. Certain peripherals, such as memory controllers, support multiple address ranges. This IPIF service provides you with IPIC ports that help you work with multiple address ranges. Indicate the number of address ranges and the size in bits of the data being accessed. We recommend that you set the size of these registers to be the same as the data-width of the bus to which they are connected: 32 bits for OPB peripherals and 64 bits for PLB peripherals. This allows for a smaller implementation of the IPIF by optimizing out the implementation of the byte-steering logic. A space select (enable) signal is generated for each range, rather than each word in the address space supported by the peripheral. This is different from the case of softwareaddressable registers where an enable signal is generated for each register. Embedded System Tools Reference Manual 79 UG111 (v4.0) February 15,

80 Chapter 4: Create and Import Peripheral Wizard Configure the IPIC After you configure the IPIF services, you must configure the IPIC. Typically the IPIC ports generated by this tool are dependent on the selections you make in the Select IPIF Services dialog bo. An advanced user, however, might want access to other IPIC ports. You can select these special ports in the IPIC dialog bo. Some of the IPIC ports in the IPIC dialog bo are already selected and cannot be deselected. These ports are required to implement the functionality indicated in the Select IPIF Services panel. Generate Peripheral Simulation Support (Optional) Besides the HDL template files, you can have the Create Peripheral wizard generate some simulation support files to help you simulate custom logic and functionality. When you select the Generate BFM simulation platform for ModelSim check bo, the wizard creates a BFM simulation platform to help you start sub-system simulation using the IBM Bus Functional Model (BFM) incorporated in the EDK. It also includes some sample bus transactions described in a BFL script file to verify various features of the template. It is optional but recommended that you let the tool generate the BFM simulation files, as this significantly saves time if you are using BFM simulation to verify your design. The BFM provides unit-level and system-level simulation and verification of logic designs which comply with CoreConnect (OPB or PLB) architecture specifications. It enables you to accelerate the design cycle time by identifying and addressing possible problems at an earlier stage of the design cycle. To take advantage of this feature, you must install the BFM toolkit in EDK and compile the ISE and EDK simulation libraries. For instructions and downloading the BFM package for your EDK installation, click the BFM Toolkit Installation Instructions link. The wizard builds a BFM simulation platform for you, including a system testbench, an IP testbench, sample bus transactions to access various IPIF features, and makefiles. These files work together to help you launch your simulator and verify the waveform. A readme file provides instructions for starting the BFM simulation after completing the wizard. Generate Peripheral Implementation Support (Optional) Besides the HDL template files, you can have the Create Peripheral wizard generate some implementation support files to help you implement custom logic and functionality, along with your software interface. Choose among the following three options. To select an option, click to select its checkbo: Generate stub user_logic template in Verilog instead of VHDL. By default, the wizard writes HDL template files in VHDL. With this option, you can implement your custom logic in the stub user logic module with Verilog instead of VHDL under a mied language design mode. If you select this option, the stub user-logic template is written in Verilog and the Verilog user logic component is instantiated in the peripheral template using a default binding rule according to the Xilin Synthesis Tool (XST). Xilin recommends that you use VHDL because all other EDK peripherals are implemented in VHDL, but you can use the HDL language you are comfortable with Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

81 Creating New Peripherals R Generate ISE and XST project files to help you implement the peripheral using XST flow. When you select this option, the wizard generates ISE and XST project files. The ISE project file helps you implement your design in Project Navigator. The XST project and synthesis script file helps you synthesize your design using XST directly. Xilin recommends that you let the tool generate ISE and XST project files for you because this significantly saves time if you use the Xilin flow to implement your design. Generate template driver files to help you implement software interface. When you select this option, software driver template files and a driver directory structure are created to help you implement drivers for your peripheral. The driver templates might include common macros and functions to access various hardware features, such as register read/write the templates and might also provide eample self-test functions to help you verify the peripheral via a software interface. FSL Bus Interfaces If you selected the FSL bus interface option, the Create and Import Peripheral wizard provides dialog boes to do the following, as described in subsequent sections. Define FSL Bus Interface Settings Generate Peripheral Implementation Support (Optional) Set Driver OPB and PLB bus interfaces are described in OPB/PLB Bus Interfaces on page 75. Define FSL Bus Interface Settings The Create Peripheral wizard generates peripherals that have at most two FSL interfaces: one for input and one for output. For input FSL interfaces, connect the peripheral s master interface to the CPU s slave interface, for data flow from peripheral to CPU. For output FSL interfaces, connect the peripheral s slave interface to the CPU s master interface for data flow from the CPU to the peripheral. In the FSL Bus Interface Settings dialog bo, select one of the following options. To select an option, click its radio button. Has input FSL interface only Specify the number of input data. Has both input and output FSL interface Specify both the number of input data and number of output data. The number of input and output data are used to create an eample HDL design. The eample design performs a simple add-to-accumulator function that primarily serves to eplain the protocol of the FSL interface. Refer to the comments in the eample HDL file for detail. Generate Peripheral Implementation Support (Optional) Besides the HDL template files, you can have the Create Peripheral wizard generate some implementation support files to help you implement your custom logic and functionality, and software interface. Embedded System Tools Reference Manual 81 UG111 (v4.0) February 15,

82 Chapter 4: Create and Import Peripheral Wizard Choose among the following three options: Generate eample design in Verilog instead of VHDL. For FSL peripheral creation, only one HDL template file is generated. By default, it is written in VHDL. With this option, you can implement your custom logic using Verilog instead of VHDL. Xilin recommends that you use VHDL because all of the other EDK peripherals are implemented in VHDL, but you can the HDL language that you are comfortable with. Generate ISE and XST project files to help you implement the peripheral using XST flow. When you select this option, the wizard generates ISE and XST project files. The ISE project file helps you implement your design in Project Navigator. The XST project and synthesis script file helps you synthesize your design using XST directly. Xilin recommends that you let the tool generate ISE and XST project files for you, because this significantly saves time if you use Xilin flow to implement your design. Generate template driver files to help you implement software interface. When you select this option, software driver template files and a driver directory structure are created to help you implement drivers for your peripheral. Xilin recommends that you let the tool generate template driver files for you, because this significantly saves time if you also implement software drivers for your peripheral. Set Driver If you select Generate template driver files to help you implement software interface in the Peripheral Implementation Support dialog bo, you must provide information for the tool to generate the C driver template for your FSL peripheral, including the function name and description and the number of input and output arguments. The driver function works with the eample HDL design to perform the co-processing task. Generating the Files Representing Your Design The Congratulations dialog bo displays the summary information for the peripheral templates you requested and a list of all the files the wizard creates. Once all the required data has been collected, the wizard does the following: Creates necessary directory structures. Creates HDL template files. Creates other files that help you complete the implementation of your peripheral. These files might include elements that help you design the peripheral using ISE, testbench and scripts that verify the peripheral using BFM simulation, C driver templates that implement the software drivers, and other documentation files that help you write applications using this peripheral. If you already have files in the target area, they are overwritten. This tool is highly dependent on the port/parameter interface and the set of HDL files that comprise your peripherals. If these change during implementation, you must re-run this tool in the Import mode to regenerate the EDK interface files Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

83 Importing an Eisting Peripheral R Review EDK Design Flow for OPB/PLB Peripheral After the wizard completes, XPS creates the following HDL files: core_name.vhd user_logic.vhd (or user_logic.v) In this case, core_name.vhd implements the top module core_name of your peripheral. It instantiates the IPIF module from the built-in EDK peripherals library and the user_logic module. The bus-interface ports appear on this module. Internally, these ports are wired to the IPIF module. The IPIF and user_logic modules are interconnected by the IPIC. The user_logic module usually has an empty implementation. In some cases, a simple implementation might be included. For eample, if software addressable register support is requested, the user_logic module implements a simple read/write to software addressable registers. Generally, you must implement the user_logic module only. However, if your user_logic module is not self-contained and needs more interface ports, you must add those to the core_name module in core_name.vhd. In such cases, add the ports to the core_name module and pass them through to the user_logic module. Do not make any other changes to the core_name.vhd file. You might need to run BFM simulation to verify that your design contains the correct functionality and achieves the epected results. Once your user logic is complete, create a simple processor system to ensure that the software and hardware components of your system are interacting as epected. The software component should implement the register reads and writes required to test out the interface. To do this, you must understand how to address the registers and interpret the data available there. These are documented in the IPIF section of the Processor IP Document. You should create a simple test system and implement and simulate that using the various flows available in EDK. Importing an Eisting Peripheral You can import an eisting peripheral in the Create and Import Peripheral Wizard. Your peripheral must be written in Verilog or VHDL, or both for a mied language design. Your peripheral can also implement the some Xilin-supported bus conventions. This tool is easiest to use if you have followed the naming conventions for the ports and parameters. Otherwise, it gives you the opportunity to establish the mapping of your ports and peripherals to the ports and peripherals in the Xilin-supported bus conventions. It is best to use this functionality in conjunction with the peripheral creation functionality described in Invoking the Wizard on page 71. Embedded System Tools Reference Manual 83 UG111 (v4.0) February 15,

84 Chapter 4: Create and Import Peripheral Wizard In this mode, the wizard does the following: Queries you about the characteristics of the peripheral and the location of the HDL files that make up the peripheral. This includes information about the target bus that the peripheral is epected to be connected to, whether it is a master and/or slave, and the characteristics of the interrupts generated by the peripheral. Copies out the HDL files into the XPS project or EDK repository using the rules for creating XPS and EDK repositories. Generates interface files such as the Microprocessor Peripheral Data (MPD), Peripheral Analyze Order (PAO), and Black-bo Data (BBD). These files allow the tools in the EDK to instantiate your peripheral in a system designed with XPS. It is very important that you follow certain conventions when you design your peripheral. The most important is the conventions used to name the top module and the logical library it is compiled into, which are described in Naming Conventions for Peripherals on page 74. The subsequent sections eplain the functionality offered by this tool, and how you can use the files that it generates. Identifying the Physical Location of Your Peripheral For information about identifying the physical location of your peripheral, refer to Identifying the Physical Location of Your Peripheral on page 73. Identifying Module and Version For information about identifying module and version information for your peripheral, refer to Identifying Module and Version on page 74. Note: Version control is optional in import mode, but Xilin recommends that you use it. You can either type your peripheral name or select a previously created peripheral from the Name drop-down list. Select Source File Types In this panel you indicate the file types that make up your peripheral. Select one of the following: HDL Source Files, described on page 85. Netlist Files, described on page 89. Documentation Files, described on page 89. Presently, the system requires that you have at least one HDL file in VHDL or Verilog with the.vhd or.v etensions, respectively. Your peripheral might also instantiate black bo netlists. These netlists might be EDIF, NGO, NGC, or any of the netlist formats supported by the XILINX implementation tools. Typically, these have.edn,.ngo, or.ngc etensions. If your peripheral is a single fied netlist, then you must create a HDL wrapper that instantiates your netlist as a black-bo. Your peripheral can also have documentation files in many of the common document formats, such as PDF or TXT, with.pdf or.tt etensions, respectively Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

85 Importing an Eisting Peripheral R HDL Source Files When you elect to use HDL Source Files, the Import Peripheral wizard displays the HDL Source Files dialog bo. In this window, you locate your HDL source files. You must also indicate whether your peripheral is in VHDL, Verilog, or Mied (if you use both HDL languages). In the HDL Source Files dialog bo, you have the following options: Decide whether or not to use data from a previous session. a. Select the Use data (*.mpd) collected during a previous invocation of the wizard check bo. b. Click Browse. c. In the Select MPD File dialog bo, navigate to the appropriate MPD file and click Select. Your file displays in the tet bo on the HDL Source Files dialog bo. Determine how to locate the HDL source files and dependent library files. Choose from the following options: i Use an XST project file (*.prj) When you select this radio button, you must select the PRJ file to use. Click Browse to find and select the file. The wizard attempts to determine the file list from the project file that you select. Verify the file list generated and modify it if necessary. i i HDL Analysis Information Use eisting Peripheral Analysis Order file (*.pao) When you select this radio button, you must select the PAO file to use. Click Browse to find and select the file. The wizard attempts to infer all dependent library files from the currently accessible EDK repositories. You can add more reference repositories or skip specific ones if files are unresolved. Note: Ensure that the filename does not contain spaces, as the wizard does not currently support such files. Browse to your HDL source and dependent library files (*.vhd, *.v) in net step When you select this radio button and click Net, the HDL Analysis Information dialog bo appears. This dialog bo is described in the net section, HDL Analysis Information. In the HDL Analysis Information dialog bo, determine the compile order of your HDL files, the HDL language type, and the logical libraries into which they are compiled. If you chose to select your HDL source files by parsing either the XST project file or the PAO file, then this dialog bo contains the list of files and the logical libraries into which they are compiled. Embedded System Tools Reference Manual 85 UG111 (v4.0) February 15,

86 Chapter 4: Create and Import Peripheral Wizard To edit the list: To add files to the list, click Add Files, and navigate to the location of the files you want to add. To add a library to the list, click Add Library, and navigate to the location of the library you want to add. The libraries available in the repositories known to the current XPS project are displayed in a Select Library drop-down list. When you select a library, the files available in that library display in the Select Peripheral list. All files in the selected library are selected by default, but you can deselect a file by disabling the check bo net to the file name. To remove an entry from the list, select it and click Remove. To change the compile order of an entry, select it in the list and click Move Up or Move Down. To modify the entry, click Modify. Normally, a selected file is assumed to be compiled into the logical library containing the current peripheral, as described in Identifying Module and Version on page 74. If you must include files from another peripheral, then that peripheral must be available in the repositories known by XPS, or it must have been previously added to the current project. After eiting the Select Library panel, you are returned to the HDL Analysis Information panel, where the newly selected files are displayed. Note: HDL source files compiled into the current logical library are copied to the peripheral directory structure. Other dependent library files are either assumed to be accessible through EDK repositories or are imported along with the peripheral under a separate directory structure if necessary. Bus Interfaces In the Bus Interfaces dialog bo, indicate the types of bus interfaces that your peripheral supports. Table 4-4 displays the bus interface choices. Table 4-4: Supported bus interfaces Bus Interface Description MSPLB SPLB MSOPB SOPB Master-slave Processor Local Bus Slave Processor Local Bus Master-Slave On-chip Peripheral Bus Slave On-chip Peripheral Bus This is a fast/wide bus that interacts directly with the processor. Most custom peripherals are unlikely to support this bus interface. Select this interface if your peripheral operates as a slave on the PLB. Most user peripherals connect to the OPB. Select this interface if your peripheral is a master and a slave. Select this interface if your peripheral operates as a slave on the OPB Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

87 Importing an Eisting Peripheral R Table 4-4: Supported bus interfaces (Continued) Bus Interface Description SDCR SLMB MFSL SFSL Slave Direct Connect Register Bus Slave Local Memory Bus Master Fast Simple Link Bus Slave Fast Simple Link Bus Select this if your peripheral operates as a slave on the Direct Control Register (DCR) bus. Select this if your peripheral operates as a slave off the LMB. Typically, this applies to systems that use the MicroBlaze soft-core processor. Select this if your peripheral operates as a master on the FSL bus. Select this if your peripheral operates as a slave on the FSL bus. Note: OPB/PLB master-only interfaces are not supported. Such interfaces are uncommon. Identifying Bus Interface Ports and Parameters Interrupt Signals A peripheral that implements a particular bus interface must have the ports required by that interface. The ports do not require specific names, but it is suggested that the ports are named eactly as specified in the specification of that interface, so that the wizard correctly identifies the bus interface ports. If the wizard is unable to identify all the ports, you must manually identify the bus interface ports before it actually imports any peripheral. Similarly, some bus interfaces require associated parameters. These are automatically identified if the parameters are named according to the interface convention. Otherwise, you must identify the required parameters. In the SOPB: Port dialog bo, identify the bus interface ports. To select a port, select the peripheral port from the Your Port column that corresponds to each bus-interface port in the SOPB Bus Connector column. In the SOPB: Parameter dialog bo, you define the parameter selections. If your peripheral follows the IPIF or CoreConnect standard naming conventions, the wizard preselects these values for you. Each peripheral must identify its interrupt signals and certain special attributes associated with the interrupt. The interrupt controller in the processor system processes these interrupts. The Identify Interrupt Signals dialog bo contains a list of non-bus interface ports on the peripheral. To define the attributes for an interrupt port, select the check bo for that port, then set your preferences in the Properties of interrupt port section. Embedded System Tools Reference Manual 87 UG111 (v4.0) February 15,

88 Chapter 4: Create and Import Peripheral Wizard The attributes are as follows: Interrupt sensitivity Select falling edge sensitive, rising edge sensitive, low level sensitive, or high level sensitive. Relative priority Choose Low, Medium or High. This information is used by some of the EDK tools to automatically prioritize the many interrupt generators in the system in which a peripheral is instantiated. If you do not have interrupts, check the No Interrupts check-bo to move to the net dialog bo in the wizard. Advanced Attributes on Ports and Parameters The Platform Specification Format (PSF) in EDK supports a large number of attributes on ports and parameters. These attributes help the tools in EDK automatically wire up the peripheral to the bus, connect the interrupt lines, display more readable names, and provide short descriptions of port and parameter functionality. In the Port Attributes and Parameter Attributes dialog boes, you input the values of the attributes. Port Attributes The Port Attributes dialog bo displays a list of ports on the left and a table of attributes on the right. By selecting from the Ports drop-down list, you can view only bus interface ports, only user (non-bus-interface) ports, or all ports. To set the attributes for a port, select it in the ports list. The Attributes table is prepopulated with the names and values of attributes for that port. The attribute names that display are descriptive names for the corresponding MPD keywords. Review and change these attributes if necessary. The Display Advanced Attributes check bo controls the display of non-essential attributes. They are not displayed by default. The value cells in the Attributes Table are color coded. A yellow cell contains data intuited from the ENTITY or module representing your peripheral. A green cell represents data intuited from inputs from some of the preceding screens. All other cells are editable. Note: If you position the cursor on one of the attributes in the left column of the Attributes Table, a short description of the attribute appears. This description usually contains the MPD keyword for this parameter. Parameter Attributes The Parameter Attributes dialog bo displays a list of parameters on the left and a table of attributes on the right. By selecting from the Parameters drop-down list, you can view only bus interface parameters, only user (non-bus-interface) parameters, or all parameters Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

89 Importing an Eisting Peripheral R Netlist Files To set the attributes for a parameter, select it in the parameters list. The Attributes table is pre-populated with the names and values of attributes for that parameter. The attribute names that display are descriptive names for the corresponding MPD keywords. Review and change these attributes if necessary. The value cells in the Attributes Table are color coded. A yellow cell contains data intuited from the VHDL entity or module representing your peripheral. A green cell represents data intuited from inputs from some of the preceding screens. All other cells are editable. Note: If you position the cursor on one of the attributes in the left column of the Attributes Table, a short description of the attribute appears. This description usually contains the MPD keyword for this parameter. Your peripheral can be HDL with fied netlists instantiated as black-boes. In this panel you locate the netlist files associated with your peripheral. Make this selection by browsing to the directory containing the file in the Netlist Files dialog bo. The wizard does not allow you to associate different netlist files with different parameter values for your peripheral. Also, you must have at least one HDL file associated with your peripheral. This could be the HDL file that just instantiates a black-bo netlist. These files can be in any of the common formats, such as NGC/NGO (.ngc and.ngo) or EDIF (.edn or.edf). Documentation Files Select documentation files by browsing to them in the wizard. These files can be in any of the common formats, such as PDF (.pdf) or TEXT (.tt). Completing Peripheral Import Once all the required data has been collected, the Import Peripheral Wizard does the following: Copies your HDL, netlist, and documentation files into the XPS project in a directory structure determined by the PSF. If the peripheral target is an XPS project, it is output to a directory named pcores located in the project directory. If the target is an EDK repository directory, then the peripheral is output to MyProcessorIPLib/pcores in the repository directory. Generates the interface files required by the EDK tools. These include the MPD, PAO, and BBD files. If you already have interface files in the target area, they are backed up unless you instruct otherwise. Note: Your source HDL, netlist, and documentation files will be copied over. If you make any changes to these files, you might have to run this tool again. Additionally, the output of this tool is highly dependent on the port/parameter interface and the HDL analyze order. If any of these change, you might want to re-run this tool. Embedded System Tools Reference Manual 89 UG111 (v4.0) February 15,

90 Chapter 4: Create and Import Peripheral Wizard Organization of Generated Files The wizard generates files based on your input. Table 4-5 describes what files are generated and how they are used. Table 4-5: Files and Directories Generated by the Wizard Directory or file Description <pcores-directory> <logical-library-name> <peripheral-name> <peripheral-version> <peripheral-directory> <devl> <devl>/readme.tt <devl>/ipwiz.log <devl>/ipwiz.opt <projnav-dir> <projnavdir>/<peripheralname>.npl This is one of the following: <EDK-Repository- Dir>/MyProcessorIPLib/pcores or <Directory-containing-XPS-Project-File>/pcores See Identifying the Physical Location of Your Peripheral on page 73 for details about how this is specified. This is the logical library name as defined in Identifying Module and Version on page 74. This is the peripheral name as defined in Identifying Module and Version on page 74. This is the peripheral version as defined in Identifying Module and Version on page 74. <pcores-directory>/<logical-libraryname> <peripheral-directory>/devl This is a directory containing collateral to help you develop the user-logic component of the peripheral. This is a file eplaining the output generated by the wizard. Xilin recommends that you look through this file. It has a lot of documentation about eactly what you must do to complete the implementation of the user-logic part of the peripheral. This is a file containing a list of messages outputted by the wizard. This is a file capturing the data input in the wizard GUI. Currently, you do not need to use this file for any purpose. <devl>/projnav This is a directory containing a Project Navigator project file. This directory contains files used by Project Navigator if you choose to develop the userlogic part of the peripheral using Project Navigator. The Project Navigator project file you can open to complete the development of the peripheral Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

91 Organization of Generated Files R Table 4-5: Files and Directories Generated by the Wizard (Continued) Directory or file Description <synthesis-dir> <simulation-dir> <projnavdir>/<peripheralname>.cli <synthesisdir>/<peripheralname>_st.prj <synthesisdir>/<peripheralname>_st.scr <simulationdir>/readme.tt <simulationdir>/bfm_sim_cmd.make <simulationdir>/bfm_sim_ps.make <simulationdir>/bfm_system.mhs <simulationdir>/bfm_system.mss <simulationdir>/bfm_system.mp <simulationdir>/scripts/sample.bfl <simulationdir>/scripts/wave.do <simulationdir>/scripts/run.do <ip-testbench-name> Not currently used. <devl>/synthesis This is a directory containing files that help you synthesize the peripheral using XST. The XST project file. If you add more HDL files to your peripheral, you need to add them to this file. This is a simple XST script file that uses the XST project file and can be passed to XST to generate the netlist representing the peripheral. <devl>/bfmsim This is a directory containing files that help you simulate the design using BFM. A README file that contains instructions on how to start BFM simulation. A makefile for command line use only. It contains targets for BFM simulation platform compilation and launching simulator. A makefile for XPS usage only. It contains targets for BFM simulation platform compilation and launching a simulator. A BFM simulation system testbench description file, input to Simgen for behavioral simulation generation. An empty system driver file to work around XPS warnings. An XPS project file for BFM simulation only. CoreConnect bus transactions described in Bus Functional Language, input to Bus Functional Compiler to generate simulator commands for simulation. A signal dataset file for viewing all signals in the waveform window. The top-level simulator script file. Contains commands to compile, load modules, and start simulation. <peripheral-name>_tb Embedded System Tools Reference Manual 91 UG111 (v4.0) February 15,

92 Chapter 4: Create and Import Peripheral Wizard Table 4-5: Files and Directories Generated by the Wizard (Continued) Directory or file Description <ip-testbench-dir> <drivers-directory> <drivers-directory>/<logical-libraryname> <peripheral-driverdirectory>/data <peripheral-driverdirectory>/src <simulation-dir>/pcores/<iptestbench-name>_<peripheral-version> This is a directory containing the IP testbench file for the peripheral. IP testbench file. Defines the processes used to test the peripheral under test and provides constant interface to the system testbench and mechanism to communicate with Bus Functional Language commands for synchronization. A directory containing EDK interface files (MPD & PAO) for the IP testbench. A directory containing EDK interface files (MPD & PAO) for the peripheral. A directory containing generated or imported VHDL files representing the peripheral. If you need more VHDL files to represent your peripheral, you can add them here. A directory containing generated or imported Verilog files representing the peripheral. If you need more VHDL files to represent your peripheral, you can add them here. <ip-testbenchdir>/hdl/vhdl/<iptestbench-name>.vhd <ip-testbenchdir>/data/ <peripheraldirectory>/data <peripheraldirectory>/hdl/vhdl <peripheraldirectory>/hdl/verilog This is one of the following: <EDK-Repository- Dir>/MyProcessorIPLib/drivers or <Directory-containing-XPS-Project- File>/drivers <peripheral-driverdirectory> A directory containing EDK interface files (MDD & TCL) for the peripheral driver. A directory containing peripheral driver source files and the makefile for compilation Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

93 estrictions R Restrictions This wizard has a number of limitations, as described here. Create Peripheral Mode Import Peripheral Mode Only simple mode DMA is supported in this release. Only ModelSim BFM simulation is supported in this release. Master-only templates are not supported; resource-wide the master-only interface does not save anything for you compared to master-slave combined templates with minimal slave functionality. Master-only bus interfaces are not supported. Such peripherals are rare. References to fied netlists cannot be parameterized. This implies that you cannot create a peripheral that is just a set of fied netlists without an associated HDL. Typically, such peripherals are supported by BBD files only, with no associated PAO file. XPS repository or projects with spaces in the path name are not supported. Embedded System Tools Reference Manual 93 UG111 (v4.0) February 15,

94 Chapter 4: Create and Import Peripheral Wizard 94 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

95 Chapter 5 Platform Generator Tool Requirements Tool Usage Hardware generation is done with the Platform Generator tool, Platgen. Platgen constructs the programmable system on a chip in the form of hardware netlists (HDL and implementation netlist files). This chapter contains the following sections: Tool Requirements Tool Usage Tool Options Load Path Output Files About Memory Generation Reserved MHS Parameters Synthesis Netlist Cache Current Limitations Set up your system to use the Xilin Development System. Verify that your system is properly configured. Consult the release notes and installation notes for more information. Run Platgen as follows: platgen -p virte2p system.mhs Tool Options The following options are supported in the current version. Table 5-1: Platgen Synta Options Option Command Description Help -h, -help Displays the usage menu and then quits. Version -v Displays the version number of Platgen and then quits. Embedded System Tools Reference Manual 95 UG111 (v4.0) February 15,

96 Chapter 5: Platform Generator Table 5-1: Platgen Synta Options (Continued) Option Command Description Filename -f<filename> Reads command line arguments and options from file. Language Log output Library Path for user peripherals and driver repositories -lang verilog vhdl -log <logfile[.log]> -lp <library_path> HDL language output. Default: vhdl. Specify the log file. Default: platgen.log. This option is currently not implemented. Add <library_path> to the list of IP search directories. A library is a collection of repository areas. Output directory -od <output_dir> Output directory path. Default: The current directory. Part name -p <partname> Use the specified part type to implement the design. Synthesis project files -st st none Generate synthesis project files. Default: st Platgen produces a synthesis vendorspecific project file. Instance name -ti <instname> Top-level instance name. Top-level module -tm <top_module> Name the top-level module as desired. Top level -toplevel yes no Input design represents a whole design or a level of hierarchy. Default: yes Load Path Refer to Figure 5-1 for a depiction of the peripheral directory structure. To specify additional directories, use one of the following options: Use the current directory (where Platgen was launched; not where the MHS resides) Set the EDK tool option -lp option Platgen uses a search priority mechanism to locate peripherals, as follows: 1. Search the pcores directory in the project directory 2. Search <library_path>/<library Name>/pcores as specified by the -lp option 3. Search XILINX_EDK/hw/<Library Name>/pcores 96 Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

97 Output Files R -lp <library_path> <Library Name> boards drivers pcores sw_services X10066 Figure 5-1: Peripheral Directory Structure From the pcores directory, the peripheral name is the name of the root directory. From the root directory, the underlying directory structure is as follows: data hdl netlist Output Files HDL Directory Platgen produces the following directories and files. From the project directory, this is the underlying directory structure: hdl implementation synthesis The hdl directory contains the following: system.[vhd v] This is the HDL file of the embedded processor system as defined in the MHS. This file contains IOB primitives if the -toplevel yes option is specified. system_stub.[vhd v] This is the toplevel template HDL file of the instantiation of the system and IOB primitives. Use this file as a starting point for your own toplevel HDL file. This file is generated when the -toplevel no option is specified. Otherwise, the system.[vhd v] file is the toplevel. <inst>_wrapper.[vhd v] This is the HDL wrapper file for the of individual IP components defined in the MHS. Embedded System Tools Reference Manual 97 UG111 (v4.0) February 15,

98 Chapter 5: Platform Generator Implementation Directory The implementation directory contains the following implementation netlist file of the peripheral: Synthesis Directory peripheral_wrapper.ngc The synthesis directory contains the following synthesis project file: system.[prj scr] About Memory Generation Platgen generates the necessary banks of memory and the initialization files for the BRAM Block (bram_block). The BRAM Block is coupled with a BRAM controller. Current BRAM controllers include the following: DSOCM BRAM Controller (dsbram_if_cntlr) PowerPC only ISOCM BRAM Controller (isbram_if_cntlr) PowerPC only LMB BRAM Controller (lmb_bram_if_cntlr) MicroBlaze only OPB BRAM Controller (opb_bram_if_cntlr) PLB BRAM Controller (plb_bram_if_cntlr) The BRAM block (bram_block) and one of the BRAM controllers are tightly bound; the associated options of the BRAM controller define the resulting BRAM block. These options are listed in every BRAM controller MPD file. For eample, the OPB BRAM controller MPD defines the following: OPTION NUM_WRITE_ENABLES = 4 OPTION ADDR_SLICE = 29 OPTION DWIDTH = 32 OPTION AWIDTH = 32 The definition of AWIDTH and DWIDTH is applied to C_AWIDTH and C_DWIDTH of the BRAM block, respectively. The port dimensions on ports A and B are symmetrical on the bram_block. Platgen overwrites all user-defined settings on the BRAM block to have uniform port widths. You can only connect BRAM controllers of the same options values to the same BRAM block instance. For eample, you can connect an OPB BRAM controller and LMB BRAM controller to the same BRAM block. However, you cannot connect an OPB BRAM controller and a PLB BRAM controller to the same BRAM block instance. You can connect an LMB BRAM controller and a DSOCM BRAM controller to the same BRAM block instance. The BRAM controller s MHS options, C_BASEADDR and C_HIGHADDR, define the different depth sizes of memory. Refer to the Microprocessor Hardware Specification (MHS) chapter in the Platform Specification Format Reference Manual for more information. Only predefined memory sizes are allowed. A predefined memory size is limited to the number of Select BlockRAM available as long as the memory size is of powers of two. The smallest memory size must support byte-write access Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

99 About Memory Generation R BMM Policy Be sure to check that your FPGA resources can adequately accommodate your eecutable image. For eample, in the smallest Spartan-II device, c2s15, only four Select BlockRAMs are available for a maimum memory size of 2 kb. In the largest Spartan-II device, c2s200, 14 Select BlockRAMs are available for a maimum memory size of 7 kb. For eample, for a memory size of 4 kbytes on a Virte device, Platgen uses eight Select BlockRAMs to support byte-write access. A BlockRAM Memory Map (BMM) file contains a syntactic description of how individual BlockRAMs constitute a contiguous logical data space. Platgen has the following policy for writing a BMM file: BMM Flow Table 5-2: Architecture Predefined Memory Sizes Memory Size (kbytes) 32-bit byte-write If PORTA is connected and PORTB is not connected, then the BMM generated will be from PORTA point of reference. If PORTA is not connected and PORTB is connected, then the BMM generated will be from PORTB point of reference. If PORTA is connected and PORTB is connected, then the BMM generated will be from PORTA point of reference. The EDK tools Implementation Tools flow using Data2MEM is as follows: ngdbuild -bm <system>.bmm <system>.ngc map par bitgen -bd <system>.elf Memory Size (kbytes) 64-bit byte-write Spartan-II 2, 4 4, Spartan-IIE 2, 4, 8, 16 4, 8, 16, 32 Spartan-3 8, 16, 32, 64 16, 32, 64, 128 Virte 2, 4, 8, 16 4, 8, 16, 32 Virte E 2, 4, 8, 16 4, 8, 16, 32 Virte -II 8, 16, 32, 64 16, 32, 64, 128 Virte -II PRO 8, 16, 32, 64 16, 32, 64, 128 Virte -4 2, 4, 8, 16, 32, 64, 128 4, 8, 16, 32, 64, 128, 256 Bitgen outputs <system>_bd.bmm that contains the physical location of BlockRAMs. The <system>_bd.bmm and <system>.bit files are input to Data2MEM. Data2MEM translates contiguous fragments of data into the proper initialization records for Virte series BlockRAMs. Embedded System Tools Reference Manual 99 UG111 (v4.0) February 15,

100 Chapter 5: Platform Generator Reserved MHS Parameters Platgen automatically epands and populates certain reserved parameters. This can help prevent errors when your peripheral requires information on the platform that is generated. The following table lists the reserved parameter names: Table 5-3: Automatically Epanded Reserved Parameters Parameter Description C_FAMILY C_PACKAGE C_SPEEDGRADE C_INSTANCE C_KIND_OF_EDGE C_KIND_OF_LVL C_KIND_OF_INTR C_NUM_INTR_INPUTS C_MASK C_NUM_MASTERS C_NUM_SLAVES C_DCR_AWIDTH C_DCR_DWIDTH C_DCR_NUM_SLAVES C_LMB_AWIDTH C_LMB_DWIDTH C_LMB_MASK C_LMB_NUM_SLAVES C_OPB_AWIDTH C_OPB_DWIDTH C_OPB_NUM_MASTERS C_OPB_NUM_SLAVES C_PLB_AWIDTH C_PLB_DWIDTH C_PLB_MID_WIDTH C_PLB_NUM_MASTERS C_PLB_NUM_SLAVES FPGA device family Device package Device speed grade Instance name of component Vector of edge sensitive (rising/falling) of interrupt signals Vector of level sensitive (high/low) of interrupt signals Vector of interrupt signal sensitivity (edge/level) Number of interrupt signals LMB Decode Mask (deprecated) Number of OPB masters (deprecated) Number of OPB slaves (deprecated) DCR Address width DCR Data width Number of DCR slaves LMB Address width LMB Data width LMB Decode Mask Number of LMB slaves OPB Address width OPB Data width Number of OPB masters Number of OPB slaves PLB Address width PLB Data width PLB master ID width Number of PLB masters Number of PLB slaves Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

101 Synthesis Netlist Cache R Synthesis Netlist Cache Current Limitations An IP rebuild occurs with one of the following fundamental changes: Instance name change Parameter value change Core version change Core is specified with the MPD CORE_STATE=DEVELOPMENT option At least one of the above conditions is occurring to trigger an IP rebuild. In the Platgen flow, vector slicing is not supported. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

102 Chapter 5: Platform Generator Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

103 Chapter 6 Simulation Model Generator Simgen Overview This chapter introduces the basics of HDL simulation and describes the Simulation Model Generator tool, Simgen, and usage of the COMPEDKLIB utility tool. It contains the following sections: Simgen Overview Simulation Basics Simulation Libraries COMPEDKLIB Utility Tool Simulation Models Simgen Synta Output Files Memory Initialization Simulating Your Design Current Limitations Simgen creates and configures various VHDL and Verilog simulation models for a specified hardware. It takes a Microprocessor Hardware Specification (MHS) file as input, which describes the instantiations and connections of hardware components. Simgen is also capable of creating scripts for a specified vendor simulation tool. The scripts compile the generated simulation models. The hardware component is defined by the MHS file. Refer to the Microprocessor Hardware Specification (MHS) chapter in the Platform Specification Format Reference Manual for more information. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

104 Chapter 6: Simulation Model Generator Simulation Basics This section introduces the basic facts and terminology of HDL simulation in EDK. There are three stages in the FPGA design process in which you conduct verification through simulation, as displayed in Figure 6-1. Design Entry Design Synthesis Design Netlist Design Implementation Implemented Design Netlist Behavioral Simulation Structural Simulation Timing Simulation Functional Simulation UG111_01_ Figure 6-1: FPGA Design Simulation Stages Behavioral Simulation Behavioral simulation verifies the synta and functionality without timing information. The majority of the design development is done through behavioral simulation until the required functionality is obtained. Errors identified early in the design cycle are inepensive to fi compared to functional errors identified during silicon debug. We refer to all pre-synthesis HDL files as behavioral files. These files can be written in a purely behavioral manner using behavioral constructs such as operators, VHDL process or Verilog always statements. They can also be written in a structural manner using instantiations of lower level components or in a mied behavioral-and-structural manner. Structural Simulation Timing Simulation After behavioral simulation is error free, the HDL design is synthesized to gates. The postsynthesized structural simulation is a functional simulation with no timing information. The simulation can be used to identify initialization issues and to analyze don t care conditions. The post synthesis simulation generally uses the same testbench as functional simulation. The HDL files at this stage do not contain any behavioral constructs, such as operators, VHDL process or Verilog always constructs. Timing simulation is a structural simulation back-annotated with timing information. Timing simulation is important in verifying the operation of your circuit after the worst case place and route delays are calculated for your design. The back annotation process produces a netlist of library components annotated in an SDF file with the appropriate block and net delays from the place and route process. The simulation will identify any race conditions and setup-and-hold violations based on the operating conditions for the specified functionality Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

105 Simulation Libraries R Simulation Libraries Xilin Libraries The following libraries are available for the Xilin simulation flow. The HDL code must refer to the appropriate compiled library. The HDL simulator must map the logical library to the physical location of the compiled library. The following libraries are provided by Xilin for simulation. These libraries can be compiled using CompXLib. Refer to the Simulating Your Design chapter in the Synthesis and Verification Design Guide in your ISE 7.1 distribution to learn more about compiling and using Xilin simulation libraries. UNISIM Library The UNISIM Library is a library of functional models used for behavioral and structural simulation. It includes all of the Xilin Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated, such as I/Os and memory cells. You can instantiate the UNISIM library components in your design (VHDL or Verilog) and simulate them during behavioral simulation. Structural simulation models generated by Simgen instantiate UNISIM library components. All asynchronous components in the UNISIM library have zero delay. All synchronous components have a unit delay to avoid race conditions. The clock-to-out delay for these is 100 ps. SIMPRIM Library The SIMPRIM Library is a library used for timing simulation. This library includes all of the Xilin Primitives Library components that are used by Xilin implementation tools. Timing simulation models generated by Simgen instantiate SIMPRIM library components. XilinCoreLib Library EDK Library The Xilin CORE Generator is a graphical Intellectual Property (IP) design tool for creating high-level modules like FIR Filters, FIFOs, CAMs, and other advanced IP. You can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilin FPGA devices, such as block multipliers, SRLs, fast carry logic and onchip, single-port or dual-port RAM. The CORE Generator HDL library models are used for behavioral simulation. You can select the appropriate HDL model to integrate into your HDL design. The models do not use library components for global signals. The EDK Library is used for behavioral simulation. It contains all the EDK IP components, precompiled for ModelSim SE and PE or NcSim. This library eliminates the need to recompile EDK components on a per project basis, minimizing the time required to compile behavioral models on each project. EDK IP components library is provided for VHDL only. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

106 Chapter 6: Simulation Model Generator COMPEDKLIB Utility Tool Usage The EDK library can be compiled with the COMPEDKLIB utility, which is described in the following section. COMPEDKLIB is a utility tool provided by Xilin to compile the EDK HDL-based simulation libraries using the tools provided by various simulator vendors. This utility can operate in both the GUI and batch modes. In the GUI mode it allows you to compile the Xilin libraries (in your ISE installation) using COMPXLIB and the libraries available in EDK. compedklib [ -h ] [ -o output-dir-name ] [ -lp repository-dir-name ] [ -E compedklib-output-dir-name ] [ -lib core-name ] [ -compile_sublibs ] [ -eclude deprecated ] -s mti_se mti_pe ncsim -X complib-output-dir-name This tool compiles the HDL in EDK pcore libraries for simulation using the simulators supported by the EDK. Currently, the only supported simulators are MTI PE/SE and NCSIM. COMPEDKLIB Command Line Eamples Use Case I: Launching the GUI to Compile the Xilin and EDK Simulation Libraries compedklib No options are required. This launches the same GUI as when selecting Optionso Compile Simulation Libraries in XPS when no project is open. Note: This is the only mode of compedklib that also compiles the Xilin Libraries. All other modes compile only the EDK libraries. Use Case II: Compiling HDL Sources in the Built-In Repositories in the EDK The most common use case is as follows: compedklib -o <compedklib-output-dir-name> -X <complib-output-dir-name> -eclude deprecated In this case the pcores available in the EDK install are compiled and stored in <compedklib-output-dir-name>. The value of the -X option indicates the directory containing the models outputted by complib, such as the unisim, simprim, and XilinCoreLib compiled libraries. Pcores can be in development, active, deprecated, or obsolete state. Adding -eclude deprecated has the effect of not compiling deprecated cores. If you have deprecated cores in your design, do not use the -eclude deprecated option Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

107 Simulation Models R Use Case III: Compiling HDL Sources in Your Own Repository If you have your own repository of EDK-style pcores, you can compile them into <compedklib-output-dir-name> as follows: compedklib -o <compedklib-output-dir-name> -X <complib-output-dir-name> -E <compedklib-output-dir-name> -lp <Your-Repository-Dir> In this form, -E accounts for the possibility that some of the pcores in your repository might need to access the compiled models generated by Use Case I. This is very likely because the pcores in your repository are likely to refer to HDL sources in the EDK built-in repositories. You can limit the compilation to named cores in the repository: compedklib -o <compedklib-output-dir-name> -X <complib-output-dir-name> -E <compedklib-output-dir-name> -lp <Your-Repository-Dir> -lib core1 -lib core2 In this case, the entire repository is read but only the pcores indicated by the -c options are compiled. You can add -compile_sublibs to the above to compile the pcores that the indicated pcore depends on. Other Details If the simulator is not indicated, then MTI is assumed. You can supply multiple -X and -E arguments. The order of arguments is important. If you have the same pcore in two places, the first one is used. Some pcores are secure in that their source code is not available. In such cases, the repository contains the compiled models. These are copied into <compedkliboutput-dir-name>. If your pcores are in your XPS project, then Use Case 2 does not apply. XPS/SIMGEN will create the scripts to compile them. Currently, only VHDL is supported. The eecution log is available in compedklib.log. Beginning in EDK 7.1, the file indicated by your MODELSIM environment variable is not modified by COMPEDKLIB. However, the simulation scripts generated by SIMGEN will modify the file pointed to by the MODELSIM variable. Simulation Models This section describes how to generate each of the three FPGA simulation stages. For each stage, a different simulation model is created by Simgen. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

108 Chapter 6: Simulation Model Generator Behavioral Models To create a behavioral simulation model as displayed in Figure 6-2, Simgen requires an MHS file as input. Simgen creates a set of HDL files that model the functionality of the design. Optionally, Simgen can generate a compile script for a specified vendor simulator. If specified, Simgen can generate HDL files with data to initialize BRAMS associated with any processor that eists in the design. This data is obtained from an eisting Eecutable and Link Format (ELF) file. mhs SimGen HDL elf Script UG111_02_ Figure 6-2: Behavioral Simulation Model Generation Structural Models To create a structural simulation model as displayed in Figure 6-3, Simgen requires an MHS file as input and associated synthesized netlist files. From these netlist files, Simgen creates a set of HDL files that structurally model the functionality of the design. Optionally, Simgen can generate a compile script for a specified vendor simulator. If specified, Simgen can generate HDL files with data to initialize BRAMS associated with any processor that eists in the design. This data is obtained from an eisting ELF file. ngc mhs SimGen HDL elf Script UG111_03_ Figure 6-3: Structural Simulation Model Generation Note: The EDK design flow is modular. Platgen will generate a set of netlist files that are used by Simgen to generate structural simulation models Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

109 Simgen Synta R Timing Models To create a timing simulation model as displayed in Figure 6-4, Simgen requires an MHS file as input and an associated implemented netlist file. From this netlist file, Simgen creates an HDL file that models the design and an SDF file with appropriate timing information for it. Optionally, Simgen can generate a compile script for a specified vendor simulator. If specified, Simgen can generate HDL files with data to initialize BRAMS associated with any processor that eists in the design. This data is obtained from an eisting ELF file. ncd mhs SimGen HDL elf Script UG111_04_ Figure 6-4: Timing Simulation Model Generation Single and Mied Language Models Simgen Synta Requirements Simgen allows the use of mied language components in behavioral files for simulation. By default, Simgen takes the native language in which each component is written. Individual components cannot be mied language. To use this feature, a mied language simulator is required. All Xilin IP components are written in VHDL. If a mied language simulator is not available, Simgen can generate single language models by translating the HDL files that are not in the desired language. The resulting translated HDL files are structural files. All Structural and Timing simulation models are always single language. At the prompt, run Simgen with the MHS file and appropriate options as inputs. For eample, simgen system_name.mhs [options] Configure your system to use the Xilin ISE tools. Verify that your system is properly configured. Consult the release notes and installation notes that came with your software package for more information. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

110 Chapter 6: Simulation Model Generator Options The following options are supported in the current version. Table 6-1: Simgen Synta Options Option Command Description Help -h, -help Displays the usage menu and then quits. Version -v Displays the version and then quits. Options File -f filename Reads command line arguments and options from file. HDL Language Log Output Library Directories -lang vhdl verilog -log logfile[.log] -lp library_path Specifies the HDL language: VHDL or Verilog. Default: vhdl Specifies the log file. Default: simgen.log Allows you to specify library directory paths. This option can be specified more than once for multiple library directories. Simulation Model Type -m beh str tim Allows you to select the type of simulation models to be used. The supported simulation model types are behavioral (beh), structural (str) and timing (tim). Default: beh Mied Language -mied yes no Allows or disallows the use of mied language behavioral files. yes - Use native language for peripherals and allow mied language systems. no - Use structural files for peripherals not available in selected language. Note: Only valid when -m beh is used Default: yes Output Directory -od output_dir Specifies the project directory path. The default is the current directory. Target Part or Family -p partname Allows you to target a specific part or family. This option must be specified. Processor ELF Files -pe proc_instance elf_file {elf_file} Specifies a list of ELF files to be associated with the processor with instance name as defined in the MHS. Simulator -s mti ncs Generates compile script for vendor simulator: mti or ncs. mti - ModelSim ncs - NcSim Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

111 Output Files R Table 6-1: Simgen Synta Options (Continued) Option Command Description Source Directory -sd source_dir Specifies the source directory to search for netlist files. Testbench Template Top-Level Instance Top-Level Module -tb -ti top_instance -tm top_module Creates a testbench template file. Use -ti and -tm to define the device under test name and the testbench name, respectively. When a testbench template is requested, use top_instance to define the instance name of the design under test. When design represents a submodule, use top_instance for the top-level instance name. When a testbench template is requested, use top_module to define the name of the testbench. When the design represents a submodule, use top_module for the top-level entity/module name. Top-Level -toplevel yes no yes - Design represents a whole design no - Design represents a level of hierarchy (submodule) Default: yes EDK Library Directory Xilin Library Directory -E edklib_dir Specifies the path to EDK simulation libraries directory. This is the output directory of the COMPEDKLIB tool. -X lib_dir Path to Xilin simulation libraries (unisim, simprim, XilinCoreLib) directory. This is the output directory of the COMPLIB tool. Output Files Simgen produces all simulation files in the simulation directory within the output directory, and inside a subdirectory for each of the simulation models. output_directory/simulation/sim_model After a successful Simgen eecution, the simulation directory contains the following files: peripheral_wrapper.[vhd v] Modular simulation files for each component. Not applicable for timing models. system_name.[vhd v] The top level HDL file of the design. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

112 Chapter 6: Simulation Model Generator system_name.sdf The Standard Delay Format (SDF) file with the appropriate block and net delays from the place and route process used only for timing simulation. system_name.[do sh] Script to compile the HDL files and load the compiled simulation models in the simulator. Memory Initialization If a design contains banks of memory for a system, the corresponding memory simulation models can be initialized with data. With the -pe switch, a list of eecutable ELF files to associate to a given processor instance can be specified. The compiled eecutable files are generated with the appropriate GNU Compiler Collection (GCC) compiler or assembler, from corresponding C or assembly source code. Note: Memory initialization of structural simulation models is only supported when the netlist file has hierarchy preserved. VHDL Verilog For VHDL simulation models, run Simgen with the -pe option to generate a VHDL file. This file contains a configuration for the system with all initialization values. For eample: simgen system.mhs -pe mblaze eecutable.elf -l vhdl... This command generates the VHDL system configuration in the file system_init.vhd. This file is used along with your system to initialize memory. The BRAM blocks connected to the processor mblaze contains the data in eecutable.elf. For Verilog simulation models, run Simgen with the -pe option to generate a Verilog file. This file contains defparam constructs that initialize memory. For eample: simgen system.mhs -pe mblaze eecutable.elf -l verilog... This command generates the Verilog memory initialization file system_init.v. This file is used along with your system to initialize memory. The BRAM blocks connected to the processor mblaze contains the data in eecutable.elf. Simulating Your Design Current Limitations When simulating your design, there are some special considerations you need to keep in mind such as the global reset and tristate nets. Xilin ISE Tools provide detailed information on how to simulate your VHDL or Verilog design. Refer to the Simulating Your Design chapter in the ISE Synthesis and Verification Design Guide for more information. A PDF version of this document is located at /doc/usenglish/books/docs/sim/sim.pdf in your XILINX install area, or online at Simgen does not provide simulation models for eternal memories and does not have automated support for simulation models. Eternal memory models must be instantiated and connected in the simulation testbench and initialized according to the model specifications Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

113 Chapter 7 Library Generator Overview This chapter describes the Library Generator utility, Libgen, needed for the generation of libraries and drivers for embedded soft processors. It also describes how you can customize peripherals and associated drivers. This chapter contains the following sections: Overview Tool Usage Tool Options Load Paths Output Files Libraries and Drivers Generation MSS Parameters Drivers Libraries OS Interrupts and Interrupt Controller XMDStub Peripherals (MicroBlaze Specific) STDIN and STDOUT Peripherals Libgen is generally the first tool that you run to configure libraries and device drivers. Libgen takes a Microprocessor Software Specification (MSS) file that you create. The MSS file defines the drivers associated with peripherals, standard input/output devices, interrupt handler routines, and other related software features. Libgen configures libraries and drivers with this information. For further description of the MSS file format, refer to the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual. Note: EDK includes a RevUp tool to convert older MSS file formats to a new MSS format. See Chapter 10, Format Revision Tool, for more information. Tool Usage To run Libgen, type the following: libgen [options] filename.mss Embedded System Tools Reference Manual UG111 (v4.0) February 15,

114 Chapter 7: Library Generator Tool Options The following options are supported in this version:. Table 7-1: Libgen Synta Options Option Command Description Help -h, -help Displays the usage menu and then quits. Version -v Displays the version number of Libgen and then quits. Log output Architecture family -log logfile[.log] Specifies the log file. Default: libgen.log -p partname Defines the target device defined either as architecture family or partname. Use -h to view a list of values for the target family. Output directory -od output_dir Specifies the output directory output_dir. The default is the current directory. All output files and directories are generated in the output directory. The input file filename.mss is taken from the current working directory. This output directory is also called OUTPUT_DIR, and the directory from which Libgen is invoked is called USER_PROJECT for convenience in the documentation. Source directory -sd source_dir Specifies the source directory source_dir for searching the input files. The default is the current working directory. Library Path for user peripherals and driver repositories -lp library_path Specifies a library containing repositories of user peripherals, drivers, OS s, and libraries. Libgen looks for the following: Drivers in the directory library_path/sub_dir/drivers / Libraries in the directory library_path/sub_dir/sw_serv ices/ OS s in the directory library_path/sub_dir/bsp/ Here sub_dir is a subdirectory under library_path Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

115 Load Paths R Table 7-1: Libgen Synta Options (Continued) Option Command Description MHS File -mhs mhsfile.mhs Specifies the Microprocessor Hardware Specification (MHS) file to be used for Libgen. The following is the order Libgen uses to search and locate mhsfile.mhs: Current working directory (USER_PROJECT/). If no -mhs option is used, look in the MSS file for the parameter HW_SPEC_FILE to get the mhsfilename. If no HW_SPEC_FILE parameter is found in the MSS file, use the base name mssfile (name without.mss etension) with the.mhs etension as the mhsfilename. Libraries -lib Use this option to copy libraries and drivers but not to compile them. Load Paths -lp<library_path> <Library Name> boards drivers pcores bsp sw_services Figure 7-1: X10133 Directory Structure of Peripherals, Drivers, Libraries, and OS s Refer to Figure 7-1 and Figure 7-2 for diagrams of the directory structure for drivers, libraries, and Operating Systems (OS s). UNIX System Load Paths On a UNIX system, the drivers, libraries, and BSP reside in the following locations: Drivers: $XILINX_EDK/sw/Library Name/drivers Libraries: $XILINX_EDK/sw/Library Name/sw_services OS s: $XILINX_EDK/sw/BSP Name/bsp Embedded System Tools Reference Manual UG111 (v4.0) February 15,

116 Chapter 7: Library Generator PC System Load Paths On a PC, the drivers and libraries reside in the following locations: Additional Directories Drivers: %XILINX_EDK%\sw\Library Name\drivers Libraries: %XILINX_EDK%\sw\Library Name\sw_services OS s: %XILINX_EDK%\sw\BSP Name\bsp To specify additional directories, use one of the following options: Use the current working directory from which Libgen was launched. Set the EDK tool option -lp. Libgen looks for drivers, OS s, and libraries under each of the subdirectories of the path specified in the -lp option. Search Priority Mechanism Libgen uses a search priority mechanism to locate drivers and libraries, as follows: 1. Search the current working directory: a. Drivers: Search for drivers inside the drivers or pcores directory in the current working directory in which you run Libgen. b. Libraries: Search for libraries inside the sw_services directory in the current working directory in which you run Libgen. c. OS: Search for OS s inside the bsp directory in the current working directory from which you run Libgen. 2. Search the repositories under the library path directory specified using the -lp option: a. Drivers: Search one of the following, as specified by the -lp option: - library_path/library Name/drivers and library_path/library Name/pcores (UNIX) - library_path\library Name\drivers and library_path\library Name\pcores (PC) b. Libraries: Search one of the following as specified by the -lp option. Here library_path is the directory argument to -lp option and Library Name is a subdirectory under library_path: - library_path/library Name/sw_services (UNIX) - library_path\library Name\sw_services (PC) c. OS s: Search one of the following as specified by the -lp option. In this case, library_path is the directory argument to the -lp option and OS Name is a subdirectory under library_path: - library_path/os Name/bsp (UNIX) - library_path\os Name\bsp (PC) Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

117 Output Files R 3. Search the EDK install area: a. Drivers: Search one of the following: - $XILINX_EDK/sw/Library Name/drivers (UNIX) - %XILINX_EDK%\sw\Library Name\drivers (PC) b. Libraries: Search $XILINX_EDK/sw/Library Name/sw_services (UNIX) and %XILINX_EDK%\sw\Library Name\sw_services c. OS s: Search $XILINX_EDK/sw/Library Name/bsp (UNIX) and %XILINX_EDK%\sw\Library Name\bsp <Library Name> drivers sw_services bsp pcores <my_driver> <my_library> <my_os> <my_driver> src data src data src data src data.c files.h files MDD Tcl.c files.h files MLD Tcl.c files.h files MLD Tcl.c files.h files MDD Tcl Figure 7-2: Directory Structure of Drivers, OS s, and Libraries X10134 Output Files Libgen generates directories and files in the USER_PROJECT directory. For every processor instance in the MSS file, Libgen generates a directory with the name of the processor instance. Within each processor instance directory, Libgen generates the following directories and files, which are described in the following subsections: include Directory lib Directory libsrc Directory code Directory Embedded System Tools Reference Manual UG111 (v4.0) February 15,

118 Chapter 7: Library Generator include Directory lib Directory libsrc Directory code Directory The include directory contains C header files that are needed by drivers. The include file parameters.h is also created through Libgen in this directory. This file defines base addresses of the peripherals in the system, #defines needed by drivers, OS s, libraries and user programs, as well as function prototypes. The Microprocessor Driver Description (MDD) file for each driver specifies the definitions that must be customized for each peripheral that uses the driver. Refer to the Microprocessor Driver Definition (MDD) chapter in the Platform Specification Format Reference Manual for more information. The Microprocessor Library Definition (MLD) file for each OS and library specifies the definitions that you must customize. Refer to the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual for more information. The lib directory contains libc.a, libm.a, and libil.a libraries. The libil library contains driver functions that the particular processor can access. For more information about the libraries, refer to the Xilin Microkernel (XMK) chapter in the EDK OS and Libraries Reference Manual. The libsrc directory contains intermediate files and makefiles that are needed to compile the OS s, libraries, and drivers. The directory contains peripheral-specific driver files, BSP files for the OS, and library files that are copied from the EDK and your driver, OS, and library directories. Refer to the Drivers, OS, and Libraries sections of this chapter for more information. The code directory is a repository for EDK eecutables. Libgen creates mdstub.elf (for MicroBlaze on-board debug) in this directory. Note: Libgen removes all the above directories every time the tool is run. You must put your sources, eecutables, and any other files in an area that you create. Libraries and Drivers Generation Basic Philosophy This section describes the basic philosophy for generation of libraries and drivers. The MHS and the MSS files define a system. For each processor in the system, Libgen finds the list of addressable peripherals. For each processor, a unique list of drivers and libraries are built. Libgen does the following for each processor: Builds the directory structure as defined in the Output Files section. Copies the necessary source files for the drivers, OS s, and libraries into the processor instance specific area: OUTPUT_DIR/processor_instance_name/libsrc. Calls the design rule check (defined as an option in the MDD/MLD file) procedure for each of the drivers, OS s, and libraries visible to the processor Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

119 MSS Parameters R Calls the generate Tcl procedure (if defined in the Tcl file associated with an MDD/MLD) for each of the drivers, OS s, and libraries visible to the processor. This generates the necessary configuration files for each of the drivers, OS s, and libraries in the include directory of the processor. Calls the post_generate Tcl procedure (if defined in the Tcl file associated with an MDD/MLD) for each of the drivers, OS s, and libraries visible to the processor. Runs make (with targets include and libs) for the OS s, drivers, and libraries specific to the processor. Calls the eecs_generate Tcl procedure (if defined in the Tcl file associated with an MDD/MLD) for each of the drivers, OS s, and libraries visible to the processor. MDD/MLD and Tcl MSS Parameters A Driver or Library has two data files associated with it: Data Definition File (MDD/MLD): This file defines the configurable parameters for the driver, OS, or library. Data Generation File (Tcl): This file uses the parameters configured in the MSS file for a driver, OS, or library to generate data. Data generated includes but is not limited to generation of header files, C files, running DRCs for the driver, OS, or library, and generating eecutables. The Tcl file includes procedures that Libgen calls at various stages of its eecution. Various procedures in a Tcl file include: i i i DRC The name of DRC given in the MDD/MLD file generate A Libgen-defined procedure that is called after files are copied post_generate A Libgen-defined procedure that is called after generate has been called on all drivers, OS s, and libraries i eecs_generate A Libgen-defined procedure that is called after the BSPs, libraries and drivers have been generated Note: The data generation (Tcl) file is not necessary for a driver, OS, or library. For more information about the Tcl procedures and MDD/MLD related parameters, refer to the Microprocessor Driver Definition (MDD) chapter in the Platform Specification Format Reference Manual and the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual. For a complete description of the MSS format and all the parameters that MSS supports, refer to the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

120 Chapter 7: Library Generator Drivers Libraries Most peripherals require software drivers. The EDK peripherals are shipped with associated drivers, libraries and BSPs. Refer to the Device Driver Programmer Guide chapter in the Processor IP Reference Guide for more information on driver functions. The MSS file includes a driver block for each peripheral instance. The block contains a reference to the driver by name (DRIVER_NAME parameter) and the driver version (DRIVER_VER). There is no default value for these parameters. A driver LEVEL is also specified depending on the driver functionality required. The driver directory contains C source and header files for each level of drivers and a makefile for the driver. A Driver has an MDD file and/or a Tcl file associated with it. The MDD file for the driver specifies all configurable parameters for the drivers. This is the data definition file. Each MDD file has a corresponding Tcl file associated with it. This Tcl file generates data that includes generation of header files, generation of C files, running DRCs for the driver and generating eecutables. Refer to the Microprocessor Driver Definition (MDD) chapter in the Platform Specification Format Reference Manual and the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual for more information. You can write your own drivers. These drivers must be in a specific directory under YOUR_PROJECT/drivers or library_name/drivers, as shown in Figure 7-1. The DRIVER_NAME attribute allows you to specify any name for your drivers, which is also the name of the driver directory. The source files and makefile for the driver must be in the src/ subdirectory under the driver_name directory. The makefile should have the targets include and libs. Each driver must also contain an MDD file and a Tcl file in the data/ subdirectory. Refer to the eisting EDK drivers to get an understanding of the structure of the drivers. Refer to the Microprocessor Driver Definition (MDD) chapter in the Platform Specification Format Reference Manual for details on how to write an MDD and its corresponding Tcl file. The MSS file now includes a library block for each library. The library block contains a reference to the library name (LIBRARY_NAME parameter) and the library version (LIBRARY_VER). There is no default value for these parameters. The library directory contains C source and header files and a makefile for the library. The MLD file for each driver specifies all configurable options for the drivers. Each MLD file has a corresponding Tcl file associated with it. Refer to the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual and the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual for more information. You can write your own libraries. These libraries must be in a specific directory under YOUR_PROJECT/sw_services or library_name/sw_services as shown in Figure 7-1. The LIBRARY_NAME attribute allows you to specify any name for your libraries, which is also the name of the library directory. The source files and makefile for the library must be in the src subdirectory under the library_name directory. The makefile should have the targets include and libs. Each library must also contain an MLD file and a Tcl file in the data subdirectory. Refer to the eisting EDK libraries for more information about the structure of the libraries. Refer to the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

121 OS R OS The MSS file now includes an OS block for each processor instance. The OS block contains a reference to the OS name (OS_NAME parameter), and the OS version (OS_VER). There is no default value for these parameters. The bsp directory contains C source and header files and a makefile for the OS. The MLD file for each OS specifies all configurable options for the OS. Each MLD file has a corresponding Tcl file associated with it. Refer to the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual and the Microprocessor Software Specification (MSS) chapter in the Platform Specification Format Reference Manual for more information. You can write your own OS s. These OS s must be in a specific directory under YOUR_PROJECT/bsp or library_name/bsp as shown in Figure 7-1 on page 115. The OS_NAME attribute allows you to specify any name for your OS, which is also the name of the OS directory. The source files and makefile for the OS must be in the src subdirectory under the os_name directory. The makefile should have the targets include and libs. Each OS must also contain an MLD file and a Tcl file in the data subdirectory. Refer to the eisting EDK OS s to get an understanding of the structure of the OS s. Refer to the Microprocessor Library Definition (MLD) chapter in the Platform Specification Format Reference Manual for details on how to write an MLD and its corresponding Tcl file. Interrupts and Interrupt Controller Importance of Instantiation An interrupt controller peripheral must be instantiated if the MHS file has multiple interrupt ports connected. Libgen statically configures interrupts and interrupt handlers through the Tcl file for the interrupt controller. Alternately, you can dynamically register interrupt handlers in your code. Interrupts for the peripherals need to be enabled in your code. Interrupt Controller Driver Customization In the MSS file, the INT_HANDLER parameter allows an interrupt handler routine to be associated with the interrupt signal. The Interrupt Controller s Tcl file uses this parameter to configure the interrupt controller handler to call the appropriate peripheral handlers on an interrupt. The functionality of these handler routines is left for you to implement. If the INT_HANDLER parameter is not specified, a default dummy handler routine for the peripheral is used. MicroBlaze For MicroBlaze, if there is only one interrupt-driven peripheral, an interrupt controller need not be used. However, the peripheral should still have an interrupt handler routine specified. Otherwise a default one is used. When MicroBlaze is the processor to which the interrupt controller is connected, and when mb-gcc is the compiler used to compile drivers, the Tcl file associated with the MicroBlaze driver MDD designates the interrupt controller handler as the main interrupt handler. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

122 Chapter 7: Library Generator PowerPC For the PowerPC processor, you are responsible for setting up the eception table. Refer to the Interrupt Management chapter in the Platform Studio User Guide for more information. XMDStub Peripherals (MicroBlaze Specific) These peripherals are used specifically for debug with the mdstub program. For more information about the debug program mdstub, refer to Chapter 15, Xilin Microprocessor Debugger (XMD). The attribute XMDSTUB_PERIPHERAL is used for denoting the debug peripheral instance. Libgen uses this attribute to generate the debug program mdstub. STDIN and STDOUT Peripherals Peripherals that handle I/O need drivers to access data. Two files inbyte.c and outbyte.c are automatically generated with calls to the driver I/O functions for STDIN and STDOUT peripherals. The driver I/O functions are specified in the MDD as the parameters INBYTE and OUTBYTE. These inbyte and outbyte functions are used by C library functions such as scanf and printf. The peripheral instance should be specified as STDIN or STDOUT in the MSS file. The STDIN/STDOUT parameters are attributes of the standalone OS. The inbyte and outbyte functions are generated only when the STDIN and STDOUT attributes are specified in MSS file for the standalone OS. Each OS is responsible for handling the STDIN/STDOUT functionality Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

123 Chapter 8 Virtual Platform Generator This chapter introduces the virtual platform generation utility (VPgen) in XPS. It contains the following sections. Overview Tool Usage and Options Output Files Available Models Current Restrictions Overview The virtual platform is a cycle-level simulation model of the hardware system. The virtual platform can be used to debug and profile software application code on the host machines, eliminating the need to get the actual hardware working on a prototyping board. EDK supports virtual platform on NT and Linu platforms only. These models are functionally correct only on clock edges and not in between the edges. Therefore they are faster than performing a complete simulation in event-driven simulators such as ModelSim and NCSim. VPgen takes an MHS file as input and generates a binary eecutable for the hardware system. VPgen substitutes every component (pcore) in the system and replaces it with the corresponding C-model of the component. VPgen can also generate a C-model from a synthesizable HDL code source. VPgen generates a top-level kernel, which integrates various models together and provides a mechanism of communication between various models. The kernel also has a static scheduling of models of various components on clock edges. The generated model has an interface used by XMD to "control" the virtual platform while eecuting, debugging, or profiling the software application. Tool Usage and Options In XPS, you can generate a virtual platform model by selecting Tools o Generate Virtual Platform. Once a virtual platform model is successfully generated, you can use XMD to connect to this model and work on your software application. Refer to Virtual Platform MicroBlaze Target on page 211. You can run VPgen from the command line as follows: % vpgen [options] system.mhs Embedded System Tools Reference Manual UG111 (v4.0) February 15,

124 Chapter 8: Virtual Platform Generator The following options are supported by VPgen: Table 8-1: VPgen Contet Options Option Command Description Help -h, -help Displays the usage menu and then eits. Display version information -v Displays the version number of VPgen. Log -log logfile[.log] Specifies the log file. The default is vpgen.log. Architecture family -p part_name Defines the target device defined either as architecture family or partname. Use the -h option to view a list of values for the target family. Specify library path for your peripherals -lp library_path Specifies a library containing repositories of user peripherals. VPgen looks for peripherals in the <library_path>/<sub_dir>/ pcores directory. Output Files Available Models VPgen generates its output in the virtualplatform directory within the directory containing the MHS file. The main output file of interest is virtualplatform/vpeec[.ee]. This file is the compiled binary eecutable of the hardware system and the kernel. To generate vpeec, VPgen also produces intermediate files such as <system>.[c h]. For each peripheral that does not have a predefined model available, a <peripheral_instance>_wrapper.[c h] file generates. There is also a makefile called vpgen.make that compiles all the C-files and produces vpeec. For any IP that requires interaction with logic outside of the FPGA, that is, which has ports going out of the MHS, a modeling of the eternal logic is required within the IP model itself. Additionally, hand-written C models of IPs are more optimized than auto-generated models. Thus, for MicroBlaze, EDK provides a hand-written Instruction Set Simulator (ISS) model that is used by VPgen Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

125 Available Models R In EDK 7.1, models for the following ISPs are provided: Table 8-2: ISP Models Provided in EDK 7.1 ISP bram_block fsl_v20 lmb_bram_if_cntlr microblaze opb_ddr opb_emc opb_gpio opb_intc opb_sdram opb_uartlite opb_timer opb_v20 util_bus_split util_flipflop util_reduced_logic util_vector_logic Supports version v1.00.a Description/Notes Supports versions v1.00.b and v2.00.a Supports version v1.00.a. However, the functionality for the lmb_bram_if_cntlr and the connected bram_block are incorporated within the MicroBlaze ISS model itself. Hence, it is required that both the ILMB and DLMB of the MicroBlaze, if used, connect to the same bram_block in MHS. Supports versions v3.00.a, and v4.00.a MicroBlaze is modeled using a cycle accurate Instruction Set Simulator (ISS). Supports versions v1_00_b and v1_10_a. opb_ddr models only a simple volatile storage with fied read and write latencies of 8 and 4 opb clock cycles respectively. Supports versions v1.10.b, v2.00.a opb_emc (and other memory models) models only a simple volatile storage on the memory interface. It does not model specific memory chips that recognize command sequences or have control registers. Supports version v3.01.b Supports version v1.00.c Supports versions v1.00.c, v1.00.d and v1.00.e opb_sdram models a volatile storage with fied read and write latencies of 8 and 4 opb clock cycles respectively. Supports version v1.00.b Supports version v1.00.b Supports version v1.10.c. The model does not support dynamic priority arbitration. Supports version v1.00.a Supports version v1.00.a Supports version v1.00.a Supports version v1.00.a VPgen generates a real model for util_* IPs provided with EDK. For any other IP, VPgen generates a dummy model that conforms to the interface required by the kernel but does not perform any functionality of that IP. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

126 Chapter 8: Virtual Platform Generator Current Restrictions In EDK 7.1 release, VPgen only supports MicroBlaze designs generated by Base System Builder Wizard (BSB) with the following eceptions: VPgen generates a dummy model for cores for which there are no available models. A dummy model does not respond to any stimulation on its ports. If the access to a core happens through the C program of MicroBlaze, then the model for MicroBlaze times out. Note: Do not stimulate the core for which there is no model available. IO peripherals other than those listed in the available models list are not supported. For eample opb_ethernetlite is not supported. If you have this peripheral in your MHS design, VPgen will generate a dummy model for this IP. This dummy model allows the VP kernel to do port-level connectivity with the rest of the system. However, the model does not update its ports so any software access to such peripherals do not receive a response. This causes the MicroBlaze ISS to time out. Only designs containing a single MicroBlaze chip are supported. PowerPC is not supported in this release Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

127 Chapter 9 Platform Specification Utility Tool Options This chapter describes the various features and the usage of the Platform Specification Utility (PsfUtil) tool that enables automatic generation of Microprocessor Peripheral Description (MPD) files required to create an IP core compliant with the Embedded Development Kit (EDK). Features provided by this tool can be used with the help of the Create/Import Peripheral Wizard in Xilin Platform Studio (XPS). For more information about using the Create/Import Peripheral Wizard, refer to Chapter 4, Create and Import Peripheral Wizard. This chapter contains the following sections. Tool Options Overview of the MPD Creation Process Detailed Use Models for Automatic MPD Creation DRC Checks in PsfUtility HDL Peripheral Definitions Table 9-1: Tool Options Option Command Description Help -h, -help Displays the usage menu and then eits. Display version information HDL file to MPD -v Displays the version number. -hdl2mpd <hdlfile> Generate MPD from VHDL/Ver src/prj file. Suboptions: -lang <ver vhdl pao> Specify language -top <design> Specify top-level entity/module name {-bus <opb plb dcr lmb> <m s ms>} Specify one or more Bus Interfaces of the core {-tbus <transparent_bus_name> bram_port} Specify one or more Transparent Bus Interfaces of the core -o <outfile> Specify output filename; default is stdout Embedded System Tools Reference Manual UG111 (v4.0) February 15,

128 Chapter 9: Platform Specification Utility Table 9-1: Tool Options (Continued) Option Command Description PAO file to MPD -pao2mpd <paofile> Generate MPD from Peripheral Analyze Order (PAO) file. Suboptions: -lang <ver vhdl pao> Specify language -top <design> Specify top-level entity/module name {-bus <opb plb dcr lmb> <m s ms>} Specify one or more Bus Interfaces of the core {-tbus <transparent_bus_name> bram_port} Specify one or more Transparent Bus Interfaces of the core -o <outfile> Specify output filename; default is stdout Overview of the MPD Creation Process You can use PsfUtility to automatically create MPD specifications from the VHDL specification of the core. The steps involved to create a core and deliver it through EDK are: 1. Code the IP in VHDL or Verilog using strict naming conventions for all Bus signals, Clock signals, Reset signals and Interrupt signals. These naming conventions are described in detail in the VHDL IP Peripheral Guide. Note: Following these naming conventions enables PsfUtility to create a correct and complete MPD. 2. Create an XST project file or a Peripheral Analyze Order (PAO) file that lists all the HDL sources required to implement the IP. Invoke PsfUtility by providing the XST project file or the PAO file with additional options. For more information on invoking PsfUtility with different options, seethe following section, Detailed Use Models for Automatic MPD Creation. Detailed Use Models for Automatic MPD Creation You can invoke PsfUtility in a variety of ways depending on the bus standard and type of bus interfaces of the peripheral and the number of bus interfaces a peripheral contains. Bus standards and types can be one of the following: OPB SLAVE OPB MASTER OPB MASTER_SLAVE PLB SLAVE PLB MASTER PLB MASTER_SLAVE DCR SLAVE LMB SLAVE TRANSPARENT BUS (special case) Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

129 Detailed Use Models for Automatic MPD Creation R Peripherals with a Single Bus Interface The majority of processor peripherals fall into this category. This is also the simplest usage model for PsfUtility. For most peripherals, complete MPD specifications can be obtained without specification of any additional attributes in the source code. Signal Naming Conventions The signal names must follow conventions as specified in the HDL Peripheral Definition Guide. Since there is only one bus interface, no bus identifier needs to be specified for the bus signals. Invoking PsfUtility The command line for invoking PsfUtility is as follows: psfutil -hdl2mpd <hdlfile> -lang <vhdl ver> -top <top_entity> -bus <busstd> <bustype> -o <mpdfile> For eample, to create an MPD specification for an OPB SLAVE peripheral such as uart, the command is psfutil -hdl2mpd uart.prj -lang vhdl -top uart -bus opb s -o uart.mpd Peripherals with Multiple Bus Interfaces Some peripherals might have multiple bus interfaces associated with them. These interfaces can be eclusive bus interfaces or non-eclusive bus interfaces, or a combination of both. All bus interfaces of the peripheral that can be connected to the peripheral at the same time are eclusive interfaces. For eample, an OPB Slave bus interface and a DCR Slave bus interface are eclusive bus interfaces on a peripheral because they can both be connected at the same time. Note: Peripherals with eclusive bus interfaces cannot have any ports that can be connected to more than one of the eclusive interfaces. Non-eclusive bus interfaces are those interfaces that cannot be connected at the same time. Note: Peripherals with non-eclusive bus interfaces have ports that can be connected to more than one of the non-eclusive interfaces. Further, non-eclusive interfaces have the same bus interface standard. For eample, an OPB Slave interface and an OPB Master Slave interface are noneclusive if they are connected to the same slave ports of the peripheral. Non-Eclusive Bus Interfaces Signal Naming Conventions The signal names must follow conventions as specified in the HDL Peripheral Definition Guide. For non-eclusive bus interfaces, bus identifiers need not be specified for the bus signals. Invoking PsfUtility With Buses Specified in the Command Line You can specify buses on the command line when the bus signals are not prefied with bus identifiers. The command line for invoking PsfUtil is as follows: psfutil -hdl2mpd <hdlfile> -lang <vhdl ver> -top <top_entity> {-bus <busstd> <bustype>} -o <mpdfile> Embedded System Tools Reference Manual UG111 (v4.0) February 15,

130 Chapter 9: Platform Specification Utility For eample, to create an MPD specification for a peripheral with a PLB slave interface and a PLB Master Slave interface such as gemac, the command is psfutil -hdl2mpd gemac.prj -lang vhdl -top gemac -bus plb s -bus plb ms -o gemac.prj Eclusive Bus Interfaces Signal Naming Conventions The signal names must follow conventions as specified in the HDL Peripheral Definition Guide. Bus identifiers must be specified only when the peripheral has more than one bus interface of the same bus standard and type. Invoking PsfUtility With Buses Specified in the Command Line You can specify buses on the command line when the bus signals are not prefied with bus identifiers. The command line for invoking PsfUtil is as follows: psfutil -hdl2mpd <hdlfile> -lang <vhdl ver> -top <top_entity> {-bus <busstd> <bustype>} -o <mpdfile> For eample, to create an MPD specification for a peripheral with a PLB slave interface and a DCR Slave interface, the command is psfutil -hdl2mpd mem.prj -lang vhdl -top mem -bus plb s -bus dcr s -o mem.prj Peripherals with TRANSPARENT Bus Interfaces Some peripherals such as BRAM controllers might have transparent bus interfaces (BUS_STD=TRANSPARENT, BUS_TYPE = UNDEF). BRAM PORTS DRC Checks in PsfUtility To add a transparent BRAM bus interface to your core, invoke psfutil with an additional -tbus option psfutil -hdl2mpd bram_ctlr.prj -lang vhdl -top bram_ctlr -bus opb s -tbus PORTA bram_port The BRAM ports should follow signal naming conventions as specified in the HDL Peripheral Definition document. The following DRC errors are reported by PsfUtility to enable generation of correct and complete MPDs from HDL sources. The DRC checks are listed in the order that the checks are performed. HDL Source Errors PsfUtility returns a failure status if errors were found in the HDL source files Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

131 HDL Peripheral Definitions R Bus Interface Checks HDL Peripheral Definitions Given the list of bus interface of the cores, PsfUtility does the following: Checks and reports any missing bus signals for every specified bus interface Checks and reports any repeated bus signals for every specified bus interface PsfUtility does not generate an MPD unless all bus interface checks are completed. The top-level VHDL source file for an IP core defines the interface of the design. The VHDL source file has the following characteristics: Lists ports and default connectivity for bus interfaces Lists parameters (generics) and default values Any HDL source parameter is overwritten by the equivalent MHS assignment Individual peripheral documentation contains information on all source file options. Bus Interface Naming Conventions A bus interface is a grouping of interface signals which are related. For the automation tools to function properly, certain conventions must be adhered to in the naming of the signals and parameters associated with a bus interface. When the signal naming conventions are followed, the following interface types are automatically recognized and the MPD file contains the bus interface label shown in Table 9-2. Table 9-2: Recognized Bus Interfaces Description Slave DCR interface Slave LMB interface Master OPB interface Master/slave OPB interface Slave OPB interface Master PLB interface Master/slave PLB interface Slave PLB interface Bus label in MPD SDCR SLMB MOPB MSOPB SOPB MPLB MSPLB SPLB For components that have more than one bus interface of the same type, a naming convention must be followed so that the automation tools can group the bus interfaces. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

132 Chapter 9: Platform Specification Utility Naming Conventions for VHDL Generics A key concept for cores with more than one bus interface port is the use of a bus identifier, which is attached to all signals grouped together in a port and the generics that are associated with the bus interface port. The bus identifier is discussed below. Generic names must be VHDL compliant. Additional conventions for IP cores are: The generic must start with C_. If more than one instance of a particular bus interface type is used on a core, a bus identifier <BI> must be used in the signal. If a bus identifier is used for the signals associated with a port, then the generics associated with that port can also optionally use the <BI>. If no <BI> string is used in the name, then the generics associated with bus parameters are assumed to be global. For eample, C_DOPB_DWIDTH has a bus identifier of D and is associated with the bus signals that also have a bus identifier of D. If only C_OPB_DWIDTH is present, then it is associated with all OPB buses regardless of the bus identifier on the port signals. For cores that have only a single bus interface, which is the case for most peripherals, the use of the bus identifier string in the signal and generic names is optional and the bus identifier is typically not included. All generics that specify a base address must end with _BASEADDR, and all generic that specify a high address must end with _HIGHADDR. Further, to tie these addresses with buses, they must also follow the conventions for parameters as listed above. For peripherals with more than one type of bus interface, the parameters must have the bus standard type specified in the name. For eample, an address on the PLB bus must be specified as C_PLB_BASEADDR and C_PLB_HIGHADDR. The Platform Generator, Platgen, automatically epands and populates certain reserved generics. In order for this to work correctly, a bus tag must be associated with these parameters. In order to have PsfUtility automatically infer this information, all of the above specified conventions must be followed for all reserved generics as well. This can help prevent errors when your peripheral requires information on the platform that is generated. The following table lists the reserved generic names. Figure 9-1: Automatically Epanded Reserved Generics Parameter Description C_BUS_CONFIG C_FAMILY C_INSTANCE C_KIND_OF_EDGE C_KIND_OF_LVL C_KIND_OF_INTR C_NUM_INTR_INPUTS C_<BI>OPB_NUM_MASTERS C_<BI>OPB_NUM_SLAVES C_<BI>DCR_AWIDTH Bus Configuration of MicroBlaze FPGA Device Family Instance name of component Vector of edge sensitive (rising/falling) of interrupt signals Vector of level sensitive (high/low) of interrupt signals Vector of interrupt signal sensitivity (edge/level) Number of interrupt signals Number of OPB masters Number of OPB slaves DCR address width Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

133 HDL Peripheral Definitions R Figure 9-1: Automatically Epanded Reserved Generics (Continued) Parameter Description C_<BI>DCR_DWIDTH DCR data width C_<BI>DCR_NUM_SLAVES Number of DCR slaves C_<BI>LMB_AWIDTH LMB address width C_<BI>LMB_DWIDTH LMB data width C_<BI>LMB_NUM_SLAVES Number of LMB slaves C_<BI>OPB_AWIDTH OPB address width C_<BI>OPB_DWIDTH OPB data width C_<BI>OPB_NUM_MASTERS Number of OPB masters C_<BI>OPB_NUM_SLAVES Number of OPB slaves C_<BI>PLB_AWIDTH PLB address width C_<BI>PLB_DWIDTH PLB data width C_<BI>PLB_MID_WIDTH PLB master ID width C_<BI>PLB_NUM_MASTERS Number of PLB masters C_<BI>PLB_NUM_SLAVES Number of PLB slaves Reserved Parameters Figure 9-2: Reserved Parameters Parameter C_BUS_CONFIG C_FAMILY C_INSTANCE C_OPB_NUM_MASTERS C_OPB_NUM_SLAVES C_DCR_AWIDTH C_DCR_DWIDTH Description Defines the bus configuration of the MicroBlaze processor. Platgen automatically populates this parameter. Defines the FPGA device family. Platgen automatically populates this parameter. The C_INSTANCE parameter defines the instance name of the component. Platgen automatically populates this parameter. Defines the number of OPB masters on the bus. Platgen automatically populates this parameter. Defines the number of OPB slaves on the bus. Platgen automatically populates this parameter. Defines the DCR address width. Platgen automatically populates this parameter. Defines the DCR data width. Platgen automatically populates this parameter. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

134 Chapter 9: Platform Specification Utility Figure 9-2: Reserved Parameters (Continued) Parameter C_DCR_NUM_SLAVES C_LMB_AWIDTH C_LMB_DWIDTH C_LMB_NUM_SLAVES C_OPB_AWIDTH C_OPB_DWIDTH C_OPB_NUM_MASTERS C_OPB_NUM_SLAVES C_PLB_AWIDTH C_PLB_DWIDTH C_PLB_MID_WIDTH C_PLB_NUM_MASTERS C_PLB_NUM_SLAVES Signal Naming Conventions Description Defines the number of DCR slaves on the bus. Platgen automatically populates this parameter. Defines the LMB address width. Platgen automatically populates this parameter. Defines the LMB data width. Platgen automatically populates this parameter. Defines the number of LMB slaves on the bus. Platgen automatically populates this parameter. Defines the OPB address width. Platgen automatically populates this parameter. Defines the OPB data width. Platgen automatically populates this parameter. Defines the number of OPB masters on the bus. Platgen automatically populates this parameter. Defines the number of OPB slaves on the bus. Platgen automatically populates this parameter. Defines the PLB address width. Platgen automatically populates this parameter. Defines the PLB data width. Platgen automatically populates this parameter. Defines the PLB master ID width. This is set to log2(s). Platgen automatically populates this parameter. Defines the number of PLB masters on the bus. Platgen automatically populates this parameter. Defines the number of PLB slaves on the bus. Platgen automatically populates this parameter. This section provides naming conventions for bus interface signal names. These conventions are fleible to accommodate embedded processor systems that have more than one bus interface and more than one bus interface port per component. A key concept for cores with more than one bus interface port is the use of a bus identifier, which is attached to all signals grouped together in a port and the parameters that are associated with the bus interface port Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

135 HDL Peripheral Definitions R The names must be HDL compliant. Additional conventions for IP cores are: Global Ports The first character in the name must be alphabetic and uppercase. The fied part of the identifier for each signal must appear eactly as shown in the applicable section below. Each section describes the required signal set for one type of bus interface. If more than one instance of a particular bus interface type is used on a core, the bus identifier <BI> must be used in the signal identifier. The bus identifier can be as simple as a single letter or as comple as a descriptive string with a trailing underscore. The <BI> must be included in the port s signal identifiers in the following cases: i The core has more than one slave PLB port. i The core has more than one master PLB port. i The core has more than one slave LMB port. i The core has more than one slave DCR port. i The core has more than one master DCR port. i The core has more than one OPB port of any type (master, slave, or master/slave). i The core has more than one port of any type and the choice of <Mn> or <Sln> causes ambiguity in the signal names. For eample, a core with both a master OPB port and master PLB port and the same <Mn> string for both ports requires a <BI> string to differentiate the ports since the address bus signal would be ambiguous without <BI>. For cores that have only a single bus interface, which is the case for most peripherals, the use of the bus identifier string in the signal names is optional and the bus identifier is typically not included. The names for the global ports of a peripheral, such as clock and reset signals, are standardized. You can use any name for other global ports, such as the interrupt signal. LMB - Clock and Reset LMB_Clk LMB_Rst OPB - Clock and Reset OPB_Clk OPB_Rst PLB - Clock and Reset PLB_Clk PLB_Rst Embedded System Tools Reference Manual UG111 (v4.0) February 15,

136 Chapter 9: Platform Specification Utility Slave DCR Ports Slave DCR ports must follow these naming conventions: <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain the string DCR (upper, lower, or mied case), so that slave outputs are not confused with bus outputs. <ndcr> is a meaningful name or acronym for the slave input. The last three characters of <ndcr> must contain the string DCR (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single slave DCR port, and required for peripherals with multiple slave DCR ports. <BI> must not contain the string DCR (upper, lower, or mied case). For peripherals with multiple slave DCR ports, the <BI> strings must be unique for each bus interface. If <BI> is present, then <Sln> is optional. DCR Slave Outputs For interconnection to the DCR, all slaves must provide the following outputs: <BI><Sln>_dcrDBus : out std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); <BI><Sln>_dcrAck : out std_logic; Eamples: Uart_dcrAck : out std_logic; Intc_dcrAck : out std_logic; Memcon_dcrAck : out std_logic; Bus1_timer_dcrAck : out std_logic; Bus1_timer_dcrDBus : out std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); Bus2_timer_dcrAck : out std_logic; Bus2_timer_dcrDBus : out std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); DCR Slave Inputs For interconnection to the DCR, all slaves must provide the following inputs: <BI><nDCR>_ABus <BI><nDCR>_DBus <BI><nDCR>_Read <BI><nDCR>_Write Eamples: : in std_logic_vector(0 to C_<BI>DCR_AWIDTH-1); : in std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); : in std_logic; : in std_logic; DCR_DBus : in std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); Bus1_DCR_DBus : in std_logic_vector(0 to C_<BI>DCR_DWIDTH-1); Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

137 HDL Peripheral Definitions R Slave LMB Ports Slave LMB ports must follow these naming conventions: <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain the string LMB (upper, lower, or mied case), so that slave outputs will not be confused with bus outputs. <nlmb> is a meaningful name or acronym for the slave input. The last three characters of <nlmb> must contain the string LMB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single slave LMB port, and required for peripherals with multiple slave LMB ports. <BI> must not contain the string LMB (upper, lower, or mied case). For peripherals with multiple slave LMB ports, the <BI> strings must be unique for each bus interface. If <BI> is present, then <Sln> is optional. LMB Slave Outputs For interconnection to the LMB, all slaves must provide the following outputs: <BI><Sln>_DBus : out std_logic_vector(0 to C_<BI>LMB_DWIDTH-1); <BI><Sln>_Ready : out std_logic; Eamples: D_Ready : out std_logic; I_Ready : out std_logic; LMB Slave Inputs For interconnection to the LMB, all slaves must provide the following inputs: <BI><nLMB>_ABus : in std_logic_vector(0 to C_<BI>LMB_AWIDTH-1); <BI><nLMB>_AddrStrobe : in std_logic; <BI><nLMB>_BE : in std_logic_vector(0 to C_<BI>LMB_DWIDTH/8-1); <BI><nLMB>_Clk : in std_logic; <BI><nLMB>_ReadStrobe : in std_logic; <BI><nLMB>_Rst : in std_logic; <BI><nLMB>_WriteDBus : in std_logic_vector(0 to C_<BI>LMB_DWIDTH-1); <BI><nLMB>_WriteStrobe : in std_logic; Eamples: LMB_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1); DLMB_ABus : in std_logic_vector(0 to C_DLMB_AWIDTH-1); Embedded System Tools Reference Manual UG111 (v4.0) February 15,

138 Chapter 9: Platform Specification Utility Master OPB Ports The signal list shown below applies to master OPB ports that are independent of slave OPB ports. Master OPB ports must follow these naming conventions: <Mn> is a meaningful name or acronym for the master output. <Mn> must not contain the string OPB (upper, lower, or mied case), so that master outputs will not be confused with bus outputs. <nobp> is a meaningful name or acronym for the master input. The last three characters of <nopb> must contain the string OPB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single OPB port (of any type), and required for peripherals with multiple OPB ports (of any type or mi of types). <BI> must not contain the string OPB (upper, lower, or mied case). For peripherals with multiple OPB ports, the <BI> strings must be unique for each bus interface. If <BI> is present, then <Mn> is optional. OPB Master Outputs For interconnection to the OPB, all masters must provide the following outputs: <BI><Mn>_ABus : out std_logic_vector(0 to C_<BI>OPB_AWIDTH-1); <BI><Mn>_BE : out std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1); <BI><Mn>_busLock : out std_logic; <BI><Mn>_DBus : out std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><Mn>_request : out std_logic; <BI><Mn>_RNW : out std_logic; <BI><Mn>_select : out std_logic; <BI><Mn>_seqAddr : out std_logic; Eamples: IM_request : out std_logic; Bridge_request : out std_logic; O2Ob_request : out std_logic; OPB Master Inputs For interconnection to the OPB, all masters must provide the following inputs: <BI><nOPB>_Clk : in std_logic; <BI><nOPB>_DBus : in std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><nOPB>_errAck : in std_logic; <BI><nOPB>_MGrant : in std_logic; <BI><nOPB>_retry : in std_logic; <BI><nOPB>_Rst : in std_logic; <BI><nOPB>_timeout : in std_logic; <BI><nOPB>_ferAck : in std_logic; Eamples: IOPB_DBus : in std_logic_vector(0 to C_IOPB_DWIDTH-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); Bus1_OPB_DBus : in std_logic_vector(0 to C_Bus1_OPB_DWIDTH-1); Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

139 HDL Peripheral Definitions R Slave OPB Ports The signal list shown below applies to master OPB ports that are independent of slave OPB ports. For the signal list for cores that use a combined master/slave bus interface, see XXX. Slave OPB ports must follow these naming conventions: <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain the string OPB (upper, lower, or mied case), so that slave outputs are not confused with bus outputs. <nopb> is a meaningful name or acronym for the slave input. The last three characters of <nopb> must contain the string OPB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single OPB port, and required for peripherals with multiple OPB ports (of any type). <BI> must not contain the string OPB (upper, lower, or mied case). For peripherals with multiple OPB ports (of any type or mi of types), the <BI> strings must be unique for each bus interface. If <BI> is present, then <Sln> is optional. OPB Slave Outputs For interconnection to the OPB, all slaves must provide the following outputs: <BI><Sln>_DBus : out std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><Sln>_errAck : out std_logic; <BI><Sln>_retry : out std_logic; <BI><Sln>_toutSup : out std_logic; <BI><Sln>_ferAck : out std_logic; Eamples: Tmr_ferAck : out std_logic; Uart_ferAck : out std_logic; Intc_ferAck : out std_logic; OPB Slave Inputs For interconnection to the OPB, all slaves must provide the following inputs: <BI><nOPB>_ABus : in std_logic_vector(0 to C_<BI>OPB_AWIDTH-1); <BI><nOPB>_BE : in std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1); <BI><nOPB>_Clk : in std_logic; <BI><nOPB>_DBus : in std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><nOPB>_Rst : in std_logic; <BI><nOPB>_RNW : in std_logic; <BI><nOPB>_select : in std_logic; <BI><nOPB>_seqAddr : in std_logic; Eamples: OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); IOPB_DBus : in std_logic_vector(0 to C_IOPB_DWIDTH-1); Bus1_OPB_DBus : in std_logic_vector(0 to C_Bus1_OPB_DWIDTH-1); Embedded System Tools Reference Manual UG111 (v4.0) February 15,

140 Chapter 9: Platform Specification Utility Master/Slave OPB Ports The signal list shown below applies to master/slave type OPB ports that attach to the same OPB bus and share the input and output data buses. This type of bus interface is typically used when a peripheral has both master and slave functionality, typical when DMA is included with the peripheral, and it is advantageous for the master and slave to share the input and output data buses. Master/Slave OPB ports must follow these naming conventions: <Mn> is a meaningful name or acronym for the master output. <Mn> must not contain the string OPB (upper, lower, or mied case), so that master outputs are not confused with bus outputs. <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain the string OPB (upper, lower, or mied case), so that slave outputs are not confused with bus outputs. <nopb> is a meaningful name or acronym for the slave input. The last three characters of <nopb> must contain the string OPB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single OPB port, and required for peripherals with multiple OPB ports (of any type). <BI> must not contain the string OPB (upper, lower, or mied case). For peripherals with multiple OPB ports (of any type or mi of types), the <BI> strings must be unique for each bus interface. If <BI> is present, then <Sln> and <Mn> are optional. OPB Master/Slave Outputs For interconnection to the OPB, all master/slaves must provide the following outputs: <BI><Sln>_ABus : out std_logic_vector(0 to C_<BI>OPB_AWIDTH-1); <BI><Sln>_BE : out std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1); <BI><Sln>_busLock : out std_logic; <BI><Sln>_request : out std_logic; <BI><Sln>_RNW : out std_logic; <BI><Sln>_select : out std_logic; <BI><Sln>_seqAddr : out std_logic; <BI><Sln>_DBus : out std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><Sln>_errAck : out std_logic; <BI><Sln>_retry : out std_logic; <BI><Sln>_toutSup : out std_logic; <BI><Sln>_ferAck : out std_logic; Eamples: IM_request : out std_logic; Bridge_request : out std_logic; O2Ob_request : out std_logic; Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

141 HDL Peripheral Definitions R OPB Master/Slave Inputs For interconnection to the OPB, all master/slaves must provide the following inputs: <BI><nOPB>_ABus : in std_logic_vector(0 to C_<BI>OPB_AWIDTH-1); <BI><nOPB>_BE : in std_logic_vector(0 to C_<BI>OPB_DWIDTH/8-1); <BI><nOPB>_Clk : in std_logic; <BI><nOPB>_DBus : in std_logic_vector(0 to C_<BI>OPB_DWIDTH-1); <BI><nOPB>_errAck : in std_logic; <BI><nOPB>_MGrant : in std_logic; <BI><nOPB>_retry : in std_logic; <BI><nOPB>_RNW : in std_logic; <BI><nOPB>_Rst : in std_logic; <BI><nOPB>_select : in std_logic; <BI><nOPB>_seqAddr : in std_logic; <BI><nOPB>_timeout : in std_logic; <BI><nOPB>_ferAck : in std_logic; Eamples: Master PLB Ports IOPB_DBus : in std_logic_vector(0 to C_IOPB_DWIDTH-1); OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1); Bus1_OPB_DBus : in std_logic_vector(0 to C_Bus1_OPB_DWIDTH-1); Master PLB ports must follow these naming conventions: <Mn> is a meaningful name or acronym for the master output. <Mn> must not contain the string PLB (upper, lower, or mied case), so that master outputs are not confused with bus outputs. <nplb> is a meaningful name or acronym for the master input. The last three characters of <nopb> must contain the string PLB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single master PLB port, and required for peripherals with multiple master PLB ports. <BI> must not contain the string PLB (upper, lower, or mied case). For peripherals with multiple master PLB ports, the <BI> strings must be unique for each bus interface. If <BI> is present, then <Mn> is optional. PLB Master Outputs For interconnection to the PLB, all masters must provide the following outputs: <BI><Mn>_ABus : out std_logic_vector(0 to C_<BI>PLB_AWIDTH-1); <BI><Mn>_BE : out std_logic_vector(0 to C_<BI>PLB_DWIDTH/8-1); <BI><Mn>_RNW : out std_logic; <BI><Mn>_abort : out std_logic; <BI><Mn>_busLock : out std_logic; <BI><Mn>_compress : out std_logic; <BI><Mn>_guarded : out std_logic; <BI><Mn>_lockErr : out std_logic; <BI><Mn>_MSize : out std_logic; <BI><Mn>_ordered : out std_logic; <BI><Mn>_priority : out std_logic_vector(0 to 1); <BI><Mn>_rdBurst : out std_logic; <BI><Mn>_request : out std_logic; Embedded System Tools Reference Manual UG111 (v4.0) February 15,

142 Chapter 9: Platform Specification Utility <BI><Mn>_size : out std_logic_vector(0 to 3); <BI><Mn>_type : out std_logic_vector(0 to 2); <BI><Mn>_wrBurst : out std_logic; <BI><Mn>_wrDBus : out std_logic_vector(0 to C_<BI>PLB_DWIDTH-1); Eamples: IM_request : out std_logic; Bridge_request : out std_logic; O2Ob_request : out std_logic; PLB Master Inputs For interconnection to the PLB, all masters must provide the following inputs: <BI><nPLB>_Clk : in std_logic; <BI><nPLB>_Rst : in std_logic; <BI><nPLB>_AddrAck : in std_logic; <BI><nPLB>_Busy : in std_logic; <BI><nPLB>_Err : in std_logic; <BI><nPLB>_RdBTerm : in std_logic; <BI><nPLB>_RdDAck : in std_logic; <BI><nPLB>_RdDBus : in std_logic_vector(0 to C_<BI>PLB_DWIDTH-1); <BI><nPLB>_RdWdAddr : in std_logic_vector(0 to 3); <BI><nPLB>_Rearbitrate : in std_logic; <BI><nPLB>_SSize : in std_logic_vector(0 to 1); <BI><nPLB>_WrBTerm : in std_logic; <BI><nPLB>_WrDAck : in std_logic; Eamples: Slave PLB Ports IPLB_MBusy : in std_logic; Bus1_PLB_MBusy : in std_logic; Slave PLB ports must follow these naming conventions: <Sln> is a meaningful name or acronym for the slave output. <Sln> must not contain the string PLB (upper, lower, or mied case), so that slave outputs are not confused with bus outputs. <nplb> is a meaningful name or acronym for the slave input. The last three characters of <nplb> must contain the string PLB (upper, lower, or mied case). <BI> is a Bus Identifier; it is optional for peripherals with a single slave PLB port, and required for peripherals with multiple slave PLB ports. <BI> must not contain the string PLB (upper, lower, or mied case). For peripherals with multiple PLB ports, the <BI> strings must be unique for each bus interface. If <BI> is present, then <Sln> is optional Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

143 HDL Peripheral Definitions R PLB Slave Outputs For interconnection to the PLB, all slaves must provide the following outputs: <BI><Sln>_addrAck : out std_logic; <BI><Sln>_MErr : out std_logic_vector(0 to C_<BI>PLB_NUM_MASTERS-1); <BI><Sln>_MBusy : out std_logic_vector(0 to C_<BI>PLB_NUM_MASTERS-1); <BI><Sln>_rdBTerm : out std_logic; <BI><Sln>_rdComp : out std_logic; <BI><Sln>_rdDAck : out std_logic; <BI><Sln>_rdDBus : out std_logic_vector(0 to C_<BI>PLB_DWIDTH-1); <BI><Sln>_rdWdAddr : out std_logic_vector(0 to 3); <BI><Sln>_rearbitrate : out std_logic; <BI><Sln>_SSize : out std_logic(0 to 1); <BI><Sln>_wait : out std_logic; <BI><Sln>_wrBTerm : out std_logic; <BI><Sln>_wrComp : out std_logic; <BI><Sln>_wrDAck : out std_logic; Eamples: Tmr_addrAck : out std_logic; Uart_addrAck : out std_logic; Intc_addrAck : out std_logic; PLB Slave Inputs For interconnection to the PLB, all slaves must provide the following inputs: <BI><nPLB>_Clk : in std_logic; <BI><nPLB>_Rst : in std_logic; <BI><nPLB>_ABus : in std_logic_vector(0 to C_<BI>PLB_AWIDTH-1); <BI><nPLB>_BE : in std_logic_vector(0 to C_<BI>PLB_DWIDTH/8-1); <BI><nPLB>_PAValid : in std_logic; <BI><nPLB>_RNW : in std_logic; <BI><nPLB>_abort : in std_logic; <BI><nPLB>_busLock : in std_logic; <BI><nPLB>_compress : in std_logic; <BI><nPLB>_guarded : in std_logic; <BI><nPLB>_lockErr : in std_logic; <BI><nPLB>_masterID : in std_logic_vector(0 to C_<BI>PLB_MID_WIDTH-1); <BI><nPLB>_MSize : in std_logic_vector(0 to 1); <BI><nPLB>_ordered : in std_logic; <BI><nPLB>_pendPri : in std_logic_vector(0 to 1); <BI><nPLB>_pendReq : in std_logic; <BI> _reqpri : in std_logic_vector(0 to 1); <BI><nPLB>_size : in std_logic_vector(0 to 3); <BI><nPLB>_type : in std_logic_vector(0 to 2); <BI><nPLB>_rdPrim : in std_logic; <BI><nPLB>_SAValid : in std_logic; <BI><nPLB>_wrPrim : in std_logic; <BI><nPLB>_wrBurst : in std_logic; <BI><nPLB>_wrDBus : in std_logic_vector(0 to C_<BI>PLB_DWIDTH-1); <BI><nPLB>_rdBurst : in std_logic; Eamples: PLB_size : in std_logic_vector(0 to 3); IPLB_size : in std_logic_vector(0 to 3); DPLB_size : in std_logic_vector(0 to 3); Embedded System Tools Reference Manual UG111 (v4.0) February 15,

144 Chapter 9: Platform Specification Utility Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

145 Chapter 10 Format Revision Tool The Format Revision Tool (revup) updates an eisting EDK 6.1, 6.2, or 6.3 project to an EDK 7.1 project. If you open a project from 6.1, 6.2, or 6.3 in XPS 7.1, it automatically revs up the project to the new release. XPS 7.1 does not update projects from EDK 3.2 or older tool release. You must use revup32to61 utility tool provided with all of the EDK 6.* tool releases. The revup in EDK 7.1 creates a backup of the current project files and then updates the eisting ones. The following files are backed up before revup: system.mp as system_mp.63 Tool Usage Limitations system.mhs as system_mhs.63 system.mss as system_mss.63 system.log as system_log.63 The contents of the log file are also cleared after creating a backup. None of the IP or driver data files (such as MPD and MDD files) need to be updated. If your project is an EDK 6.1 project, then revup updates the MSS files. It also creates software applications based on previous project settings. All changes are done automatically and no input is required. The revup tool only performs synta updates. If any IP or driver used in your project has become obsolete or been removed, you must also manually update your projects. Run the revision tool as follows from the command line: revup system.mp The following option is supported: -h (Help) Displays the usage menu and then quits. The revup tool has the following limitations: It can only revup EDK 6.1, 6.2, or 6.3 projects. You must revup older projects separately to EDK 6.1. It only performs format rev up. If any IP or driver has been marked OBSOLETE in EDK 6.3, you must manually change the design to the latest versions of IP. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

146 Chapter 10: Format Revision Tool Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

147 Chapter 11 Bitstream Initializer This chapter describes the Bitstream Initializer (BitInit) utility. The chapter contains the following sections. Overview Tool Usage Tool Options Overview BitInit initializes the instruction memory of processors on the FPGA. The instruction memory of processors is stored in BlockRAMs in the FPGA. This utility reads an MHS file, and invokes the Data2MEM utility provided in ISE to initialize the FPGA BlockRAMs. Tool Usage The BitInit tool is invoked as follows: bitinit <mhsfile> [options] Note: You must specify <mhsfile> before specifying other tool options. Tool Options The following options are supported in the current version of BitInit: Table 11-1: BitInit Synta Options Option Command Description Display Help -h Displays the usage menu and then quits. Display version -v Displays the version and then quits. Input BMM file -bm Specifies the input BMM file which contains the address map and the location of the instruction memory of the processor. Default: implementation/<sysname>_bd.bmm Bitstream file -bt Specifies the input bitstream file that does not have its memory initialized. Default: implementation/<sysname>.bit Embedded System Tools Reference Manual UG111 (v4.0) February 15,

148 Chapter 11: Bitstream Initializer Table 11-1: BitInit Synta Options (Continued) Option Command Description Output bitstream file -o Specifies the name of the output file to generate the bitstream with initialized memory. Default: implementation/download.bit Specify the Processor Instance name and list of ELF files -pe Specifies the name of the processor instance in the MHS and its associate list of ELF files that form its instruction memory. This option can be repeated several times based on the number of processor instances in the design. Libraries path -lp Specifies the path to repository libraries. This option can be repeated to specify multiple libraries. Log file name -log Specifies the name of the log file to capture the log. Default: bitinit.log Quiet mode -quiet Runs the tool in quiet mode. Note: BitInit also produces a file named data2mem.dmr that is the log file generated during invocation of the Data2MEM utility Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

149 Chapter 12 Programming Flash Memory Overview Prerequisites The Program Flash Memory dialog bo allows you to program eternal Compact Flash Interface (CFI) compliant parallel flash parts on your board, connected through the opb_emc/plb_emc eternal memory controller IP cores. The programming is done using a small in-system flash writing program that eecutes on the target processor of your design. A host TCL script drives the in-system flashwriter with commands and data and completes the flash programming. The dialog bo does not process or interpret the image file to be programmed and routinely programs the file as-is onto flash memory. Your software and hardware application setup must infer the contents of the file being programmed as desired. The following prerequisites must be satisfied before you use the Program Flash dialog bo: You must launch the dialog bo from within a suitable EDK project; the dialog bo infers and works on data from the currently open EDK project. The dialog bo assumes that your hardware design has correct connections between the flash and at least one processor through the OPB/PLB EMC peripherals. You must make sure that the target board is connected to the host via JTAG and the FPGA is initialized with the bitstream of the project because the dialog bo works by downloading and eecuting a flashwriter program. The Debug Settings dialog bo has been used to specify the up-to-date debugger information about the design. You must do the Generate Libraries and BSP step prior to this, since the flashwriter uses the processor s libraries. This step is described in Software Flow on page 42. The flashwriter requires at least 32KB of free space to eecute from in your design. The programming mode used in this case is Streaming mode. The flashwriter can also work in batch or one-shot mode, by storing the entire image file to be programmed into memory and then quickly iterating through it and writing to flash. This mode can be useful for programming large images of hundreds of kilobytes or greater. The one-shot mode also greatly improves the programming speed of the flashwriter. However, this mode requires free memory in the design equal to 32 KB plus the size of the image being programmed. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

150 Chapter 12: Programming Flash Memory Supported Flash Hardware The flashwriter program uses the Compact Flash Interface (CFI) to query the flash parts. Hence it requires that the flash part be CFI compliant. Table 12-1 lists the flash configurations that are supported. Table 12-1: The above physical layout, geometry information and other logical information such as command sets understood are determined by using the CFI. Currently, the flashwriter can handle flash parts that can understand the CFI defined command sets listed in Table The flashwriter program, by default, only supports flash parts that have a sector map that is eactly as stored in the CFI table. Some flash vendors are known to store a different sector map in the CFI table, while having a different sector map in hardware, based on the boot topology of the flash part. Refer to the Customizing Flash Programming section for more information on how to work around this. Using the Program Flash Memory Dialog Bo File to Program Auto Convert File Supported Flash Configurations Single 16-bit device forming a 16-bit data bus Paired 8-bit devices forming a 16-bit data bus Single 32-bit device forming a 32-bit data bus Paired 16-bit devices forming a 32-bit data bus Four 8-bit devices forming a 32-bit data bus Table 12-2: CFI Defined Command Sets Vendor ID OEM Sponsor Interface Name 1 Intel/Sharp Intel/Sharp Etended Command Set 2 AMD/Fujitsu AMD/Fujitsu Standard Command Se 3 Intel Intel Standard Command Set 4 AMD/Fujitsu AMD/Fujitsu Etended Command Set Click on Tools -> Program Flash Memory to open the Program Flash Memory dialog bo. Enter the following information in the Program Flash Memory dialog bo. Choose the file that you wish to program onto the flash part, by browsing to the file and selecting it, or entering the file's path in the tet bo. Select the Auto convert file check bo if the file to program onto the flash part must be converted and stored on the flash part in an image format. Select the image format, such as SREC, from the drop-down list. The auto convert file option is available only when the file to program is in ELF format. This option is useful when creating bootloaders and the ELF image of the bootloader must be converted into a common bootloader image format such as SREC Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

151 Using the Program Flash Memory Dialog Bo R Download Mode Select from one-shot or streaming. One-shot mode requires that you have enough memory to accommodate both the flashwriter program and the image file. i.e at least (32K + size of the image file) bytes of memory free. If choosing streaming mode, then you require at least 32K of free memory. Processor Instance Choose the processor that is connected to your flash parts via an EMC controller. This processor will be used to eecute the flashwriter program. Flash Memory Properties Instance Name Choose the instance name of the memory controller that interfaces to the flash parts on your target board. Program At Offset Choose an offset within the flash to start programming the image file to. If you want to program different file images at different parts of the flash, you would be changing this parameter each time to choose a different position within the flash to program the file. Scratch Pad Memory Properties Instance Name Choose the instance name of the memory controller that connects to the free scratch pad memory, that you wish to use for storing the flashwriter (and the image file if using oneshot programming mode). It must satisfy size constraints as described earlier. Do not select the same memory controller as that of the Flash Memory. Create Flash Bootloader Select the Create Flash Bootloader check bo if a bootloader application is to be automatically created for this configuration. SW Application Project Program Flash In the SW Application Project field, specify the name of the bootloader application. The name of the bootloader is initialized with an auto-generated value, but you can change this value if required. Click the Program Flash button to start the flash writer. The dialog bo launches XMD in the XPS console. The rest of the algorithm proceeds from the XMD console. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

152 Chapter 12: Programming Flash Memory Customizing Flash Programming The flash programming setup that has been described above, might not fit your requirements eactly - there could be hardware incompatibilities, flash command set incompatibilities, memory size constraints etc. This section briefly describes the internals of the flash programming algorithm. Knowing this, you can plug in and replace pieces of the flow to customize it for your particular setup. When you click on the Program flash button, then the following sequence of events happen. 1. A flash_params.tcl file is written out to the etc/ folder. This contains parameters that describe the flash programming session and is used by the flashwriter TCL. 2. XPS launches XMD with the flashwriter TCL script eecuting on it with a command such as, md -tcl flashwriter.tcl. This flashwriter host TCL comes from the installation. If you wish to run your own driver TCL when the Program Flash button is clicked, place a copy of the flashwriter.tcl file, in your project s root directory. XMD searches for the specified file to be present in your project directory first, before looking for it in the repository. 3. The flashwriter TCL script, copies over the flashwriter application's source files from the installation to the etc/flashwriter folder. It compiles the application locally to eecute out of the scratch memory address that was chosen. Here again, if you wish to compile your own flash writer sources, then you would modify your local copy of the flashwriter.tcl script to compile your own sources instead of the sources from the installation. 4. The script downloads the flashwriter to the processor. The script communicates with the flashwriter program, through mailboes in memory. In other words, it writes parameters to the memory locations corresponding to variables in the flashwriter address space and lets the flashwriter eecute. 5. The script waits for the flashwriter to invoke a callback function at the end of each operation and stops the application at the callback function by setting a breakpoint at the function. Once the flashwriter is stopped, the host TCL processes the results and then continues with more commands as required. 6. While programming, the flashwriter erases as only many flash blocks as required, to store the image in. 7. If programming in one shot, the TCL downloads the entire image to memory and lets the flashwriter complete the programming operation. If programming in streaming mode, it iteratively streams each block of the image file and lets the flashwriter program the flashpart in chunks. It stores these chunks in a memory buffer located within the flashwriter. 8. Once the programming is done, the flashwriter TCL sends an eit command to the flashwriter and terminates the XMD session. Here is an eample of steps that you would do for a custom flow, 1. Copy over flashwriter.tcl from <edk_install>/data/md/flashwriter.tcl to your EDK project folder 2. Create a directory within your EDK project, called sw_services (if it does not eist already). 3. Copy over the entire <edk_install>/data/md/flashwriter directory to the sw_services directory Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

153 Customizing Flash Programming R 4. Edit the following line in the flashwriter.tcl that you copied over set flashwriter_src [file join $ilin_edk "data" "md" "flashwriter" "src"] to set flashwriter_src [file join. "sw_services" "flashwriter" "src"] 5. Now everytime that you use the Program Flash Memory dialog bo, the script that you copied over and the sources you copied to the sw_services directory will be the ones that are used by the dialog bo. So you are free to customize these as you wish. 6. If you wish to not have the GUI overwrite the etc/flash_params.tcl file, you will have to run the command md -tcl flashwriter.tcl on the command line to just use the values that you fill in the etc/flash_params.tcl file. The various parameters in the etc/flash_params.tcl file are listed in Table 12-3 Table 12-3: FLASH_FILE Flash Programming Parameters Variable Function This a string containing the full path of the file to be programmed. FLASH_PROG_MODE STREAMING or ONESHOT - chooses the mode to program the file in. FLASH_BASEADDR FLASH_PROG_OFFSET SCRATCH_BASEADDR XMD_CONNECT PROC_INSTANCE The base address of the flash memory bank. The offset within the flash memory bank at which the programming should be done. The base address of the scratch memory used during programming. The connect command used in XMD to connect to the processor. The instance name of the processor used for programming. TARGET_TYPE MicroBlaze or PowerPC 405. The type of the processor instance used for programming. Handling Flash Parts with Conflicting Sector Layouts As mentioned earlier, some flash vendors are known to store a different sector map in the CFI table, while having a different sector map in hardware, based on the boot topology of the flash part. Since the boot topology information is not standardized in CFI, the flashwriter will have no way of determining what kind of layout your particular flash part will have. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

154 Chapter 12: Programming Flash Memory Using Flash Memory If your flash hardware has a sector layout that is different from what is stored in the CFI table of the part, then you will need to do a custom flash programming flow. You will need to find out if your flash part is a top-boot flash part or a bottom-boot flash part. A top-boot flash part is one, in which the smallest sectors are the last sectors in the flash. A bottomboot flash part is one in which the smallest sectors are the first sectors in the flash layout. Once you know this, you will have to copy over the files, as described earlier, to do a custom programming flow. If you have a bottom boot flash, you will have to add the following line in the etc/flash_params.tcl file - set FLASH_BOOT_CONFIG BOTTOM_BOOT_FLASH If you have a top-boot flash, then the line becomes - set FLASH_BOOT_CONFIG TOP_BOOT_FLASH Once you have entered this line, you would need to run the flash programming from the command line with the command, md -tcl flashwriter.tcl Internally, these variables will make the flashwriter rearrange the sector map according to the boot topology. Typically, you can program three different kinds of things in flash Eecutable/bootable images of applications Hardware bitstreams for your FPGA File system images, data files such as sample data, algorithmic tables etc. The first use case is most common. When the processor on your design comes out of reset, it will start eecuting code stored in BRAM at the processor s reset location. Typically, BRAM is too small (in the order of a few kilobytes) to accommodate your entire software application image. Therefore, you can store your software application image in flash memory (typically in the order of megabytes). A small bootloader is then designed to fit in BRAM and upon reset, start reading the software application image from flash memory, copy it over to larger and more available eternal memory and then transfer control to your software application, which then continues. Your software application that you build out of your project is in eecutable ELF format. Storing and bootloading the ELF image itself is not usually done. This is because, bootloading an ELF image, increases the compleity of the bootloader. Instead, this ELF image is converted to one of the common bootloadable image formats, such as SREC or IHEX. The bootloader then becomes very simple and therefore smaller. Customizing the Bootloader To help you get quickly started with bootloading your software application from flash, you can create a simple bootloader automatically in the Program Flash Memory dialog bo. It is capable of booting an image file in SREC format (Motorola S-record format), given the location of the image in some memory. This bootloader has been designed to obtain the image file from flash memory, which is epected to have been programmed with the image prior to invoking the bootloader. You can also subsequently modify these sources to adapt the bootloader for any specific scenario or for adding new capabilities to it to fit your needs Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

155 Converting ELF to SREC R Converting ELF to SREC If you want to manually create some SREC images of your ELF file instead of using the auto-convert feature in the Program Flash dialog bo, you can use the command line tools. For eample, for a final software application image named myeecutable.elf, navigate in the console of your operating system (Cygwin on Windows platforms) to the folder containing this ELF file and type the following: <platform>-objcopy -O srec myeecutable.elf myeecutable.srec where platform is powerpc-eabi if your processor is PPC405, or mb if your processor is MicroBlaze. This creates an SREC file that you can then use as appropriate. The utilities mb-objcopy and powerpc-eabi-objcopy are GNU binary utilities that ship with EDK. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

156 Chapter 12: Programming Flash Memory Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

157 Chapter 13 GNU Compiler Tools EDK includes the GNU compiler tools for both the PowerPC and MicroBlaze processors. The GCC tools are built out of the open source GCC version sources. This chapter describes the various options supported by MicroBlaze and PowerPC GNU tools. The MicroBlaze GNU tools include mb-gcc compiler, mb-as assembler and mb-ld loader/linker. The PowerPC tools include powerpc-eabi-gcc compiler, powerpc-eabi-as assembler and the powerpc-eabi-ld linker. The EDK GNU tools also support C++. This chapter discusses only those GNU options which were added or enhanced for the Embedded Development Kit (EDK). This chapter contains the following sections. GNU Compiler Framework Compiler Usage and Options File Etensions Compiler Interface MicroBlaze GNU Compiler PowerPC GNU Compiler GNU Compiler Framework Input C/C++ Files cpp0 cc1 cc1plus as (mb-as or powerpc-eabi-as) Libraries ld (mb-ld or powerpc-eabi-ld) Output Elf File Figure 13-1: GNU Tool Flow Embedded System Tools Reference Manual UG111 (v4.0) February 15,

158 Chapter 13: GNU Compiler Tools This section discusses the common features of both the MicroBlaze and PowerPC compilers. Figure 13-1 displays the GNU tool flow. The GNU compiler is named mb-gcc for MicroBlaze and powerpc-eabi-gcc for PowerPC. The GNU compiler is a wrapper which in turn calls four different eecutables: Pre-processor (cpp0) This is the first pass invoked by the compiler. The pre-processor replaces all macros with definitions as defined in the source and header files. Machine and Language specific Compiler (cc1) The compiler works on the preprocessed code, which is the output of the first stage. i C Compiler (cc1) The compiler is responsible for most of the optimizations done on the input C code and generates an assembly code. i C++ Compiler (cc1plus) The compiler is responsible for most of the optimizations done on the input C++ code and generates an assembly code. Assembler (mb-as for MicroBlaze and powerpc-eabi-as for PowerPC) The assembly code has mnemonics in assembly language. The assembler converts these to machine language. The assembler also resolves some of the labels generated by the compiler. It creates an object file, which is passed on to the linker. Linker (mb-ld for MicroBlaze and powerpc-eabi-ld for PowerPC) The linker links all the object files generated by the assembler. If libraries are provided on the command line, the linker resolves some of the undefined references in the code by linking in some of the functions from the assembler. Options for all these eecutables in discussed later in this chapter. Note: All references to gcc in this chapter indicate reference to both the MicroBlaze compiler, mbgcc, and the PowerPC compiler, powerpc-eabi-gcc. Compiler Usage and Options Usage To use the GNU Compiler, type: Compiler_Name options files... where Compiler_Name is powerpc-eabi-gcc or mb-gcc. Quick Reference Table 13-1 displays the commonly used compiler options. These options are common to both the compilers for MicroBlaze and PowerPC. The compiler options are case sensitive Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

159 Compiler Usage and Options R Table 13-1: Commonly Used Compiler Options Options Eplanation -E Preprocess only; do not compile, assemble and link. The preprocessed output displays on the standard out device. -S Compile only; do not assemble and link. Generates a.s file. -c Compile and Assemble only; do not link. Generates a.o file. -g Add debugging information, which is used by the GNU debugger: mb-gdb or powerpc-eabi-gdb. -gstabs -Wa,option -Wp,option -Wl,option Add debugging information to the compiled assembly file. Pass this option directly to the GNU assembler or through the -Wa option to the Compiler. Pass comma-separated option to the assembler. Pass comma-separated option to the preprocessor. Pass comma-separated option to the linker. -B directory Add directory to the C-run time library search paths. -L directory Add directory to library search path. -I directory Add directory to header search path. -l library Search library a for undefined symbols. -v Verbose. Display the programs invoked by the compiler. -o filename Place the output in the filename. -save-temps --help Store the intermediate files produced at the end of each pass. Display a short listing of options. -O n Specify Optimization level; n = 0,1,2,3. a. The compiler prefies lib to the library name indicated in this command line switch. Compiler Options -g This section discusses some of the compiler options in detail. This option adds debugging information to the output file. The debugging information is required by the GNU Debugger, mb-gdb or powerpc-eabi-gdb. The debugger provides debugging at the source and the assembly level. This option adds debugging information only when the input is a C/C++ source file. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

160 Chapter 13: GNU Compiler Tools -gstabs -On Use this option for adding debugging symbols to assembly (.S) files. This is an assembler option and should be provided directly to the GNU assembler, mb-as or powerpc-eabi-as. If an assembly file is compiled using the compiler mb-gcc or powerpc-eabi-gcc, prefi the option with -Wa,. The GNU compiler provides optimizations at different levels. These optimization levels apply only to the C and C++ source files. Table 13-2: n Optimizations for Values of n 0 No Optimization 1 Medium Optimization 2 Full optimization Optimization 3 Full optimization Attempt automatic inlining of small subprograms. S Optimize for speed -v Note: Optimization levels 1 and above cause code re-arrangement. While debugging your code, use of no optimization level is recommended. When an optimized program is debugged through gdb, the displayed results might seem inconsistent. This option eecutes the compiler and all the tools underneath the compiler in verbose mode. This option gives complete description of the options passed to all the tools. This description is helpful in discovering the default options for each tool. -save-temps The GNU compiler provides a mechanism to save all the intermediate files generated during the compilation process. The compiler stores the following files: i i Preprocessor output input_file_name.i for C code and input_file_name.ii for C++ code Compiler (cc1) output in assembly format input_file_name.s i Assembler output in ELF format input_file_name.s The compiler saves the default output of the entire compilation as a.out. -o filename The compiler stores the default output of the compilation process in an ELF file named a.out. You can change the default name using -o output_file_name. The output file is created in ELF format Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

161 Compiler Usage and Options R -Wp,option, -Wa,option, and -Wl,option --help The compiler, mb-gcc or powerpc-eabi-gcc, is a wrapper around other eecutables such as the preprocessor, compiler (cc1), assembler, and the linker. You can run these components of the compiler individually or through the top level compiler. There are certain options that are required by tools, but might not be necessary for the top level compiler. To run these commands, use the options as indicated in Table Table 13-3: Tool-Specific Options Passed to the Top-Level GCC Compiler Option Tool -Wp,option -Wa,option -Wl,option Use this option with any GNU compiler to get more information about the available options. You can also consult the GCC manual, available online at Library Search Options -l libraryname By default, the compiler searches only the standard libraries such as libc, libm and libil. You can create your own libraries containing some commonly used functions. You can specify the name of the library and where the compiler can find the definition of these functions. The compiler prefies lib to the library name that you provide. The compiler is sensitive to the order in which you provide options, particularly the -l command line switch. Provide this switch only after all of the sources in the command line. For eample, if you create your own library called libproject.a., you can include functions from this library using the following command: Compiler Source_Files -L${LIBDIR} -lproject Caution! If you supply the library flag -l library name before the source files, the compiler will not be able to find the functions called from any of the sources. This is because the compiler search is only done in one direction and does not keep a list of libraries available. -L Lib Directory This option indicates the directories in which to search for the libraries. The compiler has a default library search path, where it looks for the standard library. By using the -L option, you can include some additional directories in the compiler search path. Header File Search Option -I Directory Name Preprocessor Assembler Linker The option -I indicates to search for header files in the directory Directory Name before searching the header files in the standard path. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

162 Chapter 13: GNU Compiler Tools Linker Options -defsym _STACK_SIZE=value The total memory allocated for the stack can be modified using this linker option. The variable STACK_SIZE is the total space allocated for the stack. The variable STACK_SIZE is given the default value of 100 words, or 400 bytes. If your program is epected to need more than 400 bytes for stack and heap combined, it is recommended that you increase the value of STACK_SIZE using this option. The value is in bytes. In certain cases, a program might need a bigger stack. If the stack size required by the program is greater than the stack size available, the program tries to write in other forbidden sections of the code, leading to wrong eecution of the code. Note: For MicroBlaze systems, a minimum stack size of 16 bytes (00010) is required for programs linked with the C runtime routines (crt0.o and crt1.o). -defsym _HEAP_SIZE=value Linker Scripts Search Paths The total memory allocated for the heap can be controlled by the value given to the variable_heap_size. The default value of _HEAP_SIZE is 0. Dynamic memory allocation routines use the heap. If your program uses the heap in this fashion, then you would need to provide a reasonable value for the _HEAP_SIZE. The linker utility makes use of the linker scripts to divide your program on different blocks of memories. To provide a linker script on the gcc command line, use the following command line option: compiler -Wl,-T -Wl,linker_script <Other Options and Input Files> If the linker is eecuted on its own, the linker script to included is as follows: linker -T linker_script <Other Options and Input Files> For more information about usage of linker scripts, refer to the Address Management chapter in the Platform Studio User Guide. The compilers, mb-gcc and powerpc-eabi-gcc, search certain paths for libraries and header files. Solaris Search Paths The compilers search libraries in the following order: 1. Directories are passed to the compiler with the -L dir name option. 2. Directories are passed to the compiler with the -B dir name option. 3. ${XILINX_EDK}/gnu/processor (1) /sol/microblaze/lib 4. ${XILINX_EDK}/lib/processor 1. Processor indicates powerpc-eabi for PowerPC and microblaze for MicroBlaze Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

163 File Etensions R File Etensions Header files are searched in the following order: 1. Directories are passed to the compiler with the -I dir name option.$ 2. ${XILINX_EDK}/gnu/processor/sol/processor/include Initialization files are searched in the following order (1) : 1. Directories are passed to the compiler with the -B dir name option. 2. ${XILINX_EDK}/gnu/processor/sol/processor/lib On Windows Cygwin Shell The compilers search libraries in the following order: 1. Directories are passed to the compiler with the -L dir name option. 2. Directories are passed to the compiler with the -B dir name option. 3. %XILINX_EDK%/gnu/processor/nt/processor/lib 4. %XILINX_EDK%/lib/processor The compilers search header files in the following order: 1. Directories are passed to the compiler with the -I dir name option.$ 2. %XILINX_EDK%/gnu/processor/nt/processor/include The compilers search initialization files in the following order: 1. Directories are passed to the compiler with the -B dir name option. 2. %XILINX_EDK%/gnu/processor/nt/processor/lib File Types and Etensions The GNU compiler determines the type of your file from the file etension. Table 13-4 illustrates the valid etensions and the corresponding file types. The gcc wrapper calls the appropriate lower level tools by recognizing these file types. Table 13-4: File Etensions Etension.c C File.C C++ File.c C++ File.cpp C++ File.c++ C++ File.cc C++ File File type 1. Initialization files such as crt0.o are searched by the compiler only for mb-gcc. For powerpc-eabi-gcc, the C runtime library is a part of the library and is picked up by default from the library libil.a. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

164 Chapter 13: GNU Compiler Tools Table 13-4: File Etensions (Continued) Etension File type.s Assembly File, but might have preprocessor directives.s Assembly File with no preprocessor directives Libraries Both of the compilers, powerpc-eabi-gcc and mb-gcc, use certain libraries. The following libraries are necessary for the programs. Table 13-5: Library libil.a libc.a libm.a Libraries Used by the Compilers Particular Contain drivers, software services (such as XilNet & XilMFS) and initialization files developed for the EDK tools Standard C libraries, including functions like strcmp and strlen Math Library, containing functions like cos and sine All of the libraries are automatically linked in by both of the compilers. If the standard libraries are overridden, the search path for these libraries must be given to the compiler. The libil.a is modified by the Library Generator tool (Libgen) to add driver and library routines. Compiler Interface Input Files The compilers, mb-gcc and powerpc-eabi-gcc, take one or more of the following files as input: C source files C++ source files Assembly Files Object Files Linker scripts Note: These are optional. If they are not specified, the default linker script embedded in the linker (mb-ld or powerpc-eabi-ld) is used. The default etensions for each of these types is detailed in Table In addition to the files mentioned above, the compiler implicitly refers to the libraries files libc.a, libm.a and libil.a. The default location for these files is the EDK installation directory Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

165 MicroBlaze GNU Compiler R Output Files MicroBlaze GNU Compiler Quick Reference The compiler generates the following files as output: An ELF file; the default output file name is a.out on Solaris and a.ee on Windows Assembly file, if -save-temps or -S option are used Object file, if -save-temps or -c option are used Preprocessor output,.i or.ii file, if -save-temps option is used The MicroBlaze GNU compiler is an enhancement over the standard GNU tools and hence provides some additional options, which are specific to the MicroBlaze system.these options are available only in the MicroBlaze GNU compiler. Table 13-6: MicroBlaze-Specific Options Options -l-mode-eecutable -l-mode-mdstub -l-mode-ilkernel -ml-gp-opt -ml-soft-mul -mno-l-soft-mul -ml-soft-div -mno-l-soft-div -ml-stack-check -ml-barrel-shift -ml-pattern-compare Eplanation Default mode for compilation. Software intrusive debugging on the board. Should be used only with XMDStub downloaded on to MicroBlaze Use this option to compile ELF processes that eecute on Xilkernel. Refer to the Xilkernel reference guide for more information on Xilkernel ELF processes. You do not need this option for non-ilkernel based eecutables. Use the small data area anchors. Optimization for performance and size. Use the software routine for all multiply operations. This option should be used for devices without the hardware multiplier. This is the default option in mb-gcc Do not use software multiplier. Compiler generates mul instructions. Use the software routine for all divide operations. This is the default option. Use the hardware divide available in the MicroBlaze Generates code for checking stack overflow. Use barrel shifter. Use this option when a barrel shifter is present in the device Use pattern compare instructions while generating code. This option should be used when the pattern compare option is turned on in MicroBlaze. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

166 Chapter 13: GNU Compiler Tools Table 13-6: MicroBlaze-Specific Options (Continued) Options Eplanation -mhard-float -msmall-divides Generate hardware floating point instructions. This option should be used when MicroBlaze has the hardware floating point unit (FPU) turned on. Generate code optimized for small divides, when there is no hardware divider. For signed integer divisions where, the numerator and denominator is between 0 and 15 inclusive, this switch can provide very fast tablelookup based divisions. This switch has no effect, when the hardware divider is enabled. Note: This switch will entail a code size increase of 256 bytes if divisions are present in the code. MicroBlaze Compiler The mb-gcc compiler for Xilin s MicroBlaze soft processor introduces some new options as well as modifications to certain options supported by the gnu compiler tools. The new and modified options are summarized in this chapter. -ml-soft-mul In some devices, a hardware multiplier is not present. In such cases, the user has the option to either build the multiplier in hardware or use the software multiplier library routine provided. MicroBlaze compiler mb-gcc assumes that the target device does not have a hardware multiplier and hence every multiply operation is replaced by a call to mulsi3 defined in library libc.a. Appropriate arguments are set before calling this routine. -mno-l-soft-mul Certain devices such as Virte -II have a hardware multiplier integrated on the device. Hence the compiler can safely generate the mul or muli instruction. Using a hardware multiplier gives better performance, but can be done only on devices with hardware multiplier such as Virte-II. -ml-soft-div The MicroBlaze processor does not come with a hardware divide unit. The users would need the software routine in the libraries for the divide operation. This option is turned on by default in mb-gcc. -mno-l-soft-div In MicroBlaze version 2.00 and beyond, the user can instantiate a hardware divide unit in MicroBlaze. If such a unit is present, this option should be provided to mb-gcc compiler. Refer to the MicroBlaze Processor Reference Guide for more details about the usage of hardware divide option in the MicroBlaze Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

167 MicroBlaze GNU Compiler R -ml-stack-check This option lets users check if the stack overflows during the eecution of the program. The compiler inserts code in the prologue of the every function, comparing the stack pointer value with the available memory. If the stack pointer eceeds the available free memory, the program jumps to a the subroutine _stack_overflow_eit. This subroutine sets the value of the variable _stack_overflow_error to 1. The standard stack overflow handler can be overridden by providing the function _stack_overflow_eit in the source code, which acts as the stack overflow handler. -ml-barrel-shift The MicroBlaze processor can be configured to be built with a barrel shifter. In order to use the barrel shift feature of the processor, use the option -ml-barrel-shift. The default option is to assume that no barrel shifter is present and hence the compiler will use add and multiply operations to shift the operands. Barrel shift can increase the speed significantly, especially while doing floating point operations.refer to the MicroBlaze Processor Reference Guide for more details about the usage of the barrel shifter option in the MicroBlaze. -ml-gp-opt If the memory location requires more than 32K, the load/store operation requires two instructions. MicroBlaze ABI offers two global small data areas, which can contain up to 64K bytes of data each. Any memory location within these areas can be accessed using the small data area anchors and a 16-bit immediate value. Hence needing only one instruction for load/store to the small data area.this optimization can be turned ON with the -ml-gpopt command line parameter. Variables of size lesser than a certain threshold value are stored in these areas. The value of the pointers is determined during linking. -l-mode-eecutable This is the default mode used for compiling programs with mb-gcc. The final eecutable created starts from address location 00 and links in crt0.o. This option need not be provided on the command line for mb-gcc. -l-mode-mdstub Xilin Microprocessor Debugger (XMD) allows three different modes of debugging an user program for MicroBlaze. The three debugging options are Simulator mode (Does not require a board) XMDStub mode (Requires the XMDStub to be a part of the bitstream) MDM mode (Hardware debugging enabled. Bitstream does not contain the XMDStub) For more information about the XMD tool, refer to the Xilin Microprocessor Debugger (XMD) chapter in the guide. For programs compiled with the XMDStub mode, the address locations 00 to 03ff are reserved for the XMDStub. Hence the user program can start only at Embedded System Tools Reference Manual UG111 (v4.0) February 15,

168 Chapter 13: GNU Compiler Tools The usage of -l-mode-mdstub has two effects: The start address of the user program is set to Users can change this address by overriding the _TEXT_START_ADDR in the linker script or through linker options. For more details about linker options, refer to the Linker Options section. If the start address is defined to be less than 0800, XMD issues an address overlap error. crt1.o is used as the initialization file. The crt1.o file returns the control back to the XMDStub when the user program eecution is complete. Note: -l-mode-mdstub should be used for designs when XMDStub is part of the bitstream. This mode should not be used when the system is complied for No Debug or when Hardware Debugging is turned ON. For more details on debugging with md, refer to Chapter 15, Xilin Microprocessor Debugger (XMD). -l-mode-ilkernel The Embedded Development Kit provides a microkernel (XMK). Any application which needs to be eecuted on top of this kernel should be compiled with the -l-mode-ilkernel. Refer to the EST Libraries Guide for more information regarding the various option provided by the Xilin MicroKernel. Caution! mb-gcc will signal fatal error if more than one mode of eecution is supplied on the command line. -ml-pattern-compare This option turns on the usage of pattern compare instructions in the compiler. Pattern compare instructions can produce nominal speedups in your program. However, the main benefit of pattern compare instructions, comes from string manipulation routines, that can now operate on full words, instead of bytes at a time. In this case, the speedup produced can be significant. -mhard-float This options turns on the usage of fadd, frsub, fmul, fdiv instructions in the compiler. It also uses fcmp.p instructions, where p is a predicate condition such as le, ge, lt, gt, eq, ne. MicroBlaze Assembler The mb-as assembler for Xilin s MicroBlaze soft processor supports the same set of options supported by the standard GNU compiler tools. It also supports the same set of assembler directives supported by the standard gnu assembler. The mb-as assembler supports all the opcodes in the MicroBlaze machine instruction set, with the eception of the imm instruction. The mb-as assembler generates imm instructions when large immediate values are used. The assembly language programmer is never required to write code with imm instructions. For more information on the MicroBlaze instruction set, refer to the MicroBlaze Processor Reference Guide. The mb-as assembler requires all Type B MicroBlaze instructions ( instructions with an immediate operand) to be specified as a constant or a label. If the instruction requires a PCrelative operand, then the mb-as assembler will compute it, and will include an imm instruction if necessary. For eample, the Branch Immediate if Equal (beqi) instruction requires a PC-relative operand Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

169 MicroBlaze GNU Compiler R The assembly programmer should use this instruction as follows: beqi r3, mytargetlabel where mytargetlabel is the label of the target instruction. The mb-as assembler computes the immediate value of the instruction as mytargetlabel - PC. If this immediate value is greater than 16 bits, the mb-assembler automatically inserts an imm instruction. If the value of mytargetlabel is not known at the time of compilation, the mb-as assembler always inserts an imm instruction. The rela option of the linker should be used to remove any imm instructions that are found to be unnecessary. Similarly, if an instruction needs a large constant as an operand, the assembly language programmer should use the operand as-is, without using an imm instruction. For eample, the following code is used to add the constant 200,000 to the contents of register r3, and store the result in register r4: addi r4, r3, The mb-as assembler will recognize that this operand needs an imm instruction, and insert one automatically. In addition to the standard MicroBlaze instruction set, the mb-as assembler also supports some pseudo-opcodes to ease the task of assembly programming. The supported pseudoops are listed in Table Table 13-7: Pseudo-Opcodes Supported by the Gnu Assembler Pseudo Opcodes Eplanation nop la Rd, Ra, Imm No operation. Replaced by instruction: or R0, R0, R0 Replaced by instruction: addik Rd, Ra, imm; = Rd = Ra + Imm; not Rd, Ra Replace by instruction: ori Rd, Ra, -1 neg Rd, Ra sub Rd, Ra, Rb Replace by instruction: rsub Rd, Ra, R0 Replace by instruction: rsub Rd, Rb, Ra MicroBlaze Linker The mb-ld linker for Xilin s MicroBlaze soft processor introduces some new options in addition to those supported by the gnu compiler tools. The new options are summarized in this section. -defsym _TEXT_START_ADDR=value By default, the tet section of the output code starts with the base address 00. This can be overridden by using the above options. If this is supplied to mb-gcc, the tet section of the output code will now start from the given value. When the compiler is invoked with -lmode-mdstub, the user program starts at 0800 by default. You do not have to use -defsym _TEXT_START_ADDR, if you want to use the default start address set by the compiler. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

170 Chapter 13: GNU Compiler Tools -rela -N Initialization Files This is a linker option and should be used when the user is invoking the linker separately. If the linker is being invoked as a part of the mb-gcc flow, the user has to use the following option -Wl,-defsym -Wl,_TEXT_START_ADDR=value This is a linker option, used to remove all the unwanted imm instructions generated by the assembler. The assembler generates imm instruction for every instruction where the value of the immediate can not be calculated during the assembler phase. Most of these instructions won t need an imm instruction. These are removed by the linker when the - rela command line option is provided to the linker. This option is required only when linker is invoked on its own. When linker is invoked through the mb-gcc compiler, this option is automatically provided to the linker. This option sets the tet and data section to be readable and writable. It also does not pagealign the data segment. This option is required only for MicroBlaze programs. The top level gcc compiler automatically includes this option, while invoking the linker, but if you intend to invoke the linker without using gcc, you should have use this option. For more details on this option, refer to the GNU manuals online at this location: The final eecutable needs certain registers such as the small data area anchors (R2 and R13) and the stack pointer (R1) to be initialized. shows how specific registers get modified. These C-Runtime files also set up the interrupt and eception handler routines. Table 13-8: Register initialization in the C-Runtime files Register Value Description r1 _stack-16 Stack pointer register is initialization the bottom of the allocated stack, offset by 16 bytes. The 16 bytes can be used for passing in arguments. r2 _SDA2_BASE _SDA2_BASE_ is the read-only small data anchor address. r13 _SDA_BASE SDA_BASE is the read-write small data anchor address. Other registers Undefined Other registers do not have defined values. These initialization files are distributed with the Embedded Development Kit. In addition to the precompiled object files, source files are also distributed in order to help user make their own changes as per their requirements. Initialization can be done using one of the three C runtime routines: Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

171 MicroBlaze GNU Compiler R crt0.o crt1.o crt4.o This initialization file is to be used for programs which are to be eecuted standalone, i.e without the use of any bootloader or debugging stub (such as mdstub). This file is located in the same directory and should be used when software intrusive debugging (XMDstub) is used. crt1.o returns the control of the program back to the XMDStub on completion of user program. Xilkernel supports creating processes out of separate ELF files. For these separate ELF files, a special CRT is required to ensure that the run-time initialization performed by the kernel is not overwritten. Therefore, when compiling such ELF files, crt4.o is used as the startup file by the compiler. crt4.o does not set up the interrupt and eception handlers since the default handling of the interrupts and eceptions are done by the kernel. This crt also return the control back to the kernel on completion of the user program. The source for initialization files is available in the <XILINX_EDK>/sw/lib/microblaze/src directory, i <XILINX_EDK> : Installation area These files can be changed as per the requirements of the project. These changed files have to be then assembled to generate an object file (.o format). To refer to the newly created object files instead of the standard files, use the -B directory-name command line option while invoking mb-gcc. According to the C standard specification, all global and static variables need to be initialized to 0. This is a common functionality required by all the crt s above. Hence another routine _crtinit is defined in crtinit.o file. This file is part of the libc.a library. The _crtinit routine will initialize memory in the bss section of the program, defined by the default linker script. If you intend to provide your own linker script, you will need to compile a new _crtinit routine. The default crtinit.s file is provided in assembly source format as a part of the Embedded Development Kit. Compiler Libraries The mb-gcc compiler requires the GNU C standard library and the GNU math library. Precompiled versions of these libraries are shipped with EDK. The CPU driver for MicroBlaze copies over the correct version, based on the hardware configuration of MicroBlaze, during the eecution of Libgen. If you want to manually pick the version of the library that you would like to use, then you can find these libraries in the following folder: <edk_install>/gnu/microblaze/<platform>/microblaze/lib The filenames are encoded based on the compiler flags and configurations used to compile the library. For eample, libc_m_bs.a is the C library compiled with hardware multiplier and barrel shifter enabled in the compiler. Embedded System Tools Reference Manual UG111 (v4.0) February 15,

172 Chapter 13: GNU Compiler Tools Of special interest are the math library files (libm*.a). Using MicroBlaze with a singleprecision hardware Floating-Point Unit (FPU), you might want to use the version of the library that is tailored to best use the hardware unit, instead of the default floating point emulation. The CPU driver by default picks up the double precision (libm_*_fpd.a) version of the library. However, you might want to use the single-precision version of the library since it might be sufficient and more efficient for your application. In this case, copy over the corresponding, libm_*_fps.a file into your processor s library folder (such as microblaze_0/lib) as libm.a. Once you have copied over the library that you want to use, rebuild your application s software project and the library that you copied over is used to build the final eecutable. Command Line Arguments Interrupt Handlers MicroBlaze programs can not take in command line arguments. The command line arguments argc and argv are initialized to 0 by the C runtime routines. Interrupt handlers need to be compiled in a different manner as compared to the normal sub-routine calls. In addition to saving non-volatiles, interrupt handlers have to save the volatile registers which are being used. Interrupt handler should also store the value of the machine status register (RMSR), when an interrupt occurs. _interrupt_handler attribute In order to distinguish an interrupt handler from a sub-routine, mb-gcc looks for an attribute (interrupt_handler) in the declaration of the code. This attribute is defined as follows: void function_name () attribute ((interrupt_handler)); Note: Attribute for interrupt handler is to be given only in the prototype and not the definition. Interrupt handlers might also call other functions, which might use volatile registers. In order to maintain the correct values in the volatile registers, the interrupt handler saves all the volatiles, if the handler is a non-leaf function (1). Interrupt handlers can also be defined in the MicroBlaze Hardware Specification (MHS) and the MicroBlaze Software Specification (MSS) file. These definitions would automatically add the attributes to the interrupt handler functions. For more information refer to MicroBlaze Interrupt Management document. The interrupt handler uses the instruction rtid for returning to the interrupted function. _save_volatiles attribute The MicroBlaze compiler provides the attribute save_volatiles, which is similar to the _interrupt_handler attribute, but returns using rtsd instead of rtid. This attributes save all the volatiles for non-leaf functions and only the used volatiles in case of leaf functions. void function_name () attribute ((save_volatiles)); 1. Functions which have calls to other sub-routines are called non-leaf functions Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

173 PowerPC GNU Compiler R The attributes with their functions are tabulated in Table Table 13-9: Use of Attributes Attributes interrupt_handler save_volatiles Functions This attribute saves the machine status register and all the volatiles in addition to the non-volatile registers. rtid is used for returning from the interrupt handler. If the interrupt handler function is a leaf function, only those volatiles which are used by the function are saved. This attribute is similar to interrupt_handler, but it used rtsd to return to the interrupted function, instead of rtid. PowerPC GNU Compiler Compiler Options The PowerPC GNU compiler (powerpc-eabi-gcc) is built completely out of the open source effort, with very few modifications. No enhancements have been done to the compiler. The PowerPC compiler does not support any special options. All the listed common options are supported by the powerpc-eabi compiler. The PPC405 specific options that are supported by the compiler are, -mhard-float This option tells the compiler to produce code that uses the floating point registers and the floating point instructions native to the PPC405. If the PPC405 that you are targeting supports the native floating point instructions, then this option is required to leverage it. This is turned off by default. -msoft-float Linker Options This option is enabled by default and tells the compiler to produce floating point that uses the software floating point libraries. -defsym _START_ADDR=value By default, the tet section of the output code starts with the base address 0ffff0000, since this is the start address indicated in the default linker script. This can be overridden by using the above option OR providing a linker script, which lists the value for start address The user does not have to use -defsym _START_ADDR, if they wish to use the default start address set by the compiler. This is a linker option and should be used when the user is invoking the linker separately. If the linker is being invoked as a part of the powerpc-eabi-gcc flow, the user has to use the following option -Wl,-defsym -Wl,_START_ADDR=value Embedded System Tools Reference Manual UG111 (v4.0) February 15,

174 Chapter 13: GNU Compiler Tools Initialization Files The compiler looks for certain initialization files (such as boot.o, crt0.o). These files are compiled along with the drivers and archived in libil.a library. This library is generated using Libgen by compiling the distributed sources in the Board Support Package (BSP). For more information on the PowerPC initialization files, refer to the Standalone BSP chapter in the OS and Libraries Reference Manual. For more information about Libgen, refer to Chapter 7, Library Generator Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

175 Chapter 14 GNU Debugger Overview This chapter describes the general usage of the Xilin GNU debugger (GDB) for MicroBlaze and PowerPC. This chapter contains the following sections: Overview MicroBlaze GDB Targets PowerPC Targets Console Mode GDB Command Reference GDB is a powerful yet fleible tool that provides a unified interface for debugging and verifying MicroBlaze and PowerPC systems during various development phases. It uses Xilin Microprocessor Debugger (XMD) as the underlying engine to communicate to Processor targets. Tool Usage Tool Options MicroBlaze GDB usage: mb-gdb options eecutable-file PowerPC GDB usage: powerpc-eabi-gdb options eecutable-file The following options are the most common in the GNU debugger: --command=file Eecute GDB commands from FILE. Used for debugging in batch/script mode. --batch Eit after processing options. Used for debugging in batch/script mode. --nw Do not use a GUI interface. -w Use a GUI interface (Default). Embedded System Tools Reference Manual UG111 (v4.0) February 15,

176 Chapter 14: GNU Debugger Debug Flow using GDB MicroBlaze GDB Targets Simulator Target Hardware Target 1. Start XMD from XPS. 2. Connect to the Processor target, located in Simulator/Hardware/Virtual Platform. This action opens a GDB Server for the target. 3. Start GDB from XPS. 4. Connect to Remote GDB Server on XMD. 5. Download the Program and Debug application. Currently, there are three possible remote targets that are supported by the MicroBlaze GNU Debugger and XMD tools. Remote debugging is done through XMD. The XMD server program can be started on a host computer with the Simulator target, Hardware target, or Virtual Platform target transparent to mb-gdb. The Cycle-Accurate Instruction Set Simulator and the Hardware interface provide powerful debugging tools for verifying a complete MicroBlaze system. The debugger mb-gdb connects to md using the GDB Remote Protocol over TCP/IP socket connection. The XMD simulator is a Cycle-Accurate Instruction Set Simulator of the MicroBlaze system which presents the simulated MicroBlaze system state to GDB. With the hardware target, XMD communicates with opb_mdm debug core or an mdstub program running on a hardware board through the serial cable or JTAG cable, and presents the running MicroBlaze system state to GDB. For more information about XMD, refer to Chapter 15, Xilin Microprocessor Debugger (XMD). Virtual Platform Target Virtual Platform is a Cycle-Accurate MicroBlaze fied Reference design. It supports LMB and Eternal Memory, UARTlite, and GPIO interface. Refer to the Chapter 8, Virtual Platform Generator for more information on generating Virtual Platform. Refer to the Virtual Platform MicroBlaze Target section of Chapter 15, Xilin Microprocessor Debugger (XMD) for more information on Virtual Platform debugging. Compiling for Debugging on MicroBlaze Targets In order to debug a program, you must generate debugging information when you compile it. This debugging information is stored in the object file; it describes the data type of each variable or function and the correspondence between source line numbers and addresses in the eecutable code. The mb-gcc compiler for Xilin s MicroBlaze soft processor includes this information when the appropriate modifier is specified Embedded System Tools Reference Manual UG111 (v4.0) February 15, 2005

177 PowerPC Targets R The -g option in mb-gcc allows you to perform debugging at the source level. The debugger mb-gcc adds appropriate information to the eecutable file, which helps in debugging the code. The debugger mb-gdb provides debugging at source, assembly, and mied source and assembly. Note: While initially verifying the functional correctness of a C program, do not use any mb-gcc optimization option like -O2 or -O3 as mb-gcc does aggressive code motion optimizations which might make debugging difficult to follow. Note: For debugging with md in hardware mode using XMDStub, you must specify the mb-gcc option -l-mode-mdstub. Refer to Chapter 15, Xilin Microprocessor Debugger (XMD) for more information about compiling for specific targets. PowerPC Targets Debugging for the PowerPC405 is supported by powerpc-eabi-gdb and md through the GDB Remote TCP protocol. XMD supports two remote targets: PowerPC Hardware on Virte -II Pro and Virte -4, and Cycle-Accurate PowerPC Instruction Set Simulator. To connect to a PowerPC target: 1. Start md and connect to the board using the connect ppc command as described in Chapter 15, Xilin Microprocessor Debugger (XMD). 2. Select Run o Connect to target from GDB. 3. In the GDB target selection dialog bo, specify the following: i Target: Remote/TCP i Hostname: localhost i Port: Click OK. The compiler powerpc-eabi-gdb attempts to make a connection to XMD. If successful, a message is printed in the shell window where XMD started. Figure 14-1: Target Selection Dialog Bo At this point, the compiler is connected to XMD and controls the debugging. The GUI can be used to debug the program and read and write memory and registers. Embedded System Tools Reference Manual UG111 (v4.0) February 15,