Virtex-4 PowerPC Example Design. UG434 (v1.2) January 17, 2008

Transcription

1 Virtex-4 PowerPC Example Design R

2 R Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Revision History The following table shows the revision history for this document. Date Version Revision 1/19/ Initial Xilinx release 8/27/ Updated for EDK 9.2i 1/17/ Updated for EDK 10.1i Virtex-4 PowerPC Example Design

3 Table of Contents Overview Hardware Requirements: Software Requirements: Design Description Design Contents Project File Description Running the Example Design Implementing the Example Design Creating the Example Design Creating the Hardware Platform Using Base System Builder Implementing the Embedded System Further Reading Virtex-4 PowerPC Example Design

4 Virtex-4 PowerPC Example Design

5 R Virtex-4 PowerPC Example Design Overview Target board: Xilinx Virtex -4 ML403 Evaluation Platform Development system: Embedded Development Kit (EDK) This Example design is provided with the EDK development system. The design is completely implemented and ready to download and run on a ML403 Evaluation Platform. Hardware Requirements: Xilinx Virtex-4 ML403 Evaluation Platform, Revision 1 (or later). Serial cable: 9-pin female to 9-pin female null modem. Platform USB Cable or Xilinx Parallel Cable 4 (with flat ribbon cable). Software Requirements: Design Description Xilinx Embedded Development Kit (EDK). This project should be run on the same version of EDK in which it was installed, or later. Xilinx ISE (refer to Getting Started With EDK for the required version of ISE). HyperTerminal (or similar) for host communication with the Xilinx Virtex-4 ML403 Evaluation Platform. This Example Design is originally created using the Base System Builder (BSB) in the EDK development system. BSB generates the customized embedded system hardware platform based on user selections from features available on the target board (ML403 Evaluation Platform). BSB also generates two sample application programs (TestApp_Memory.c and TestApp_Peripheral.c) which exercises some of the selected hardware features. The TestApp_Memory.c application tests the Memory core in the system by doing 32, 16, and 8 bit reads and writes to internal and external memory. However, in this example system, since both the memories (XPS BRAM and DDR SDRAM) hold a part of the application program, no memory test routine will be run for any of the memories. The TestApp_Peripheral.c application does some basic tests on peripherals like UARTLite, Interrupt controller, Timer, and the GPIO LEDs that are available in the system. Virtex-4 PowerPC Example Design 3

6 Design Contents R Design Contents The embedded processor system contained in this Example Design consists of the following: PowerPC bit hard processor core on a 200 MHz system clock 32 KB of BRAM (XPS BRAM) connected to the processor PLB bus Multi-Ported Memory Controller (MPMC) on the processor PLB Bus connected to 64MB of DDR2 memory UART peripheral (XPS UARTLite) on the processor PLB bus connected to the RS232 serial channel on the ML403 Evaluation Platform used for STDIN and STDOUT General Purpose I/O peripheral (XPS GPIO) on the processor PLB bus connected to four LEDs on the ML403 Evaluation Platform Timer/counter peripheral (XPS Timer) on the processor PLB bus, used to generate interrupts at varying intervals Interrupt controller (XPS INTC) on the processor PLB bus, used to manage multiple interrupts The embedded processor system is implemented in a XC4VFX12-FF Virtex-4 FPGA device on the ML403 Evaluation Platform. Project File Description system.xmp: XPS project file (target device, project options, source file pointers) system.mhs: Microprocessor Hardware Specification (processor, busses, peripherals, ports, peripheral configuration parameters) system.mss: Microprocessor Software Specification (libraries, drivers, system software options) data/system.ucf: Implementation constraint file (pinouts and clock frequency) TestApp_Memory/src/TestApp_Memory.c: Application program TestApp_Peripheral/src/TestApp_peripheral.c: Application program Running the Example Design This section provides the steps for running the Example Design using the pre-built bitstream and the compiled software applications. 1. Connect the Platform USB Cable or Parallel Cable 4 between the host computer and the FPGA & CPU Debug port of the ML403 Evaluation Platform. Supply power to the Parallel Cable 4 using either the PS2 port of the host computer or external power supply. 2. Connect the serial cable between the host computer and the RS232 ( UART Host ) port of the ML403 Evaluation Platform. 3. Apply power to the ML403 Evaluation Platform. 4. Start a HyperTerminal (or similar) session on the host computer with the following settings as shown in Figure 1. Select the COM port corresponding to connected serial port on the host computer. Set the Baud Rate = 9600, Data = 8 bits, Parity = None, Stop = 1 bit, Flow control = None. 4 Virtex-4 PowerPC Example Design

7 R Running the Example Design UG434_01_ Figure 1: HyperTerminal Settings 5. Change directories to the ready_for_download directory where the Virtex4_PPC_Example project was expanded. 6. Use impact to download the bitstream by using the following command: impact -batch virtex4_ppc_example.cmd 7. Invoke XMD and connect to the PowerPC processor by using the following command: xmd -opt virtex4_ppc_example.opt 8. Download the Application to be tested by using one of the following commands: dow testapp_memory_executable.elf dow testapp_peripheral_executable.elf 9. To run the software applications,use the run command inside XMD. The status of the software application is displayed in the HyperTerminal data screen. The output of the TestApp Memory application will look like the following -- Entering main() Exiting main()-- Note: Since both XPS BRAM and DDR SDRAM hold a part of the application program, no actual memory test is run for any of the memories. The output of the TestApp Peripheral application will look like the following -- Entering main() -- Runnning IntcSelfTestExample() for xps_intc_0... Virtex-4 PowerPC Example Design 5

8 Implementing the Example Design R IntcSelfTestExample PASSED Intc Interrupt Setup PASSED Running GpioOutputExample() for LEDs_8Bit... GpioOutputExample PASSED. Running TmrCtrSelfTestExample() for xps_timer_1... TmrCtrSelfTestExample PASSED Running Interrupt Test for xps_timer_1... Timer Interrupt Test PASSED -- Exiting main() -- Implementing the Example Design This section provides the steps for implementing the Example Design using Xilinx Platform Studio (XPS). 1. Perform steps 1-4 in the Running the Example Design section. 2. Invoke Xilinx Platform Studio (XPS). (It is not necessary to invoke ISE Project Navigator software to run this example design.) 3. Open the Example design by selecting the system.xmp file in the directory where you expanded the Virtex4_PPC_Example design. 4. In XPS, select Device Configuration Update Bitstream. The design will be implemented and the FPGA bitstream is created. 5. In XPS, select Software Launch Platform Studio SDK to launch SDK. Import TestApp_Memory and TestApp_Peripheral into SDK by following the steps outlined in Creating the Software Executables using Platform Studio SDK 6. In SDK, Build all applications by selecting Project Build Automatically. This will automatically build all the applications. 7. In SDK, in Device Configuration Bitstream Settings..., select the bootloop executable ppc405_0.elf for initializing the BRAM. 8. In SDK, select Device Configuration Program FPGA. The design will be downloaded into the FPGA. 9. In SDK, Launch XMD with Xilinx Tools View XMD Console. In XMD console, type the following command: connect ppc hw 10. Download the Application to be tested by using one of the following commands: dow SDK_projects/TestApp_Memory/Debug/TestApp_Memory.elf dow SDK_projects/TestApp_Peripheral/Debug/TestApp_Peripheral.elf 6 Virtex-4 PowerPC Example Design

9 R Creating the Example Design 11. To run the software applications,use the run command inside XMD. The status of the software application is displayed in the HyperTerminal data screen. The output of the TestApp Memory application will look like the following -- Entering main() Exiting main()-- Note: Since both XPS BRAM and DDR SDRAM hold a part of the application program, no actual memory test is run for any of the memories. The output of the TestApp Peripheral application will look like the following -- Entering main() -- Runnning IntcSelfTestExample() for xps_intc_0... IntcSelfTestExample PASSED Intc Interrupt Setup PASSED Running GpioOutputExample() for LEDs_8Bit... GpioOutputExample PASSED. Running TmrCtrSelfTestExample() for xps_timer_1... TmrCtrSelfTestExample PASSED Running Interrupt Test for xps_timer_1... Timer Interrupt Test PASSED -- Exiting main() -- Creating the Example Design This Example design was prepared using the following procedure: Creating the Hardware Platform Using Base System Builder 1. Invoke XPS. 2. Create a new project and select to use the Base System Builder Wizard (default). 3. In the Create New XPS Project Using BSB Wizard window, browse to a directory in which to write the project file (system.xmp by default). 4. In the Base System Builder - Welcome dialog, choose I would like to create a new design (default). Virtex-4 PowerPC Example Design 7

10 Creating the Example Design R 5. In the Base System Builder - Select Board window, make the selections shown in Figure 2: a. Choose I would like to create a system for the following development board (default). b. In the Board Vendor field, select Xilinx. c. For the Board Name field, select Virtex-4 ML403 Evaluation Platform. If necessary, select the revision of the board you are using. UG434_02_ Figure 2: Base System Builder - Selection of Board 8 Virtex-4 PowerPC Example Design

11 R Creating the Example Design 6. In the Base System Builder - Select Processor window, verify that the PowerPC Processor is selected(default). 7. In the Base System Builder - Configure PowerPC Processor window make the selections as shown in Figure 3: a. Under System Wide Settings, select 100 MHz as the Reference clock frequency (default), 200 MHz as the Processor clock frequency (default), and 100 MHz as the Bus clock frequency (default). b. Under Processor Configuration, for Debug Interface, accept FPGA JTAG as the debug interface (default). c. Under On-Chip Memory, select NONE for Data and Instruction. d. For Cache setup, check Enable. e. Confirm that Enable Floating point unit (FPU) is unchecked. Figure 3: PowerPC Configuration UG434_03_ Virtex-4 PowerPC Example Design 9

12 Creating the Example Design R 8. In the Base System Builder - Configure I/O Interfaces (1 of 4) window, make the selections as shown in Figure 4: a. Check RS232_Uart (default)then select XPS UARTLITE in the Peripheral field. Set the Baud Rate to 9600 (default), the Data bits to 8 (default), the Parity to None (default). Check Use Interrupt. b. Check LEDs_4Bit (default). In the Peripheral field, select XPS_GPIO (default), and uncheck Use Interrupt (default). c. Uncheck LEDs_Positions. Note: The Base System Builder - Configure I/O Interfaces windows may slightly differ from the screenshots shown below based on the screen resolution used. Figure 4: IO interface Configuration 10 Virtex-4 PowerPC Example Design

13 R Creating the Example Design 9. In the Base System Builder - Configure I/O Interfaces (2 of 4) window, make the selections as shown in Figure 5. a. Uncheck Push_Buttons_Position. b. Uncheck the peripherals IIC_EEPROM, SysACE_CompactFlash, and Cypress_USB. Figure 5: Removing IO Peripherals Virtex-4 PowerPC Example Design 11

14 Creating the Example Design R 10. In the Base System Builder - Configure I/O Interfaces (3 of 4) window, make the selections as shown in Figure 6. a. Check DDR_SDRAM (default). In the Peripheral field, select MPMC (default). b. Uncheck Ethernet_MAC and TriMode_MAC_GMII. Figure 6: Adding MPMC Peripheral 12 Virtex-4 PowerPC Example Design

15 R Creating the Example Design 11. In the Base System Builder - Configure I/O Interfaces (4 of 4) window, make the selections as shown in Figure 7. a. Uncheck the peripherals SRAM, and FLASH. Figure 7: Excluding SRAM, and FLASH Virtex-4 PowerPC Example Design 13

16 Creating the Example Design R 12. In the Base System Builder - Add Internal Peripherals (1 of 1) window, make the selections as shown in Figure 8: a. For XPS BRAM IF CNTLR, select Memory Size of 32 KB. b. Click Add Peripheral. Select XPS Timer as the peripheral to be added to the system. For Counter Bit Width, select 32 (default). Select One timer is present for Timer Mode and check Use Interrupt. UG434_06_ Figure 8: Add Internal Peripheral Settings 14 Virtex-4 PowerPC Example Design

17 R Creating the Example Design 13. In the Base System Builder - Cache Setup window, make the selections shown in Figure 9. a. For Instruction Cache ( ICache) Size, note the setting of 16 KB (default). b. For Data Cache ( DCache) Size, note the setting of 16 KB (default). c. Select both ICache and DCache for performing Cache transations using the DDR_SDRAM as Cacheable memory. Figure 9: Cache Setup Virtex-4 PowerPC Example Design 15

18 Creating the Example Design R 14. In the Base System Builder - Software Setup window, make the selections as shown in Figure 10. a. In the STDIN and STDOUT fields, select RS232_Uart (default). b. In the Boot Memory field, select xps_bram_if_cntrl_1 (default). c. Under Sample Application Selection, check Memory Test (default) and check Peripheral selftest (default). Figure 10: Software Setup settings UG434_09_ Virtex-4 PowerPC Example Design

19 R Creating the Example Design 15. In the Base System Builder - Configure Memory Test Application window, make the selections as shown in Figure 11: a. In the Instruction, Data and Stack/Heap fields, select xps_bram_if_cntlr_1 (default). b. In the Interrupt Vec field, select DDR_SDRAM (default). UG434_10_ Figure 11: Memory Test Software Application Configuration Virtex-4 PowerPC Example Design 17

20 Creating the Example Design R 16. In the Base System Builder - Configure Peripheral Test Application window, make the selections as shown in Figure 12. a. In the Instruction, Data, Stack/Heap, and Interrupt Vec fields, select DDR_SDRAM (default). UG434_11_ Figure 12: Peripheral Test Software Application Configuration 17. In the Base System Builder - System Created window, where the selections which have been made are summarized, click Generate to generate the system. 18. In the Base System Builder - Finish window, check Save Settings File (default) and click Finish. 19. In the Next Steps window, select Start Using Platform Studio. Generating the Hardware Bitstream 1. In XPS, select Device Configuration Update Bitstream to generate the hardware bitstream for the embedded system Virtex-4 PowerPC Example Design

21 R Creating the Example Design Creating the Software Executables using Platform Studio SDK 1. In XPS, select Software Launch Platform Studio SDK to launch the SDK application to create the software executables. 2. In the Platform Studio SDK Application Wizard, select Import XPS Application Projects as shown in Figure 13. Figure 13: Selecting Import XPS Application Projects Wizard 3. In the following Import XPS Application Projects to SDK window, select the application projects that need to be inported by the SDK as shown in Figure 14. Figure 14: Selecting XPS Applications to be Imported Virtex-4 PowerPC Example Design 19

22 Creating the Example Design R 4. In SDK, if the Project Build Automatically option is set, then the SDK automatically builds the software applications & marks it to BRAM as specified.if this option is not selected,then select Project Build All option to build all the applications. 5. In SDK, select Device Configuration Bitstream Settings... to initialize the BRAM with the required Software executable. a. In the Bitstream Settings window, select the bootloop executable ppc405_0.elf from the drop down menu as shown in Figure 15. b. Click on Save to save the Bitstream settings. Figure 15: Bitstream settings to specify the ELF file to be initialized into BRAM 6. In SDK, select Device Configuration Program FPGA. The design will be downloaded using the Platform USB Cable into the JTAG port of the FPGA on the Virtex-4 ML403 Evaluation Platform, Rev In SDK, Launch XMD with Xilinx Tools View XMD Console. In XMD console, type the following command: connect ppc hw 8. Download the Application to be tested by using one of the following commands: dow SDK_projects/TestApp_Memory/Debug/TestApp_Memory.elf dow SDK_projects/TestApp_Peripheral/Debug/TestApp_Peripheral.elf 9. To run the software applications, use the run command inside XMD. The HyperTerminal results will appear as described in step 11 in the section Running the Example Design Virtex-4 PowerPC Example Design

23 R Further Reading Further Reading A complete description of design techniques and function calls required to implement interrupts in a PowerPC design can be found in the Interrupt Management chapter of the Embedded System Tools Reference Manual. Details on the driver calls used to control the XPS_UARTlite, XPS_Timer, XPS_GPIO and XPS_Intc peripherals can be found in the Driver Reference Guide. Complete instructions for developing embedded processor designs using Xilinx Platform Studio can be found in the XPS on-line help (select Help Help Topics). Complete instructions for developing embedded processor software applications using Xilinx Platfrom Studio SDK can be found in Xilinx Platform Studio SDK User Guide in the XPS SDK on-line help (select Help Welcome). Virtex-4 PowerPC Example Design 21

24 Further Reading R 22 Virtex-4 PowerPC Example Design