ML410 BSB DDR2 Design Creation Using 8.2i SP1 EDK Base System Builder (BSB) April

Transcription

1 ML40 BSB DDR2 Design Creation Using 8.2i SP EDK Base System Builder (BSB) April 2007

2 Overview Hardware Setup Software Requirements Create a BSB DDR2 System Build (BSB) in EDK Generate a Bitstream Transfer the Bitstream onto the FPGA Loading a Bootloop into the Block RAM

3 ML40 BSB DDR2 Hardware The ML40 BSB DDR2 design hardware includes: 64 KB BRAM DDR2 Interface (256 MB) UART Interrupt Controller PLB2OPB Bridge PLB and OPB Arbiters Networking

4 Additional Setup Details Refer to ml40_overview_setup.ppt for details on: Software Requirements ML40 Board Setup Equipment and Cables Software Network Terminal Programs This presentation requires the N- Baud terminal setup

5 Hardware Setup Connect the Xilinx Parallel Cable IV (PC4) to the ML40 board Connect the RS232 null modem cable to the ML40 board

6 ISE Software Requirement Xilinx ISE 8.2i SP2 software

7 EDK Software Requirement Xilinx EDK 8.2i SP software

8 Software Setup Start the Terminal Program:

9 Run Xilinx Platform Studio Open Xilinx Platform Studio Select File New Project ()

10 Run Xilinx Platform Studio Select Base System Builder wizard ()

11 Create Base System Build Enter the path and file name: C:\ml40_bsb_ddr2_design\ml40_bsb_ddr2.xmp () Click OK (2) 2

12 Create Base System Build Create a new design () Click Next (2) 2

13 Create Base System Build Select (): Board Vendor: Xilinx Board Name: ML40 Board Revision: B Click Next (2) 2 Note: This is also the correct setting for RevC and RevD boards

14 Create Base System Build Select the PowerPC processor () Click Next (2) 2

15 Create Base System Build Change the Processor Clock Frequency to 300 MHz () Click Next (2) 2

16 Create Base 2 System Build De-select RS232_Uart_ () RS232_Uart_2 Select OPB UART6550 Peripheral (2) Select Use Interrupt (3) Click Next (4) 3 4

17 Create Base 2 3 System Build Deselect DDR_SDRAM_32Mx64 () SPI_EEPROM (2) LEDs_8Bit (3) LCD_OPTIONAL (4) Click Next (5) 4 5

18 Create Base 2 3 System Build Deselect: pci_arbiter_0 () PCI32_BRIDGE (2) SysACE_CompactFlash (3) IIC_BUS (4) Click Next (5) 4 5

19 Create Base 2 System Build De-select Ethernet_MAC () TriMode_MAC_GMII (2) Select Use Interrupt (3) Click Next (4) 3 4

20 Create Base System Build Select DDR2_SRAM_32x64 () Click Next (2) 2

21 Create Base System Build PLB BRAM IF CNTLR Change the memory size from 6 KB to 64 KB () Click Next (2) 2

22 Create Base System Build Leave this window as is Click Next ()

23 Create Base System Build Leave this window as is Click Next ()

24 Create Base System Build Leave this window as is Click Next ()

25 Create Base System Build Create the Base System Build Click Generate ()

26 Create Base System Build Finalize the creation of the Base System Build Click Finish ()

27 Create Base System Build Before generating a bitstream the MHS file () must be updated

28 Update MHS Open ml40_bsb_ddr2_system.mhs Add this parameter to the plb_v34 (): PARAMETER C_NUM_OPBCLK_PLB2OPB_REARB = 00

29 Update MHS Add this parameter to the plb_ddr2 (): PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT =

30 Update TestApp Open TestApp_Peripheral/src/xtemac_example.h Change the PHY Address from 0 to 7 #define TEMAC_PHY_ID 7 See Answer Record for details

31 Update TestApp Open TestApp_Peripheral/src/xtemac_example_util.c Add this line twice as shown here (): usleep(000000); See Answer Record for details

32 Generate Bitstream Generate the libraries needed to create the bitstream Select Software Generate Libraries and BSPs ()

33 Generate Bitstream Compile the TestApp project and create an executable (executable.elf) Select Software Build All User Applications ()

34 Generate Bitstream Create the hardware design, ml40_bsb_system.bit, that is located in <project directory> /implementation Select Hardware Generate Bitstream () (Takes roughly 40 minutes)

35 Download the Bitstream Initialize the compiled TestApp project in the block RAM and download the new bitstream (download.bit) Select Device Configuration Download Bitstream ()

36 Download the Bitstream View the output of a successful bitstream download in the terminal window

37 Loading Bootloop into BRAM A concatenated software/hardware file, known as an ACE file, is useful for loading large programs, such as a Linux, VxWorks, or U-Boot into the external memory A bootloop program must be used to occupy the processor until the software is loaded into memory The following pages show how to initialize a bootloop program into block RAM and to test its existence

38 Loading Bootloop into BRAM Right-click the TestApp_Memory project and de-select Mark to Initialize BRAMs () This will prevent the TestApp program from being inserted into the block RAM when the new bitstream is created

39 Loading Bootloop into BRAM Right-click the ppc405_0_bootloop project and select Mark to Initialize BRAMs () Now the bootloop will be instantiated into block RAM rather than the TestApp_Memory project

40 Loading Bootloop into BRAM Update the bitstream (download.bit) with a bootloop ELF file (ppc405_0.elf) Select Device Configuration Update Bitstream ()

41 Loading Bootloop into BRAM Load the new design onto the FPGA and load the bootloop program into the block RAM Select Device Configuration Download Bitstream ()

42 Loading Bootloop into BRAM A memory read can be executed to test if bootloop was successfully loaded Select Debug Launch XMD () Select ppc405_0 (2) 2

43 XMD Setup The first time XMD runs on a project, the options must be set Click OK () Click Save (2) 2

44 Loading Bootloop into BRAM XMD opens and connects to the processor, using the default options

45 Loading Bootloop into BRAM To execute a memory read, type mrd 0xfffffffc This will read the memory address at the reset vector; the value should be 0x as shown below

46 Loading Bootloop into BRAM Make a copy of the updated bitstream (download.bit) and rename it ml40_bsb_bootloop.bit This bootloop bitstream will be used in future designs, such as the Linux and VxWorks builds

47 Appendix Adding the Null Tiles

48 Null Tiles AR 2340 Needed to preserve unused MGTs for future designs Step Download the null tile pcore Unzip this to the <design dir>/pcores

49 Null Tiles Step 2 Update the UCF file AR 2340 has the UCF File changes for the Virtex-4 FX60-FF52 Paste these constraints into your <Design dir>/data/ml40_bsb_system.ucf file:

50 Null Tiles Step 3 Update the MHS file AR 2340 has the MHS file changes for the Virtex-4 FX60-FF52 Paste these lines (ports and pcore instantiations) into your <Design dir>/ml40_bsb_system.mhs file:

51 Null Tiles Step 4 Recompile the bitstream

52 Available Documentation Platform Studio Documentation Embedded Development Kit (EDK) Resources OS and Libraries Document Collection ML40 ML40 User's Guide ML40 Overview ML40 Schematics